diff options
| author | Kerwin Wan <kerwinw@nvidia.com> | 2013-11-08 10:07:56 +0800 |
|---|---|---|
| committer | Chao Xu <cxu@nvidia.com> | 2013-11-08 16:09:36 -0800 |
| commit | 645571550662785c019838ea32852b8dad97a068 (patch) | |
| tree | 27862317b157de8597ba1b9a307f402176d993d1 /drivers/video/tegra/dc/sor_regs.h | |
| parent | 5e76c56a4a19291f15afce2c482c117d560039eb (diff) | |
video: tegra: dc: fix dp link configuration
1. Correct the bandwidth setting.
2. Fix some registers settings.
Change-Id: I1baf59e3582b4b13049a8f6224ed0aa6450ac470
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/325908
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/sor_regs.h')
| -rw-r--r-- | drivers/video/tegra/dc/sor_regs.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/sor_regs.h b/drivers/video/tegra/dc/sor_regs.h index b765451e42fd..f375b63d31e9 100644 --- a/drivers/video/tegra/dc/sor_regs.h +++ b/drivers/video/tegra/dc/sor_regs.h @@ -264,6 +264,13 @@ #define NV_SOR_PLL1_TERM_COMPOUT_SHIFT (15) #define NV_SOR_PLL1_TERM_COMPOUT_LOW (0 << 15) #define NV_SOR_PLL1_TERM_COMPOUT_HIGH (1 << 15) +#define NV_SOR_PLL1_TMDS_TERMADJ_SHIFT (9) +#define NV_SOR_PLL1_TMDS_TERMADJ_OHM500 (8 << 9) +#define NV_SOR_PLL1_LVDSCM_SHIFT (24) +#define NV_SOR_PLL1_LOADADJ_SHIFT (20) +#define NV_SOR_PLL1_RBR_LOADADJ (3 << 20) +#define NV_SOR_PLL1_HBR_LOADADJ (4 << 20) +#define NV_SOR_PLL1_HBR2_LOADADJ (6 << 20) #define NV_SOR_PLL2 (0x19) #define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT (0) #define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0) @@ -705,6 +712,8 @@ #define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16) #define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16) #define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT (8) +#define NV_SOR_DP_PADCTL_TX_PU_VALUE_RBR_HBR (0x10 << 8) +#define NV_SOR_DP_PADCTL_TX_PU_VALUE_HBR2 (0x20 << 8) #define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8) #define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT (7) #define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) |