video: tegra: host: CPU reg read to use power management

CPU register read did not have access to nvhost power management.
Due to this only modules that were powered on previously are actually
accessible via the API. This patch refactors CPU access to:

 * Move mutexes to sync point, as they're sync point operations
 * Move register address spaces to nvhost_device
 * Call register read with access to the respective nvhost_device
 * Initialize module completely at boot-up so that register reads
   can be done without an initialized channel.

Reviewed-on: http://git-master/r/75275

Change-Id: I0db38cef7b2cd92dc64e7f55d227bdd2fdb8f752
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77764
Reviewed-by: Automatic_Commit_Validation_User

20 files changed, 289 insertions, 361 deletions

diff --git a/drivers/video/tegra/host/Makefile b/drivers/video/tegra/host/Makefile
index 4fd19ac809b8..be2be9211731 100644
--- a/drivers/video/tegra/host/Makefile
+++ b/drivers/video/tegra/host/Makefile
@@ -3,12 +3,12 @@ nvhost-objs = \
 	nvhost_acm.o \
 	nvhost_syncpt.o \
 	nvhost_cdma.o \
-	nvhost_cpuaccess.o \
 	nvhost_intr.o \
 	nvhost_channel.o \
 	nvhost_job.o \
 	dev.o \
 	bus.o \
+	bus_client.o \
 	debug.o
 
 obj-$(CONFIG_TEGRA_GRHOST) += mpe/
diff --git a/drivers/video/tegra/host/bus_client.c b/drivers/video/tegra/host/bus_client.c
new file mode 100644
index 000000000000..3d455298af8e
--- /dev/null
+++ b/drivers/video/tegra/host/bus_client.c
@@ -0,0 +1,53 @@
+/*
+ * drivers/video/tegra/host/bus_client.c
+ *
+ * Tegra Graphics Host Client Module
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include "bus_client.h"
+#include "dev.h"
+#include <linux/string.h>
+
+void nvhost_read_module_regs(struct nvhost_device *ndev,
+			u32 offset, int count, u32 *values)
+{
+	void __iomem *p = ndev->aperture + offset;
+
+	nvhost_module_busy(ndev);
+	while (count--) {
+		*(values++) = readl(p);
+		p += 4;
+	}
+	rmb();
+	nvhost_module_idle(ndev);
+}
+
+void nvhost_write_module_regs(struct nvhost_device *ndev,
+			u32 offset, int count, const u32 *values)
+{
+	void __iomem *p = ndev->aperture + offset;
+
+	nvhost_module_busy(ndev);
+	while (count--) {
+		writel(*(values++), p);
+		p += 4;
+	}
+	wmb();
+	nvhost_module_idle(ndev);
+}
diff --git a/drivers/video/tegra/host/bus_client.h b/drivers/video/tegra/host/bus_client.h
new file mode 100644
index 000000000000..dc1b6be1d8dc
--- /dev/null
+++ b/drivers/video/tegra/host/bus_client.h
@@ -0,0 +1,35 @@
+/*
+ * drivers/video/tegra/host/bus_client.h
+ *
+ * Tegra Graphics Host Cpu Register Access
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __NVHOST_BUS_CLIENT_H
+#define __NVHOST_BUS_CLIENT_H
+
+#include <linux/types.h>
+struct nvhost_device;
+
+void nvhost_read_module_regs(struct nvhost_device *ndev,
+			u32 offset, int count, u32 *values);
+
+void nvhost_write_module_regs(struct nvhost_device *ndev,
+			u32 offset, int count, const u32 *values);
+
+#endif
diff --git a/drivers/video/tegra/host/chip_support.h b/drivers/video/tegra/host/chip_support.h
index 16ec7bfc7533..17c2116b14cf 100644
--- a/drivers/video/tegra/host/chip_support.h
+++ b/drivers/video/tegra/host/chip_support.h
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Chip Support
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,7 +35,6 @@ struct nvhost_cdma;
 struct nvhost_intr;
 struct push_buffer;
 struct nvhost_syncpt;
-struct nvhost_cpuaccess;
 struct nvhost_master;
 struct dentry;
 struct nvhost_job;
@@ -114,6 +113,10 @@ struct nvhost_chip_support {
 				  int num_waitchk);
 		void (*debug)(struct nvhost_syncpt *);
 		const char * (*name)(struct nvhost_syncpt *, u32 id);
+		int (*mutex_try_lock)(struct nvhost_syncpt *,
+				      unsigned int idx);
+		void (*mutex_unlock)(struct nvhost_syncpt *,
+				     unsigned int idx);
 	} syncpt;
 
 	struct {
@@ -128,14 +131,6 @@ struct nvhost_chip_support {
 		void (*free_host_general_irq)(struct nvhost_intr *);
 		int (*request_syncpt_irq)(struct nvhost_intr_syncpt *syncpt);
 	} intr;
-
-	struct {
-		int (*mutex_try_lock)(struct nvhost_cpuaccess *,
-				      unsigned int idx);
-		void (*mutex_unlock)(struct nvhost_cpuaccess *,
-				     unsigned int idx);
-	} cpuaccess;
-
 };
 
 #endif /* _NVHOST_CHIP_SUPPORT_H_ */
diff --git a/drivers/video/tegra/host/dev.c b/drivers/video/tegra/host/dev.c
index ea502442aeef..be8fc987e7cc 100644
--- a/drivers/video/tegra/host/dev.c
+++ b/drivers/video/tegra/host/dev.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Driver Entrypoint
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
  */
 
 #include "dev.h"
+#include "bus_client.h"
 
 #include <linux/slab.h>
 #include <linux/string.h>
@@ -529,9 +530,9 @@ static int nvhost_ctrlrelease(struct inode *inode, struct file *filp)
 	filp->private_data = NULL;
 	if (priv->mod_locks[0])
 		nvhost_module_idle(priv->dev->dev);
-	for (i = 1; i < priv->dev->nb_mlocks; i++)
+	for (i = 1; i < priv->dev->syncpt.nb_mlocks; i++)
 		if (priv->mod_locks[i])
-			nvhost_mutex_unlock(&priv->dev->cpuaccess, i);
+			nvhost_mutex_unlock(&priv->dev->syncpt, i);
 	kfree(priv->mod_locks);
 	kfree(priv);
 	return 0;
@@ -546,7 +547,7 @@ static int nvhost_ctrlopen(struct inode *inode, struct file *filp)
 	trace_nvhost_ctrlopen(host->dev->name);
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	mod_locks = kzalloc(sizeof(u32)*host->nb_mlocks, GFP_KERNEL);
+	mod_locks = kzalloc(sizeof(u32) * host->syncpt.nb_mlocks, GFP_KERNEL);
 
 	if (!(priv && mod_locks)) {
 		kfree(priv);
@@ -605,7 +606,7 @@ static int nvhost_ioctl_ctrl_module_mutex(
 	struct nvhost_ctrl_module_mutex_args *args)
 {
 	int err = 0;
-	if (args->id >= ctx->dev->nb_mlocks ||
+	if (args->id >= ctx->dev->syncpt.nb_mlocks ||
 	    args->lock > 1)
 		return -EINVAL;
 
@@ -614,51 +615,73 @@ static int nvhost_ioctl_ctrl_module_mutex(
 		if (args->id == 0)
 			nvhost_module_busy(ctx->dev->dev);
 		else
-			err = nvhost_mutex_try_lock(&ctx->dev->cpuaccess, args->id);
+			err = nvhost_mutex_try_lock(&ctx->dev->syncpt,
+					args->id);
 		if (!err)
 			ctx->mod_locks[args->id] = 1;
 	} else if (!args->lock && ctx->mod_locks[args->id]) {
 		if (args->id == 0)
 			nvhost_module_idle(ctx->dev->dev);
 		else
-			nvhost_mutex_unlock(&ctx->dev->cpuaccess, args->id);
+			nvhost_mutex_unlock(&ctx->dev->syncpt, args->id);
 		ctx->mod_locks[args->id] = 0;
 	}
 	return err;
 }
 
+static struct nvhost_device *get_ndev_by_moduleid(struct nvhost_master *host,
+		u32 id)
+{
+	int i;
+
+	for (i = 0; i < host->nb_channels; i++) {
+		struct nvhost_device *ndev = host->channels[i].dev;
+		if (id == ndev->moduleid)
+			return ndev;
+	}
+	return NULL;
+}
+
 static int nvhost_ioctl_ctrl_module_regrdwr(
 	struct nvhost_ctrl_userctx *ctx,
 	struct nvhost_ctrl_module_regrdwr_args *args)
 {
 	u32 num_offsets = args->num_offsets;
 	u32 *offsets = args->offsets;
-	void *values = args->values;
+	u32 *values = args->values;
 	u32 vals[64];
+	struct nvhost_device *ndev;
 
 	trace_nvhost_ioctl_ctrl_module_regrdwr(args->id,
 			args->num_offsets, args->write);
-	if (!(args->id < ctx->dev->nb_modules) ||
-	    (num_offsets == 0))
+	/* Check that there is something to read and that block size is
+	 * u32 aligned */
+	if (num_offsets == 0 || args->block_size & 3)
+		return -EINVAL;
+
+	ndev = get_ndev_by_moduleid(ctx->dev, args->id);
+	if (!ndev)
 		return -EINVAL;
 
 	while (num_offsets--) {
-		u32 remaining = args->block_size;
+		int remaining = args->block_size >> 2;
 		u32 offs;
 		if (get_user(offs, offsets))
 			return -EFAULT;
 		offsets++;
 		while (remaining) {
-			u32 batch = min(remaining, 64*sizeof(u32));
+			int batch = min(remaining, 64);
 			if (args->write) {
-				if (copy_from_user(vals, values, batch))
+				if (copy_from_user(vals, values,
+							batch*sizeof(u32)))
 					return -EFAULT;
-				nvhost_write_module_regs(&ctx->dev->cpuaccess,
-							args->id, offs, batch, vals);
+				nvhost_write_module_regs(ndev,
+						offs, batch, vals);
 			} else {
-				nvhost_read_module_regs(&ctx->dev->cpuaccess,
-							args->id, offs, batch, vals);
-				if (copy_to_user(values, vals, batch))
+				nvhost_read_module_regs(ndev,
+						offs, batch, vals);
+				if (copy_to_user(values, vals,
+							batch*sizeof(u32)))
 					return -EFAULT;
 			}
 			remaining -= batch;
@@ -829,14 +852,8 @@ static void nvhost_remove_chip_support(struct nvhost_master *host)
 	kfree(host->intr.syncpt);
 	host->intr.syncpt = 0;
 
-	kfree(host->cpuaccess.regs);
-	host->cpuaccess.regs = 0;
-
-	kfree(host->cpuaccess.reg_mem);
-	host->cpuaccess.reg_mem = 0;
-
-	kfree(host->cpuaccess.lock_counts);
-	host->cpuaccess.lock_counts = 0;
+	kfree(host->syncpt.lock_counts);
+	host->syncpt.lock_counts = 0;
 }
 
 static int __devinit nvhost_init_chip_support(struct nvhost_master *host)
@@ -873,19 +890,12 @@ static int __devinit nvhost_init_chip_support(struct nvhost_master *host)
 	host->intr.syncpt = kzalloc(sizeof(struct nvhost_intr_syncpt) *
 				    host->syncpt.nb_pts, GFP_KERNEL);
 
-	host->cpuaccess.reg_mem = kzalloc(sizeof(struct resource *) *
-				       host->nb_modules, GFP_KERNEL);
-
-	host->cpuaccess.regs = kzalloc(sizeof(void __iomem *) *
-				       host->nb_modules, GFP_KERNEL);
-
-	host->cpuaccess.lock_counts = kzalloc(sizeof(atomic_t) *
-				       host->nb_mlocks, GFP_KERNEL);
+	host->syncpt.lock_counts = kzalloc(sizeof(atomic_t) *
+				       host->syncpt.nb_mlocks, GFP_KERNEL);
 
 	if (!(host->channels && host->syncpt.min_val &&
 	      host->syncpt.max_val && host->syncpt.base_val &&
-	      host->intr.syncpt && host->cpuaccess.reg_mem &&
-	      host->cpuaccess.regs && host->cpuaccess.lock_counts)) {
+	      host->intr.syncpt && host->syncpt.lock_counts)) {
 		/* frees happen in the support removal phase */
 		return -ENOMEM;
 	}
@@ -957,21 +967,14 @@ static int __devinit nvhost_probe(struct platform_device *pdev)
 	/*  Give pointer to host1x via driver */
 	nvhost_set_drvdata(&hostdev, host);
 
+	BUG_ON(!host_channel_op(host).init);
 	for (i = 0; i < host->nb_channels; i++) {
 		struct nvhost_channel *ch = &host->channels[i];
-		BUG_ON(!host_channel_op(host).init);
-		err = host_channel_op(host).init(ch, host, i);
-		if (err < 0) {
-			dev_err(&pdev->dev, "failed to init channel %d\n", i);
+		err = nvhost_channel_init(ch, host, i);
+		if (err)
 			goto fail;
-		}
-		ch->dev->channel = ch;
 	}
 
-	err = nvhost_cpuaccess_init(&host->cpuaccess, pdev);
-	if (err)
-		goto fail;
-
 	err = nvhost_intr_init(&host->intr, intr1->start, intr0->start);
 	if (err)
 		goto fail;
@@ -986,7 +989,7 @@ static int __devinit nvhost_probe(struct platform_device *pdev)
 
 	for (i = 0; i < host->nb_channels; i++) {
 		struct nvhost_channel *ch = &host->channels[i];
-		nvhost_module_preinit(ch->dev);
+		nvhost_module_init(ch->dev);
 	}
 
 	platform_set_drvdata(pdev, host);
diff --git a/drivers/video/tegra/host/dev.h b/drivers/video/tegra/host/dev.h
index 635b0c90ccf9..7b6fd99746dc 100644
--- a/drivers/video/tegra/host/dev.h
+++ b/drivers/video/tegra/host/dev.h
@@ -26,7 +26,6 @@
 #include "nvhost_acm.h"
 #include "nvhost_syncpt.h"
 #include "nvhost_intr.h"
-#include "nvhost_cpuaccess.h"
 #include "nvhost_channel.h"
 #include "chip_support.h"
 
@@ -43,13 +42,10 @@ struct nvhost_master {
 	struct device *ctrl;
 	struct nvhost_syncpt syncpt;
 	struct nvmap_client *nvmap;
-	struct nvhost_cpuaccess cpuaccess;
-	u32 nb_mlocks;
 	struct nvhost_intr intr;
 	struct nvhost_device *dev;
 	struct nvhost_channel *channels;
 	u32 nb_channels;
-	u32 nb_modules;
 
 	u32 sync_queue_size;
 
diff --git a/drivers/video/tegra/host/host1x/Makefile b/drivers/video/tegra/host/host1x/Makefile
index ba59d870d15b..c3214ffe147b 100644
--- a/drivers/video/tegra/host/host1x/Makefile
+++ b/drivers/video/tegra/host/host1x/Makefile
@@ -4,7 +4,6 @@ EXTRA_CFLAGS += -Idrivers/video/tegra/host
 
 nvhost-host1x-objs  = \
 	host1x_syncpt.o \
-	host1x_cpuaccess.o \
 	host1x_channel.o \
 	host1x_intr.o \
 	host1x_cdma.o \
diff --git a/drivers/video/tegra/host/host1x/host1x_cdma.c b/drivers/video/tegra/host/host1x/host1x_cdma.c
index e5a72514c071..65a72801528f 100644
--- a/drivers/video/tegra/host/host1x/host1x_cdma.c
+++ b/drivers/video/tegra/host/host1x/host1x_cdma.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Command DMA
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
  */
 
 #include <linux/slab.h>
+#include <linux/platform_device.h>
 #include "nvhost_cdma.h"
 #include "dev.h"
 
diff --git a/drivers/video/tegra/host/host1x/host1x_cpuaccess.c b/drivers/video/tegra/host/host1x/host1x_cpuaccess.c
deleted file mode 100644
index 927f4ca85bdc..000000000000
--- a/drivers/video/tegra/host/host1x/host1x_cpuaccess.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * drivers/video/tegra/host/host1x/host1x_cpuaccess.c
- *
- * Tegra Graphics Host Cpu Register Access
- *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include "nvhost_cpuaccess.h"
-#include "dev.h"
-#include "host1x_hardware.h"
-
-static int t20_cpuaccess_mutex_try_lock(struct nvhost_cpuaccess *ctx,
-					unsigned int idx)
-{
-	struct nvhost_master *dev = cpuaccess_to_dev(ctx);
-	void __iomem *sync_regs = dev->sync_aperture;
-	/* mlock registers returns 0 when the lock is aquired.
-	 * writing 0 clears the lock. */
-	return !!readl(sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
-}
-
-static void t20_cpuaccess_mutex_unlock(struct nvhost_cpuaccess *ctx,
-				       unsigned int idx)
-{
-	struct nvhost_master *dev = cpuaccess_to_dev(ctx);
-	void __iomem *sync_regs = dev->sync_aperture;
-
-	writel(0, sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
-}
-
-int nvhost_init_t20_cpuaccess_support(struct nvhost_master *host)
-{
-	host->nb_modules = NVHOST_MODULE_NUM;
-
-	host->op.cpuaccess.mutex_try_lock = t20_cpuaccess_mutex_try_lock;
-	host->op.cpuaccess.mutex_unlock = t20_cpuaccess_mutex_unlock;
-
-	return 0;
-}
diff --git a/drivers/video/tegra/host/host1x/host1x_syncpt.c b/drivers/video/tegra/host/host1x/host1x_syncpt.c
index 21390fca7e9d..622c8e049a7b 100644
--- a/drivers/video/tegra/host/host1x/host1x_syncpt.c
+++ b/drivers/video/tegra/host/host1x/host1x_syncpt.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Syncpoints for HOST1X
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
  */
 
 #include <linux/nvhost_ioctl.h>
+#include <linux/platform_device.h>
 #include "nvhost_syncpt.h"
 #include "dev.h"
 #include "host1x_syncpt.h"
@@ -220,6 +221,23 @@ static void t20_syncpt_debug(struct nvhost_syncpt *sp)
 	}
 }
 
+static int syncpt_mutex_try_lock(struct nvhost_syncpt *sp,
+		unsigned int idx)
+{
+	void __iomem *sync_regs = syncpt_to_dev(sp)->sync_aperture;
+	/* mlock registers returns 0 when the lock is aquired.
+	 * writing 0 clears the lock. */
+	return !!readl(sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
+}
+
+static void syncpt_mutex_unlock(struct nvhost_syncpt *sp,
+	       unsigned int idx)
+{
+	void __iomem *sync_regs = syncpt_to_dev(sp)->sync_aperture;
+
+	writel(0, sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
+}
+
 int host1x_init_syncpt_support(struct nvhost_master *host)
 {
 
@@ -235,10 +253,13 @@ int host1x_init_syncpt_support(struct nvhost_master *host)
 	host->op.syncpt.wait_check = t20_syncpt_wait_check;
 	host->op.syncpt.debug = t20_syncpt_debug;
 	host->op.syncpt.name = t20_syncpt_name;
+	host->op.syncpt.mutex_try_lock = syncpt_mutex_try_lock;
+	host->op.syncpt.mutex_unlock = syncpt_mutex_unlock;
 
 	host->syncpt.nb_pts = NV_HOST1X_SYNCPT_NB_PTS;
 	host->syncpt.nb_bases = NV_HOST1X_SYNCPT_NB_BASES;
 	host->syncpt.client_managed = NVSYNCPTS_CLIENT_MANAGED;
+	host->syncpt.nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
 
 	return 0;
 }
diff --git a/drivers/video/tegra/host/nvhost_acm.c b/drivers/video/tegra/host/nvhost_acm.c
index 8d44d87769d1..a2386a257c8f 100644
--- a/drivers/video/tegra/host/nvhost_acm.c
+++ b/drivers/video/tegra/host/nvhost_acm.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Automatic Clock Management
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,6 +28,7 @@
 #include <linux/err.h>
 #include <linux/device.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
 #include <mach/powergate.h>
 #include <mach/clk.h>
 #include <mach/hardware.h>
@@ -339,11 +340,12 @@ void nvhost_module_remove_client(struct nvhost_device *dev, void *priv)
 	mutex_unlock(&client_list_lock);
 }
 
-void nvhost_module_preinit(struct nvhost_device *dev)
+int nvhost_module_init(struct nvhost_device *dev)
 {
 	int i = 0;
 
 	/* initialize clocks to known state */
+	INIT_LIST_HEAD(&dev->client_list);
 	while (dev->clocks[i].name && i < NVHOST_MODULE_MAX_CLOCKS) {
 		char devname[MAX_DEVID_LENGTH];
 		long rate = dev->clocks[i].default_rate;
@@ -357,31 +359,7 @@ void nvhost_module_preinit(struct nvhost_device *dev)
 		clk_enable(c);
 		clk_set_rate(c, rate);
 		clk_disable(c);
-		i++;
-	}
-
-	if (dev->can_powergate) {
-		do_powergate_locked(dev->powergate_ids[0]);
-		do_powergate_locked(dev->powergate_ids[1]);
-	} else {
-		do_unpowergate_locked(dev->powergate_ids[0]);
-		do_unpowergate_locked(dev->powergate_ids[1]);
-	}
-}
-
-int nvhost_module_init(struct nvhost_device *dev)
-{
-	int i = 0;
-
-	nvhost_module_preinit(dev);
-
-	INIT_LIST_HEAD(&dev->client_list);
-	while (dev->clocks[i].name && i < NVHOST_MODULE_MAX_CLOCKS) {
-		char devname[MAX_DEVID_LENGTH];
-
-		snprintf(devname, MAX_DEVID_LENGTH, "tegra_%s", dev->name);
-		dev->clk[i] = clk_get_sys(devname, dev->clocks[i].name);
-		BUG_ON(IS_ERR_OR_NULL(dev->clk[i]));
+		dev->clk[i] = c;
 		i++;
 	}
 	dev->num_clks = i;
@@ -390,13 +368,16 @@ int nvhost_module_init(struct nvhost_device *dev)
 	init_waitqueue_head(&dev->idle_wq);
 	INIT_DELAYED_WORK(&dev->powerstate_down, powerstate_down_handler);
 
-	if (dev->can_powergate)
+	/* power gate units that we can power gate */
+	if (dev->can_powergate) {
+		do_powergate_locked(dev->powergate_ids[0]);
+		do_powergate_locked(dev->powergate_ids[1]);
 		dev->powerstate = NVHOST_POWER_STATE_POWERGATED;
-	else
+	} else {
+		do_unpowergate_locked(dev->powergate_ids[0]);
+		do_unpowergate_locked(dev->powergate_ids[1]);
 		dev->powerstate = NVHOST_POWER_STATE_CLOCKGATED;
-
-	if (dev->init)
-		dev->init(dev);
+	}
 
 	return 0;
 }
@@ -425,8 +406,8 @@ static void debug_not_idle(struct nvhost_master *host)
 		mutex_unlock(&dev->lock);
 	}
 
-	for (i = 0; i < host->nb_mlocks; i++) {
-		int c = atomic_read(&host->cpuaccess.lock_counts[i]);
+	for (i = 0; i < host->syncpt.nb_mlocks; i++) {
+		int c = atomic_read(&host->syncpt.lock_counts[i]);
 		if (c) {
 			dev_warn(&host->pdev->dev,
 				"tegra_grhost: lock id %d: refcnt %d\n",
diff --git a/drivers/video/tegra/host/nvhost_acm.h b/drivers/video/tegra/host/nvhost_acm.h
index 3e1636f44176..06a11ff840f2 100644
--- a/drivers/video/tegra/host/nvhost_acm.h
+++ b/drivers/video/tegra/host/nvhost_acm.h
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Automatic Clock Management
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -30,7 +30,6 @@
 #include <linux/nvhost.h>
 
 /* Sets clocks and powergating state for a module */
-void nvhost_module_preinit(struct nvhost_device *ndev);
 int nvhost_module_init(struct nvhost_device *ndev);
 void nvhost_module_deinit(struct nvhost_device *dev);
 int nvhost_module_suspend(struct nvhost_device *dev, bool system_suspend);
diff --git a/drivers/video/tegra/host/nvhost_channel.c b/drivers/video/tegra/host/nvhost_channel.c
index 6d39eba643c4..c7b0c82b3e45 100644
--- a/drivers/video/tegra/host/nvhost_channel.c
+++ b/drivers/video/tegra/host/nvhost_channel.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Channel
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,6 +32,57 @@
 
 #define NVHOST_CHANNEL_LOW_PRIO_MAX_WAIT 50
 
+int nvhost_channel_init(struct nvhost_channel *ch,
+		struct nvhost_master *dev, int index)
+{
+	int err;
+	struct nvhost_device *ndev;
+	struct resource *r = NULL;
+	void __iomem *regs = NULL;
+	struct resource *reg_mem = NULL;
+
+	/* Link nvhost_device to nvhost_channel */
+	err = host_channel_op(dev).init(ch, dev, index);
+	if (err < 0) {
+		dev_err(&dev->dev->dev, "failed to init channel %d\n",
+				index);
+		return err;
+	}
+	ndev = ch->dev;
+	ndev->channel = ch;
+
+	/* Map IO memory related to nvhost_device */
+	if (ndev->moduleid != NVHOST_MODULE_NONE) {
+		/* First one is host1x - skip that */
+		r = platform_get_resource(dev->pdev,
+				IORESOURCE_MEM, ndev->moduleid + 1);
+		if (!r)
+			goto fail;
+
+		reg_mem = request_mem_region(r->start,
+				resource_size(r), ndev->name);
+		if (!reg_mem)
+			goto fail;
+
+		regs = ioremap(r->start, resource_size(r));
+		if (!regs)
+			goto fail;
+
+		ndev->reg_mem = reg_mem;
+		ndev->aperture = regs;
+	}
+	return 0;
+
+fail:
+	if (reg_mem)
+		release_mem_region(r->start, resource_size(r));
+	if (regs)
+		iounmap(regs);
+	dev_err(&ndev->dev, "failed to get register memory\n");
+	return -ENXIO;
+
+}
+
 int nvhost_channel_submit(struct nvhost_job *job)
 {
 	/* Low priority submits wait until sync queue is empty. Ignores result
@@ -49,12 +100,9 @@ struct nvhost_channel *nvhost_getchannel(struct nvhost_channel *ch)
 	int err = 0;
 	mutex_lock(&ch->reflock);
 	if (ch->refcount == 0) {
-		err = nvhost_module_init(ch->dev);
-		if (!err) {
-			err = nvhost_cdma_init(&ch->cdma);
-			if (err)
-				nvhost_module_deinit(ch->dev);
-		}
+		if (ch->dev->init)
+			ch->dev->init(ch->dev);
+		err = nvhost_cdma_init(&ch->cdma);
 	} else if (ch->dev->exclusive) {
 		err = -EBUSY;
 	}
@@ -89,7 +137,7 @@ void nvhost_putchannel(struct nvhost_channel *ch, struct nvhost_hwctx *ctx)
 	if (ch->refcount == 1) {
 		channel_cdma_op(ch).stop(&ch->cdma);
 		nvhost_cdma_deinit(&ch->cdma);
-		nvhost_module_deinit(ch->dev);
+		nvhost_module_suspend(ch->dev, false);
 	}
 	ch->refcount--;
 	mutex_unlock(&ch->reflock);
diff --git a/drivers/video/tegra/host/nvhost_cpuaccess.c b/drivers/video/tegra/host/nvhost_cpuaccess.c
deleted file mode 100644
index 0c7d0a4a98dc..000000000000
--- a/drivers/video/tegra/host/nvhost_cpuaccess.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * drivers/video/tegra/host/nvhost_cpuaccess.c
- *
- * Tegra Graphics Host Cpu Register Access
- *
- * Copyright (c) 2010, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include "nvhost_cpuaccess.h"
-#include "dev.h"
-#include <linux/string.h>
-
-int nvhost_cpuaccess_init(struct nvhost_cpuaccess *ctx,
-			struct platform_device *pdev)
-{
-	struct nvhost_master *host = cpuaccess_to_dev(ctx);
-	int i;
-
-	for (i = 0; i < host->nb_modules; i++) {
-		struct resource *mem;
-		mem = platform_get_resource(pdev, IORESOURCE_MEM, i+1);
-		if (!mem) {
-			dev_err(&pdev->dev, "missing module memory resource\n");
-			return -ENXIO;
-		}
-		ctx->reg_mem[i] = mem;
-		ctx->regs[i] = ioremap(mem->start, resource_size(mem));
-		if (!ctx->regs[i]) {
-			dev_err(&pdev->dev, "failed to map module registers\n");
-			return -ENXIO;
-		}
-	}
-
-	return 0;
-}
-
-void nvhost_cpuaccess_deinit(struct nvhost_cpuaccess *ctx)
-{
-	struct nvhost_master *host = cpuaccess_to_dev(ctx);
-	int i;
-
-	for (i = 0; i < host->nb_modules; i++) {
-		iounmap(ctx->regs[i]);
-		release_resource(ctx->reg_mem[i]);
-	}
-}
-
-int nvhost_mutex_try_lock(struct nvhost_cpuaccess *ctx, unsigned int idx)
-{
-	struct nvhost_master *dev = cpuaccess_to_dev(ctx);
-	u32 reg;
-	BUG_ON(!cpuaccess_op(ctx).mutex_try_lock);
-
-	nvhost_module_busy(dev->dev);
-	reg = cpuaccess_op(ctx).mutex_try_lock(ctx, idx);
-	if (reg) {
-		nvhost_module_idle(dev->dev);
-		return -EBUSY;
-	}
-	atomic_inc(&ctx->lock_counts[idx]);
-	return 0;
-}
-
-void nvhost_mutex_unlock(struct nvhost_cpuaccess *ctx, unsigned int idx)
-{
-	struct nvhost_master *dev = cpuaccess_to_dev(ctx);
-	BUG_ON(!cpuaccess_op(ctx).mutex_unlock);
-
-	cpuaccess_op(ctx).mutex_unlock(ctx, idx);
-	nvhost_module_idle(dev->dev);
-	atomic_dec(&ctx->lock_counts[idx]);
-}
-
-void nvhost_read_module_regs(struct nvhost_cpuaccess *ctx, u32 module,
-			u32 offset, size_t size, void *values)
-{
-	struct nvhost_master *dev = cpuaccess_to_dev(ctx);
-	void __iomem *p = ctx->regs[module] + offset;
-	u32 *out = (u32 *)values;
-	BUG_ON(size & 3);
-	size >>= 2;
-	nvhost_module_busy(dev->dev);
-	while (size--) {
-		*(out++) = readl(p);
-		p += 4;
-	}
-	rmb();
-	nvhost_module_idle(dev->dev);
-}
-
-void nvhost_write_module_regs(struct nvhost_cpuaccess *ctx, u32 module,
-			u32 offset, size_t size, const void *values)
-{
-	struct nvhost_master *dev = cpuaccess_to_dev(ctx);
-	void __iomem *p = ctx->regs[module] + offset;
-	const u32 *in = (const u32 *)values;
-	BUG_ON(size & 3);
-	size >>= 2;
-	nvhost_module_busy(dev->dev);
-	while (size--) {
-		writel(*(in++), p);
-		p += 4;
-	}
-	wmb();
-	nvhost_module_idle(dev->dev);
-}
diff --git a/drivers/video/tegra/host/nvhost_cpuaccess.h b/drivers/video/tegra/host/nvhost_cpuaccess.h
deleted file mode 100644
index 2e210b7477af..000000000000
--- a/drivers/video/tegra/host/nvhost_cpuaccess.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * drivers/video/tegra/host/nvhost_cpuaccess.h
- *
- * Tegra Graphics Host Cpu Register Access
- *
- * Copyright (c) 2010, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#ifndef __NVHOST_CPUACCESS_H
-#define __NVHOST_CPUACCESS_H
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-enum nvhost_module_id {
-	NVHOST_MODULE_DISPLAY_A = 0,
-	NVHOST_MODULE_DISPLAY_B,
-	NVHOST_MODULE_VI,
-	NVHOST_MODULE_ISP,
-	NVHOST_MODULE_MPE,
-#if 0
-	/* TODO: [ahatala 2010-07-02] find out if these are needed */
-	NVHOST_MODULE_FUSE,
-	NVHOST_MODULE_APB_MISC,
-	NVHOST_MODULE_CLK_RESET,
-#endif
-	NVHOST_MODULE_NUM
-};
-
-struct nvhost_cpuaccess {
-	struct resource **reg_mem;
-	void __iomem **regs;
-	atomic_t *lock_counts;
-};
-
-#define cpuaccess_to_dev(ctx) container_of(ctx, struct nvhost_master, cpuaccess)
-#define cpuaccess_op(ctx) (cpuaccess_to_dev(ctx)->op.cpuaccess)
-int nvhost_cpuaccess_init(struct nvhost_cpuaccess *ctx,
-			struct platform_device *pdev);
-
-int nvhost_mutex_try_lock(struct nvhost_cpuaccess *ctx, unsigned int idx);
-
-void nvhost_mutex_unlock(struct nvhost_cpuaccess *ctx, unsigned int idx);
-
-void nvhost_read_module_regs(struct nvhost_cpuaccess *ctx, u32 module,
-			u32 offset, size_t size, void *values);
-
-void nvhost_write_module_regs(struct nvhost_cpuaccess *ctx, u32 module,
-			u32 offset, size_t size, const void *values);
-
-#endif
diff --git a/drivers/video/tegra/host/nvhost_syncpt.c b/drivers/video/tegra/host/nvhost_syncpt.c
index f212e618f950..04c6e917a84c 100644
--- a/drivers/video/tegra/host/nvhost_syncpt.c
+++ b/drivers/video/tegra/host/nvhost_syncpt.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Syncpoints
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
  */
 
 #include <linux/nvhost_ioctl.h>
+#include <linux/platform_device.h>
 #include "nvhost_syncpt.h"
 #include "dev.h"
 
@@ -235,6 +236,28 @@ void nvhost_syncpt_debug(struct nvhost_syncpt *sp)
 	syncpt_op(sp).debug(sp);
 }
 
+int nvhost_mutex_try_lock(struct nvhost_syncpt *sp, int idx)
+{
+	struct nvhost_master *host = syncpt_to_dev(sp);
+	u32 reg;
+
+	nvhost_module_busy(host->dev);
+	reg = syncpt_op(sp).mutex_try_lock(sp, idx);
+	if (reg) {
+		nvhost_module_idle(host->dev);
+		return -EBUSY;
+	}
+	atomic_inc(&sp->lock_counts[idx]);
+	return 0;
+}
+
+void nvhost_mutex_unlock(struct nvhost_syncpt *sp, int idx)
+{
+	syncpt_op(sp).mutex_unlock(sp, idx);
+	nvhost_module_idle(syncpt_to_dev(sp)->dev);
+	atomic_dec(&sp->lock_counts[idx]);
+}
+
 /* check for old WAITs to be removed (avoiding a wrap) */
 int nvhost_syncpt_wait_check(struct nvhost_syncpt *sp,
 			     struct nvmap_client *nvmap,
diff --git a/drivers/video/tegra/host/nvhost_syncpt.h b/drivers/video/tegra/host/nvhost_syncpt.h
index 0dfb11775980..1f22a6d2742e 100644
--- a/drivers/video/tegra/host/nvhost_syncpt.h
+++ b/drivers/video/tegra/host/nvhost_syncpt.h
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Host Syncpoints
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -43,6 +43,8 @@ struct nvhost_syncpt {
 	u32 nb_pts;
 	u32 nb_bases;
 	u32 client_managed;
+	atomic_t *lock_counts;
+	u32 nb_mlocks;
 };
 
 int nvhost_syncpt_init(struct nvhost_syncpt *);
@@ -159,4 +161,8 @@ int nvhost_syncpt_wait_check(struct nvhost_syncpt *sp,
 
 void nvhost_syncpt_debug(struct nvhost_syncpt *sp);
 
+int nvhost_mutex_try_lock(struct nvhost_syncpt *sp, int idx);
+
+void nvhost_mutex_unlock(struct nvhost_syncpt *sp, int idx);
+
 #endif
diff --git a/drivers/video/tegra/host/t20/t20.c b/drivers/video/tegra/host/t20/t20.c
index 6983f1cc3fbd..a08728c4a0df 100644
--- a/drivers/video/tegra/host/t20/t20.c
+++ b/drivers/video/tegra/host/t20/t20.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Init for T20 Architecture Chips
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -56,6 +56,7 @@ struct nvhost_device devices[] = {
 	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_NONE,
 },
 {
 	/* channel 1 */
@@ -69,6 +70,7 @@ struct nvhost_device devices[] = {
 	.clocks = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
 	.powergate_ids = {TEGRA_POWERGATE_3D, -1},
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_NONE,
 },
 {
 	/* channel 2 */
@@ -83,6 +85,7 @@ struct nvhost_device devices[] = {
 			{"emc", UINT_MAX} },
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	.clockgate_delay = 0,
+	.moduleid      = NVHOST_MODULE_NONE,
 },
 {
 	/* channel 3 */
@@ -91,6 +94,7 @@ struct nvhost_device devices[] = {
 	.syncpts = 0,
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_ISP,
 },
 {
 	/* channel 4 */
@@ -104,6 +108,7 @@ struct nvhost_device devices[] = {
 	.exclusive     = true,
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_VI,
 },
 {
 	/* channel 5 */
@@ -119,6 +124,7 @@ struct nvhost_device devices[] = {
 	.clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
 	.powergate_ids = {TEGRA_POWERGATE_MPE, -1},
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_MPE,
 },
 {
 	/* channel 6 */
@@ -128,6 +134,7 @@ struct nvhost_device devices[] = {
 	.modulemutexes = BIT(NVMODMUTEX_DSI),
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_NONE,
 } };
 
 static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
@@ -164,7 +171,6 @@ static int t20_channel_init(struct nvhost_channel *ch,
 
 int nvhost_init_t20_channel_support(struct nvhost_master *host)
 {
-	host->nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
 	host->nb_channels =  NVHOST_NUMCHANNELS;
 
 	host->op.channel.init = t20_channel_init;
@@ -194,8 +200,5 @@ int nvhost_init_t20_support(struct nvhost_master *host)
 	err = nvhost_init_t20_intr_support(host);
 	if (err)
 		return err;
-	err = nvhost_init_t20_cpuaccess_support(host);
-	if (err)
-		return err;
 	return 0;
 }
diff --git a/drivers/video/tegra/host/t20/t20.h b/drivers/video/tegra/host/t20/t20.h
index 20bb13691321..4a8a8e6324fd 100644
--- a/drivers/video/tegra/host/t20/t20.h
+++ b/drivers/video/tegra/host/t20/t20.h
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Chip support for T20
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,7 +29,6 @@ int nvhost_init_t20_channel_support(struct nvhost_master *);
 int nvhost_init_t20_debug_support(struct nvhost_master *);
 int nvhost_init_t20_syncpt_support(struct nvhost_master *);
 int nvhost_init_t20_intr_support(struct nvhost_master *);
-int nvhost_init_t20_cpuaccess_support(struct nvhost_master *);
 int nvhost_init_t20_support(struct nvhost_master *host);
 int nvhost_t20_save_context(struct nvhost_module *mod, u32 syncpt_id);
 
diff --git a/drivers/video/tegra/host/t30/t30.c b/drivers/video/tegra/host/t30/t30.c
index 7e1a09394c03..a6fb142793b4 100644
--- a/drivers/video/tegra/host/t30/t30.c
+++ b/drivers/video/tegra/host/t30/t30.c
@@ -3,7 +3,7 @@
  *
  * Tegra Graphics Init for T30 Architecture Chips
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@
 
 #include <linux/mutex.h>
 #include <mach/powergate.h>
+#include <mach/iomap.h>
 #include "dev.h"
 #include "t20/t20.h"
 #include "t30.h"
@@ -60,6 +61,7 @@ static struct nvhost_device devices[] = {
 	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_NONE,
 },
 {
 	/* channel 1 */
@@ -83,6 +85,7 @@ static struct nvhost_device devices[] = {
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
 	.can_powergate = true,
 	.powergate_delay = 100,
+	.moduleid      = NVHOST_MODULE_NONE,
 },
 {
 	/* channel 2 */
@@ -97,6 +100,7 @@ static struct nvhost_device devices[] = {
 			{"emc", 300000000} },
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	.clockgate_delay = 0,
+	.moduleid      = NVHOST_MODULE_NONE,
 },
 {
 	/* channel 3 */
@@ -105,6 +109,7 @@ static struct nvhost_device devices[] = {
 	.syncpts       = 0,
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_ISP,
 },
 {
 	/* channel 4 */
@@ -118,6 +123,7 @@ static struct nvhost_device devices[] = {
 	.exclusive     = true,
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_VI,
 },
 {
 	/* channel 5 */
@@ -135,6 +141,7 @@ static struct nvhost_device devices[] = {
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
 	.can_powergate  = true,
 	.powergate_delay = 100,
+	.moduleid      = NVHOST_MODULE_MPE,
 },
 {
 	/* channel 6 */
@@ -144,6 +151,7 @@ static struct nvhost_device devices[] = {
 	.modulemutexes = BIT(NVMODMUTEX_DSI),
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
+	.moduleid      = NVHOST_MODULE_NONE,
 } };
 
 #define NVHOST_CHANNEL_BASE 0
@@ -217,8 +225,5 @@ int nvhost_init_t30_support(struct nvhost_master *host)
 	err = nvhost_init_t20_intr_support(host);
 	if (err)
 		return err;
-	err = nvhost_init_t20_cpuaccess_support(host);
-	if (err)
-		return err;
 	return 0;
 }