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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2016-06-29 14:29:20 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2016-06-29 16:49:20 +0200
commit715cac9a8034c84b4c245f96c2ab484e1a3eca99 (patch)
treefaf4777572e2dc222287ffd9362822c951842341 /drivers/video/tegra
parent5d491c1d43f00ddf9c9414c283a96b71fff23c22 (diff)
video: tegra: correct lvds clk sequence
Patch taken from Manoj Gupta's post on NVIDIA's public embedded systems forum: https://devtalk.nvidia.com/default/topic/822612/jetson-tk1/-issue-lvds-panel-enabled-effect-hdmi-out-image-pull-down-menu-items/post/4673174/#4673174 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Diffstat (limited to 'drivers/video/tegra')
-rw-r--r--drivers/video/tegra/dc/sor.c39
1 files changed, 28 insertions, 11 deletions
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index e5fe66be55d0..43f7cb0cc8a4 100644
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -1184,6 +1184,33 @@ void tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
tegra_dc_put(dc);
}
+static void tegra_sor_config_lvds_clk(struct tegra_dc_sor_data *sor)
+{
+ int flag = tegra_is_clk_enabled(sor->sor_clk);
+
+ if (sor->clk_type == TEGRA_SOR_LINK_CLK)
+ return;
+
+ tegra_sor_writel(sor, NV_SOR_CLK_CNTRL,
+ NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK |
+ NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS);
+
+ tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
+
+ /*
+ * HW bug 1425607
+ * Disable clocks to avoid glitch when switching
+ * between safe clock and macro pll clock
+ */
+ if (flag) clk_disable_unprepare(sor->sor_clk);
+
+ tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 1);
+
+ if (flag) clk_prepare_enable(sor->sor_clk);
+
+ sor->clk_type = TEGRA_SOR_LINK_CLK;
+}
+
void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
bool balanced, bool conforming)
{
@@ -1253,20 +1280,10 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK);
tegra_dc_sor_enable_lane_sequencer(sor, true, true);
- tegra_dc_sor_set_link_bandwidth(sor, SOR_LINK_SPEED_LVDS);
+ tegra_sor_config_lvds_clk(sor);
tegra_dc_sor_attach_lvds(sor);
- tegra_sor_writel(sor, NV_SOR_CLK_CNTRL,
- NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK |
- NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS);
-
-
-
-
- /* re-enable SOR clock */
- tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 1);
-
if ((tegra_dc_sor_set_power_state(sor, 1))) {
dev_err(&sor->dc->ndev->dev,
"Failed to power up SOR sequencer for LVDS\n");