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authorAnson Huang <b20788@freescale.com>2015-06-03 22:54:38 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-09-17 09:23:42 -0500
commit7ca28f8bde7d5bc0616ec7816622114e2621e59e (patch)
treed004674836aeda3b642ba014926b2150bc9a48df /drivers/video
parentbf2ba739b11adab2b8f0c3b10146520a7af7fb6d (diff)
MLK-10945 ARM: imx: correct busfreq flow for i.mx6qp/dq/dl
When busfreq transit to low bus mode and back to normal mode, the delay line settings should be restored, but the software flow is entering the med setpoint path which is NOT supported now, it will lead to incorrect delay line settings for normal mode when busfreq is ever switching to other mode and back to normal mode; Store MMDC1 ODT setting as well and improve those MMDC settings to align with ddr script in uboot, recommended by design team. During DLL On/Off switch, pre-charge command should be only issued to those open banks, otherwise, some boards busfreq stress test will be failed. Signed-off-by: Anson Huang <b20788@freescale.com> Conflicts: arch/arm/mach-imx/busfreq_ddr3.c
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