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authorJason Chen <b02280@freescale.com>2009-12-17 18:58:56 +0800
committerJason Chen <b02280@freescale.com>2009-12-17 20:51:17 +0800
commita0f08ff09d20a69e68eefcd14edb6354dfc46d98 (patch)
tree58e9e8ae96026106be0962d0c2aafeb17ff883a8 /drivers/video
parent520f070590696c4790f2d7feee6ae70fd132acf6 (diff)
ENGR00119274 TVE: HDTV can not work
1.arrange display port according to choice of different display device 2.for ipu_disp.c: not round pixel clock to even for tvout. 3.cmdline "hdtv" enable 720P, "hdtv=2" enable 720P as primary. Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/mxc/mxc_ipuv3_fb.c2
-rw-r--r--drivers/video/mxc/tve.c20
2 files changed, 14 insertions, 8 deletions
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
index f9b8f6b0f84c..39c9fdd207af 100644
--- a/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -168,6 +168,8 @@ static int _setup_disp_channel1(struct fb_info *fbi)
if (mxc_fbi_tmp->ipu_ch == MEM_BG_SYNC) {
fbi->var.vmode =
registered_fb[i]->var.vmode;
+ mxc_fbi->ipu_di_pix_fmt =
+ mxc_fbi_tmp->ipu_di_pix_fmt;
break;
}
}
diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c
index 061d65a7cd20..74c98521bfc1 100644
--- a/drivers/video/mxc/tve.c
+++ b/drivers/video/mxc/tve.c
@@ -221,8 +221,8 @@ static int tve_setup(int mode)
{
u32 reg;
struct clk *pll3_clk;
- unsigned long pll3_clock_rate = 216000000;
- struct clk *ipu_di0_clk;
+ unsigned long pll3_clock_rate = 216000000, di1_clock_rate = 27000000;
+ struct clk *ipu_di1_clk;
if (tve.cur_mode == mode)
return 0;
@@ -233,25 +233,23 @@ static int tve_setup(int mode)
case TVOUT_FMT_PAL:
case TVOUT_FMT_NTSC:
pll3_clock_rate = 216000000;
+ di1_clock_rate = 27000000;
break;
case TVOUT_FMT_720P60:
pll3_clock_rate = 297000000;
+ di1_clock_rate = 74250000;
break;
}
if (enabled)
clk_disable(tve.clk);
pll3_clk = clk_get(NULL, "pll3");
- ipu_di0_clk = clk_get(NULL, "ipu_di0_clk");
- if ((clk_get_parent(ipu_di0_clk) == pll3_clk) &&
- (clk_get_rate(pll3_clk) != pll3_clock_rate)) {
- printk(KERN_INFO "Cannot setup TV since display is using PLL3\n");
- return -EINVAL;
- }
+ ipu_di1_clk = clk_get(NULL, "ipu_di1_clk");
clk_disable(pll3_clk);
clk_set_rate(pll3_clk, pll3_clock_rate);
clk_enable(pll3_clk);
+ clk_set_rate(ipu_di1_clk, di1_clock_rate);
clk_enable(tve.clk);
@@ -616,6 +614,7 @@ static int _tve_get_revision(void)
return rev;
}
+extern int g_di1_tvout;
static int tve_probe(struct platform_device *pdev)
{
int ret, i;
@@ -623,6 +622,11 @@ static int tve_probe(struct platform_device *pdev)
struct tve_platform_data *plat_data = pdev->dev.platform_data;
u32 conf_reg;
+ if (!g_di1_tvout) {
+ pr_debug("TVE: DI1 was occupied by other device,TVE will not enable\n");
+ return -EBUSY;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
return -ENOMEM;