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authorTroy Kisky <troy.kisky@boundarydevices.com>2015-06-09 12:15:35 -0700
committerMax Krummenacher <max.krummenacher@toradex.com>2015-12-26 14:50:33 +0100
commitdf7b30b5b521fad21e682f318ee703be2144358b (patch)
tree6eaf13dfa1176c145fab05849d0c0a40d12102bd /drivers
parentab9e816efb07dcaec23d3c55d3db1773b745ae47 (diff)
pci-imx6: fix reboot bug
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/host/pci-imx6.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index d5d9f7991a84..3ff14371838a 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -59,6 +59,7 @@ struct imx6_pcie {
struct regmap *iomuxc_gpr;
struct regmap *reg_src;
struct regulator *pcie_phy_regulator;
+ int force_detect_state;
};
/* PCIe Root Complex registers (memory-mapped) */
@@ -261,7 +262,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
- u32 val, gpr1, gpr12;
+ u32 gpr1, gpr12;
if (is_imx7d_pcie(imx6_pcie)) {
/* G_RST */
@@ -299,11 +300,7 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
- val = readl(pp->dbi_base + PCIE_PL_PFLR);
- val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
- val |= PCIE_PL_PFLR_FORCE_LINK;
- writel(val, pp->dbi_base + PCIE_PL_PFLR);
-
+ imx6_pcie->force_detect_state = 1;
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0);
}
@@ -431,6 +428,15 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
udelay(200);
}
+ if (imx6_pcie->force_detect_state) {
+ u32 val;
+
+ imx6_pcie->force_detect_state = 0;
+ val = readl(pp->dbi_base + PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+ writel(val, pp->dbi_base + PCIE_PL_PFLR);
+ }
/*
* Release the PCIe PHY reset here
*/