diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-05-23 17:58:46 -0700 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-06-24 14:46:22 +0200 |
| commit | 053c208cac8778fee589ef4f6b3a4ebe0d7a44d2 (patch) | |
| tree | 660b5bb01252309ef5f2786acc7c13c76d0c76af /drivers | |
| parent | ae992c91dce799267c38935fa2eab635641c3c7c (diff) | |
pinctrl: pinctrl-imx: add support for LPSR GPR padctrl
The LPSR IOMUXC also has a general purpose (GPR) part which is able
to define pad settings for GPIO8-15. Implement it as yet another
pinctrl driver.
Note: 4 GPIO's share one register, the values are currently over-
written, hence the current code only allows one GPIO per register
to be configured...
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pinctrl/freescale/pinctrl-imx7d.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index fb5082711909..b5e3f116184d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -185,6 +185,17 @@ enum imx7d_lpsr_pads { MX7D_PAD_GPIO1_IO07 = 7, }; +enum imx7d_lpsr_gpr_pads { + MX7D_PAD_GPIO1_IO08_GPR = 0, + MX7D_PAD_GPIO1_IO09_GPR = 1, + MX7D_PAD_GPIO1_IO10_GPR = 2, + MX7D_PAD_GPIO1_IO11_GPR = 3, + MX7D_PAD_GPIO1_IO12_GPR = 4, + MX7D_PAD_GPIO1_IO13_GPR = 5, + MX7D_PAD_GPIO1_IO14_GPR = 6, + MX7D_PAD_GPIO1_IO15_GPR = 7, +}; + /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0), @@ -356,6 +367,17 @@ static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07), }; +static const struct pinctrl_pin_desc imx7d_lpsr_gpr_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14_GPR), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15_GPR), +}; + static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { .pins = imx7d_pinctrl_pads, .npins = ARRAY_SIZE(imx7d_pinctrl_pads), @@ -367,9 +389,16 @@ static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = { .flags = ZERO_OFFSET_VALID, }; +static struct imx_pinctrl_soc_info imx7d_lpsr_gpr_pinctrl_info = { + .pins = imx7d_lpsr_gpr_pinctrl_pads, + .npins = ARRAY_SIZE(imx7d_lpsr_gpr_pinctrl_pads), + .flags = ZERO_OFFSET_VALID, +}; + static struct of_device_id imx7d_pinctrl_of_match[] = { { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, }, { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info }, + { .compatible = "fsl,imx7d-lpsr-gpr", .data = &imx7d_lpsr_gpr_pinctrl_info }, { /* sentinel */ } }; |