diff options
| author | Archit Taneja <architt@codeaurora.org> | 2015-03-04 15:19:35 +0530 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2015-05-17 19:12:19 -0400 |
| commit | 5ec6388f8e752c6f63caf859ad2be687668c3389 (patch) | |
| tree | b60c9e4adb193d7a37e843a160445fa26a6f1fa2 /drivers | |
| parent | d415fc1d430b6f0a5c1011bf9830fcdb756a8718 (diff) | |
clk: qcom: fix RCG M/N counter configuration
[ Upstream commit 0b21503dbbfa669dbd847b33578d4041513cddb2 ]
Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.
In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.
Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/qcom/clk-rcg2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index cfa9eb4fe9ca..f76b6853b61c 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -240,7 +240,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; cfg = f->pre_div << CFG_SRC_DIV_SHIFT; cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT; - if (rcg->mnd_width && f->n) + if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask, cfg); |