diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2011-09-01 10:36:42 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-09-01 21:11:34 -0700 |
| commit | 6d310aef62c5b1d11b44379d28766f20b1f3335d (patch) | |
| tree | b13aea40d15fbf86987ff6ca1ecb38e04cac8f91 /drivers | |
| parent | e0631d5c41fbfd2de09f10b344a800aed723285c (diff) | |
Serial: tegra: Allow 2% error in selecting clock source for baudrate.
Allowing 2% error in calculated baudrate when finding the best clock
source uart controller.
bug 870388
Change-Id: Id765efd7bf087e10bc93a8ba5bd1eec8a8f3ef48
Reviewed-on: http://git-master/r/50255
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/serial/tegra_hsuart.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c index 3709162e67dd..078e2965fafc 100644 --- a/drivers/serial/tegra_hsuart.c +++ b/drivers/serial/tegra_hsuart.c @@ -1076,14 +1076,20 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t, unsigned long fin_rate = rate; int final_index = -1; int count; + unsigned long error_2perc; pdata = u->dev->platform_data; if (!pdata || !pdata->parent_clk_count) return fin_rate; + error_2perc = (rate / 50); + for (count = 0; count < pdata->parent_clk_count; ++count) { parent_rate = pdata->parent_clk_list[count].fixed_clk_rate; + if (parent_rate < rate) + continue; + #ifndef CONFIG_ARCH_TEGRA_2x_SOC divider = clk_div71_get_divider(parent_rate, rate); @@ -1097,8 +1103,12 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t, final_index = count; fin_err = err_rate; fin_rate = new_rate; + if (fin_err < error_2perc) + break; } } + if (fin_err < error_2perc) + break; } #endif /* Get the divisor by uart controller dll/dlm */ @@ -1113,8 +1123,12 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t, final_index = count; fin_err = err_rate; fin_rate = parent_rate; + if (fin_err < error_2perc) + break; } } + if (fin_err < error_2perc) + break; } } |