diff options
| author | Yudong Tan <ytan@nvidia.com> | 2011-06-27 14:05:58 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-11 17:06:49 -0700 |
| commit | 72f29850f1f356e58bb3282b0b069443bbfc6bc9 (patch) | |
| tree | 4044000bcba7aaa3f9a9f39eaa71f74d60bddd44 /drivers | |
| parent | 246302bc5e5ae7292e733fd3b1053f8639ca8211 (diff) | |
video: tegra: Use new Tegra platform types
This change is needed to support three platforms, silicon,
fpga and simulation.
Change-Id: I70c6edbab85712b037b1ddf15ce72cf1a2affeba
Reviewed-on: http://git-master/r/36354
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 20 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/dsi.c | 2 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/rgb.c | 6 |
3 files changed, 14 insertions, 14 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 788c7d3e07d2..4aa8ad1b8b8b 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -1037,10 +1037,10 @@ EXPORT_SYMBOL(tegra_dc_sync_windows); static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc) { -#ifdef CONFIG_TEGRA_FPGA_PLATFORM - return 27000000; -#else +#ifdef CONFIG_TEGRA_SILICON_PLATFORM return clk_get_rate(dc->clk); +#else + return 27000000; #endif } @@ -1233,11 +1233,11 @@ static inline void print_mode(struct tegra_dc *dc, static inline void enable_dc_irq(unsigned int irq) { -#ifdef CONFIG_TEGRA_FPGA_PLATFORM +#ifdef CONFIG_TEGRA_SILICON_PLATFORM + enable_irq(irq); +#else /* Always disable DC interrupts on FPGA. */ disable_irq(irq); -#else - enable_irq(irq); #endif } @@ -1580,7 +1580,7 @@ static void tegra_dc_vblank(struct work_struct *work) static irqreturn_t tegra_dc_irq(int irq, void *ptr) { -#ifndef CONFIG_TEGRA_FPGA_PLATFORM +#ifdef CONFIG_TEGRA_SILICON_PLATFORM struct tegra_dc *dc = ptr; unsigned long status; unsigned long val; @@ -1686,9 +1686,9 @@ static irqreturn_t tegra_dc_irq(int irq, void *ptr) } return IRQ_HANDLED; -#else /* CONFIG_TEGRA_FPGA_PLATFORM */ +#else /* CONFIG_TEGRA_SILICON_PLATFORM */ return IRQ_NONE; -#endif /* !CONFIG_TEGRA_FPGA_PLATFORM */ +#endif /* !CONFIG_TEGRA_SILICON_PLATFORM */ } static void tegra_dc_set_color_control(struct tegra_dc *dc) @@ -1880,7 +1880,7 @@ static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc) msleep(5); tegra_periph_reset_assert(dc->clk); msleep(2); -#ifndef CONFIG_TEGRA_FPGA_PLATFORM +#ifdef CONFIG_TEGRA_SILICON_PLATFORM tegra_periph_reset_deassert(dc->clk); msleep(1); #endif diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index a807fdfc682b..fbfb02c16d66 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -895,7 +895,7 @@ static void tegra_dsi_set_dc_clk(struct tegra_dc *dc, /* Get the corresponding register value of shift_clk_div. */ shift_clk_div_register = dsi->shift_clk_div * 2 - 2; -#ifdef CONFIG_TEGRA_FPGA_PLATFORM +#ifndef CONFIG_TEGRA_SILICON_PLATFORM shift_clk_div_register = 1; #endif diff --git a/drivers/video/tegra/dc/rgb.c b/drivers/video/tegra/dc/rgb.c index e7ea9a8914df..7b87a2da4b4d 100644 --- a/drivers/video/tegra/dc/rgb.c +++ b/drivers/video/tegra/dc/rgb.c @@ -42,13 +42,13 @@ static const u32 tegra_dc_rgb_enable_out_sel_pintable[] = { DC_COM_PIN_OUTPUT_SELECT0, 0x00000000, DC_COM_PIN_OUTPUT_SELECT1, 0x00000000, DC_COM_PIN_OUTPUT_SELECT2, 0x00000000, -#ifdef CONFIG_TEGRA_FPGA_PLATFORM +#ifdef CONFIG_TEGRA_SILICON_PLATFORM + DC_COM_PIN_OUTPUT_SELECT3, 0x00000000, +#else /* The display panel sub-board used on FPGA platforms (panel 86) is non-standard. It expects the Data Enable signal on the WR pin instead of the DE pin. */ DC_COM_PIN_OUTPUT_SELECT3, 0x00200000, -#else - DC_COM_PIN_OUTPUT_SELECT3, 0x00000000, #endif DC_COM_PIN_OUTPUT_SELECT4, 0x00210222, DC_COM_PIN_OUTPUT_SELECT5, 0x00002200, |