diff options
| author | Francesco Dolcini <francesco.dolcini@toradex.com> | 2022-09-21 12:34:13 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2022-09-22 20:13:31 +0000 |
| commit | b804bcdad822b47127b56f33c72f2e19bf12c7c3 (patch) | |
| tree | 013ef3c6ca5b8731ea7149af13c33722ed4d2ef4 /drivers | |
| parent | cc9f4e5667e1cb60538de6b62c7096e1b0b5e88d (diff) | |
drm/bridge: lt8912b: clarify lvds output status
Add comments on the lt8912_write_lvds_config() config to document the
current settings and to make it clear that this is a hardcoded
configuration not relevant for the HDMI output (could be removed without
affecting the HDMI port).
No changes on the actual register writes.
Upstream-Status: Submitted [https://lore.kernel.org/all/20220922124306.34729-5-dev@pschenker.ch/]
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/bridge/lontium-lt8912b.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c b/drivers/gpu/drm/bridge/lontium-lt8912b.c index 82169b6bfca1..b109ad89f638 100644 --- a/drivers/gpu/drm/bridge/lontium-lt8912b.c +++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c @@ -163,24 +163,32 @@ static int lt8912_write_rxlogicres_config(struct lt8912 *lt) return ret; }; +/* enable LVDS output with some hardcoded configuration, not required for the HDMI output */ static int lt8912_write_lvds_config(struct lt8912 *lt) { const struct reg_sequence seq[] = { + // lvds power up {0x44, 0x30}, {0x51, 0x05}, - {0x50, 0x24}, - {0x51, 0x2d}, - {0x52, 0x04}, - {0x69, 0x0e}, + + // core pll bypass + {0x50, 0x24}, // cp=50uA + {0x51, 0x2d}, // Pix_clk as reference, second order passive LPF PLL + {0x52, 0x04}, // loopdiv=0, use second-order PLL + {0x69, 0x0e}, // CP_PRESET_DIV_RATIO {0x69, 0x8e}, {0x6a, 0x00}, - {0x6c, 0xb8}, + {0x6c, 0xb8}, // RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] {0x6b, 0x51}, - {0x04, 0xfb}, + + {0x04, 0xfb}, // core pll reset {0x04, 0xff}, - {0x7f, 0x00}, - {0xa8, 0x13}, - {0x02, 0xf7}, + + // scaler bypass + {0x7f, 0x00}, // disable scaler + {0xa8, 0x13}, // 0x13: JEIDA, 0x33: VESA + + {0x02, 0xf7}, // lvds pll reset {0x02, 0xff}, {0x03, 0xcf}, {0x03, 0xff}, |