diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2017-06-20 14:14:03 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2017-06-20 14:16:46 +0800 |
| commit | 89869792e2f59c81354f9a53280c4eb6e95f4a9a (patch) | |
| tree | 9c8dc431ab6191800a538bb84ec5b6864bb561d1 /drivers | |
| parent | 037051e60f3b29fb09aae6f2c97a3532482dfc2a (diff) | |
MLK-15120 ARM: imx7d: clk: select uart3 clock parent and set rate
The clock driver may enable uart clock tree when earlycon/earlyprintk
kernel param is enabled, and the clock gate specify CLK_SET_RATE_GATE,
then .of_clk_set_defaults() set the dts node assigned-rate will be failed.
So set parent and set rate in clock driver is reasonable.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 90b90b8e97f5..ccc211989522 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -941,6 +941,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) /* set parent of SIM1 root clock */ imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]); + imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); + imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000); imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000); imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); |