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authorRakesh Bodla <rbodla@nvidia.com>2012-02-07 18:26:46 +0530
committerSimone Willett <swillett@nvidia.com>2012-03-26 17:47:39 -0700
commitaa6554e19d34990e864e5f10f25a217f4ace73bf (patch)
treee6f5e8358541c0c57a47dc355cac68b7b6879251 /drivers
parent9e50d0fba280c9db720bfd98e9c3455e025d8eef (diff)
usb: ehci: tegra: Fence read for AHB memory coherency
Fix memory coherency of AHB Master-initiated writes to DRAM by reading the fence registers to make sure memory is flushed to DRAM from the MC/EMC. Bug 729267 Bug 952405 Change-Id: Ia60ee6796e53de6ece89e7e2ad531009a2fe5f00 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-on: http://git-master/r/88284 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/host/ehci-tegra.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 168015da8cb1..8dd873bbe59b 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -52,6 +52,10 @@
#define HOSTPC1_DEVLC_STS (1 << 28)
#define HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
+#define USB1_PREFETCH_ID 6
+#define USB2_PREFETCH_ID 18
+#define USB3_PREFETCH_ID 17
+
struct tegra_ehci_hcd {
struct ehci_hcd *ehci;
struct tegra_usb_phy *phy;
@@ -167,6 +171,14 @@ static irqreturn_t tegra_ehci_irq (struct usb_hcd *hcd)
irqreturn_t irq_status;
bool pmc_remote_wakeup = false;
+ /* Fence read for coherency of AHB master intiated writes */
+ if (tegra->phy->instance == 0)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB1_PREFETCH_ID));
+ else if (tegra->phy->instance == 1)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB2_PREFETCH_ID));
+ else if (tegra->phy->instance == 2)
+ readb(IO_ADDRESS(IO_PPCS_PHYS + USB3_PREFETCH_ID));
+
if ((tegra->phy->usb_phy_type == TEGRA_USB_PHY_TYPE_UTMIP) &&
(tegra->ehci->has_hostpc)) {
/* check if there is any remote wake event */