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authorLaxman Dewangan <ldewangan@nvidia.com>2010-06-28 22:32:04 +0530
committerGary King <gking@nvidia.com>2010-07-09 09:48:49 -0700
commitdcea9bbb855b9fcb34371ff4d021d5095adb5d4a (patch)
treedc58545d7d6ee148b4484e68b6aa49f9401544bf /drivers
parent2a63e51b5ede608a2f6cc20f31c55e660b5b2ce9 (diff)
[arm/tegra] serial: Enabling hw based rts control.
Tegra arch2x have the capability to control the rts line based on data available in the rx fifo. If data vaiable in rx fifo is equal to the rx trigger level then rts become inactive by the controller. Once the data read from fifo either by cpu or by the dma, the rts become active by hw. Change-Id: I67a52ea105973e9ca21a4cc08f0fb1e3234a7d55 Reviewed-on: http://git-master/r/3299 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers')
-rwxr-xr-xdrivers/serial/tegra_hsuart.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c
index 6162f306212d..fc4dd8c7d791 100755
--- a/drivers/serial/tegra_hsuart.c
+++ b/drivers/serial/tegra_hsuart.c
@@ -815,9 +815,10 @@ static void set_rts(struct tegra_uart_port *t, bool active)
unsigned char mcr;
mcr = t->mcr_shadow;
if (active)
- mcr |= UART_MCR_RTS;
+ mcr |= UART_MCR_RTS_EN;
else
- mcr &= ~UART_MCR_RTS;
+ mcr &= ~UART_MCR_RTS_EN;
+
if (mcr != t->mcr_shadow) {
uart_writeb(t, mcr, UART_MCR);
t->mcr_shadow = mcr;