diff options
author | Han Xu <b45815@freescale.com> | 2015-06-10 17:14:01 -0500 |
---|---|---|
committer | Han Xu <b45815@freescale.com> | 2015-06-11 15:14:51 -0500 |
commit | 374e8f4b518e8c9a307d3208550dfedd69d266a4 (patch) | |
tree | 8639d03f4bee3e10203e75b030f438a46b498a43 /drivers | |
parent | 2e4f9e33fd8b77bb29f928a206a8d1a270789a59 (diff) |
MLK-11087: mtd:qspi: support DDR Quad mode for Macronix mx25l51245g
Enable DDR quad mode for Macronix qspi chip mx25l51245g by setting Quad
bit in status register and enabling in dts file.
The LUT for SPINOR_OP_READ_1_4_4_D was initially designed for Spansion
qspi chip, so there is one cycle for "mode" after address and before
dummy. While Macronix qspi chip doesn't have this feature, so we just
take off one cycle in dts file to bypass this problem.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit 2ee7cdc2b821605dbb47854238d7fc124800547a)
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 7b8f4d9a37f7..84d2723984e5 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -877,6 +877,14 @@ static int set_ddr_quad_mode(struct spi_nor *nor, u32 jedec_id) return status; } return status; + case CFI_MFR_MACRONIX: + status = macronix_quad_enable(nor); + if (status) { + dev_err(nor->dev, + "Macronix DDR quad-read not enabled\n"); + return status; + } + return status; case CFI_MFR_ST: /* Micron, actually */ /* DTR quad read works with the Extended SPI protocol. */ return 0; @@ -1081,6 +1089,8 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, nor->read_opcode = SPINOR_OP_READ_1_4_4_D; } else if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { nor->read_opcode = SPINOR_OP_READ_1_1_4_D; + } else if (JEDEC_MFR(info->jedec_id) == CFI_MFR_MACRONIX) { + nor->read_opcode = SPINOR_OP_READ_1_4_4_D; } else { dev_err(dev, "DDR Quad Read is not supported.\n"); return -EINVAL; |