diff options
| author | Xin Xie <xxie@nvidia.com> | 2011-07-07 14:05:04 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-26 16:53:00 -0700 |
| commit | 54445ff6b7305bead87a79d60c4781d66f7cef18 (patch) | |
| tree | 946b7512fd0a6b3cc21c849ae28b741bce7bfdd0 /drivers | |
| parent | 74f141a4702ff0edea6c473f182905ebd8ac4acb (diff) | |
video: tegra: dc: fix tiled memory efficiency
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3.
This patch adds one memory controller API to retrive tiled memory efficiency.
BUG 847731
Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1
Reviewed-on: http://git-master/r/40074
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 6 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/dc_priv.h | 12 |
2 files changed, 5 insertions, 13 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index f7b5e2d720a7..132ec05022ed 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -707,16 +707,20 @@ static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc, struct tegra_dc_win *w) { unsigned long ret; + int tiled_windows_bw_multiplier; if (!WIN_IS_ENABLED(w)) return 0; + tiled_windows_bw_multiplier = + tegra_mc_get_tiled_memory_bandwidth_multiplier(); + /* perform calculations with most significant bits of pixel clock * to prevent overflow of long. */ ret = (unsigned long)(dc->pixel_clk >> 16) * (tegra_dc_fmt_bpp(w->fmt) / 8) * (WIN_USE_V_FILTER(w) ? 2 : 1) * w->w / w->out_w * - (WIN_IS_TILED(w) ? TILED_WINDOWS_BW_MULTIPLIER : 1); + (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1); /* * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h index ecec2ee78c4a..ebb97d9f6b22 100644 --- a/drivers/video/tegra/dc/dc_priv.h +++ b/drivers/video/tegra/dc/dc_priv.h @@ -41,18 +41,6 @@ #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2) #endif -/* - * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is - * discarded in tiling mode. - */ -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#define TILED_WINDOWS_BW_MULTIPLIER 1 -#elif defined(CONFIG_ARCH_TEGRA_3x_SOC) -#define TILED_WINDOWS_BW_MULTIPLIER 2 -#else -#warning "need to revisit memory tiling effects on DC" -#endif - struct tegra_dc; struct tegra_dc_blend { |