diff options
| author | Nikita Yushchenko <nyushchenko@dev.rtsoft.ru> | 2014-04-28 19:23:44 +0400 |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2014-06-06 12:38:19 +0200 |
| commit | 9c7d0b459c3d169fd4fbe2f831444c1669cef8c2 (patch) | |
| tree | 793d421263f52242ded2f6f5c227c63f96993af8 /drivers | |
| parent | 361f937995467af9221608315b6db80766ca5ef4 (diff) | |
fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6
commit d183c81929beeba842b74422f754446ef2b8b49c upstream.
Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller
present in these SoCs has bit 17 of USBx_CONTROL register marked as
Reserved - there is no PHY_CLK_VALID bit there.
Testing for this bit in ehci_fsl_setup_phy() behaves differently on two
P1020RDB boards available here - on one board test passes and fsl-usb
init succeeds, but on other board test fails, causing fsl-usb init to
fail.
This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on
controller version 1.6 that (per manual) does not have this bit.
Signed-off-by: Nikita Yushchenko <nyushchenko@dev.rtsoft.ru>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/host/ehci-fsl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index f2407b2e8a99..ce65c4ec6550 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -261,7 +261,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, break; } - if (pdata->have_sysif_regs && pdata->controller_ver && + if (pdata->have_sysif_regs && + pdata->controller_ver > FSL_USB_VER_1_6 && (phy_mode == FSL_USB2_PHY_ULPI)) { /* check PHY_CLK_VALID to get phy clk valid */ if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) & |