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authorLiu Ying <Ying.Liu@freescale.com>2011-10-25 14:16:30 +0800
committerAndy Voltz <andy.voltz@timesys.com>2012-03-09 11:26:44 -0500
commita20cf668dca6c0ac1403ff1826c91804ec8803d1 (patch)
tree05a84cac2f5010dc883cfdd50f79264578cfa856 /drivers
parent31e394fe2acf6eab781a836d0014cd443c9c2bb1 (diff)
ENGR00160566 IPUv3:Improve IDMAC_LOCK_EN setting
1) Clear IDMAC_LOCK_EN when dual display is enabled to workaround black flash issue when playing video on DP-FG. 2) Only set IDMAC_LOCK_EN for IPUv3M. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 7c22da39601cfc6551292cbd2c5c1d9ee3b4fbfa)
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mxc/ipu3/ipu_common.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 1f5ed8bc10a5..baf22dda10ae 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -386,7 +386,8 @@ static int ipu_probe(struct platform_device *pdev)
__raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
/* AXI burst setting for sync refresh channels */
- __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
+ if (g_ipu_hw_rev == 3)
+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
/* Set MCU_T to divide MCU access window into 2 */
__raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
@@ -989,6 +990,11 @@ void ipu_uninit_channel(ipu_channel_t channel)
__raw_writel(ipu_conf, IPU_CONF);
+ /* Restore IDMAC_LOCK_EN when we don't use dual display */
+ if (!(ipu_di_use_count[0] && ipu_di_use_count[1]) &&
+ _ipu_is_dmfc_chan(in_dma) && g_ipu_hw_rev == 3)
+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
+
spin_unlock_irqrestore(&ipu_lock, lock_flags);
ipu_put_clk();
@@ -1800,6 +1806,14 @@ int32_t ipu_enable_channel(ipu_channel_t channel)
ipu_conf |= IPU_CONF_SMFC_EN;
__raw_writel(ipu_conf, IPU_CONF);
+ /* Clear IDMAC_LOCK_EN to workaround black flash for dual display */
+ if (g_ipu_hw_rev == 3 && _ipu_is_dmfc_chan(in_dma)) {
+ if (ipu_di_use_count[1] && ipu_di_use_count[0])
+ __raw_writel(0x0, IDMAC_CH_LOCK_EN_1);
+ else
+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
+ }
+
if (idma_is_valid(in_dma)) {
reg = __raw_readl(IDMAC_CHA_EN(in_dma));
__raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
@@ -2782,7 +2796,8 @@ static int ipu_resume(struct platform_device *pdev)
__raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
/* AXI burst setting for sync refresh channels */
- __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
+ if (g_ipu_hw_rev == 3)
+ __raw_writel(0x003F0000, IDMAC_CH_LOCK_EN_1);
clk_disable(g_ipu_clk);
}
mutex_unlock(&ipu_clk_lock);