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authorAlison Wang <b18965@freescale.com>2012-07-26 15:57:13 +0800
committerJustin Waters <justin.waters@timesys.com>2012-09-12 16:49:44 -0400
commitebb6e03ca97c7dc7c626527fa921fb88d9157ba9 (patch)
tree88721bbd5189064c143689a533f55fde7edeee0b /drivers
parent982bc515fdc519abfcfcb3f3921f90528be3077e (diff)
ENGR00212262-2: esdhc: add esdhc controller support for MVF
Add esdhc controller support for MVF. The wp_pin for esdhc should be disabled. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/host/Kconfig2
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c31
2 files changed, 22 insertions, 11 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 64aac7898334..a33e8f5ed74c 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -134,7 +134,7 @@ config MMC_SDHCI_CNS3XXX
config MMC_SDHCI_ESDHC_IMX
bool "SDHCI platform support for the Freescale eSDHC i.MX controller"
- depends on MMC_SDHCI_PLTFM && (ARCH_MX25 || ARCH_MX35 || ARCH_MX5 || ARCH_MX6)
+ depends on MMC_SDHCI_PLTFM && (ARCH_MX25 || ARCH_MX35 || ARCH_MX5 || ARCH_MX6 || ARCH_MVF)
select MMC_SDHCI_IO_ACCESSORS
help
This selects the Freescale eSDHC controller support on the platform
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index e76ef23e1f2a..41c11f1cab1d 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -6,6 +6,8 @@
* Copyright (c) 2010 Pengutronix e.K.
* Author: Wolfram Sang <w.sang@pengutronix.de>
*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
@@ -144,13 +146,14 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
if ((val & SDHCI_INT_DATA_END) && \
!(val & SDHCI_INT_DMA_END))
val = readl(host->ioaddr + reg);
- } else if (reg == SDHCI_CAPABILITIES_1 && cpu_is_mx6()) {
+ } else if (reg == SDHCI_CAPABILITIES_1 &&
+ (cpu_is_mx6() || cpu_is_mvf())) {
/*
- * on mx6q, no cap_1 available, fake one.
+ * on mx6q and faraday, no cap_1 available, fake one.
*/
val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | \
SDHCI_SUPPORT_SDR50;
- } else if (reg == SDHCI_MAX_CURRENT && cpu_is_mx6()) {
+ } else if (reg == SDHCI_MAX_CURRENT && (cpu_is_mx6() || cpu_is_mvf())) {
/*
* on mx6q, no max current available, fake one.
*/
@@ -192,7 +195,7 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
writel(SDHCI_INT_CARD_INT, \
host->ioaddr + SDHCI_INT_STATUS);
- if (val & SDHCI_INT_CARD_INT && !cpu_is_mx6()) {
+ if (val & SDHCI_INT_CARD_INT && !(cpu_is_mx6())) {
/*
* clear D3CD bit and set D3CD bit to avoid
* losing card interrupt
@@ -611,8 +614,10 @@ static irqreturn_t cd_irq(int irq, void *data)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhost);
struct pltfm_imx_data *imx_data = pltfm_host->priv;
- writel(0, sdhost->ioaddr + SDHCI_MIX_CTRL);
- writel(0, sdhost->ioaddr + SDHCI_TUNE_CTRL_STATUS);
+ if (!cpu_is_mvf()) {
+ writel(0, sdhost->ioaddr + SDHCI_MIX_CTRL);
+ writel(0, sdhost->ioaddr + SDHCI_TUNE_CTRL_STATUS);
+ }
if (cpu_is_mx6()) {
imx_data->scratchpad &= ~SDHCI_MIX_CTRL_DDREN;
@@ -659,10 +664,14 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
+ if (cpu_is_mvf())
+ host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
+
/* write_protect can't be routed to controller, use gpio */
sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro;
- if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51() || cpu_is_mx6()))
+ if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51() ||
+ cpu_is_mx6() || cpu_is_mvf()))
imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
host->ocr_avail_sd = MMC_VDD_29_30 | MMC_VDD_30_31 | \
@@ -684,9 +693,11 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
host->clk_mgr_en = true;
}
- reg = readl(host->ioaddr + SDHCI_MIX_CTRL);
- reg &= ~SDHCI_MIX_CTRL_DDREN;
- writel(reg, host->ioaddr + SDHCI_MIX_CTRL);
+ if (!cpu_is_mvf()) {
+ reg = readl(host->ioaddr + SDHCI_MIX_CTRL);
+ reg &= ~SDHCI_MIX_CTRL_DDREN;
+ writel(reg, host->ioaddr + SDHCI_MIX_CTRL);
+ }
/* disable card interrupt enable bit, and clear status bit
* the default value of this enable bit is 1, but it should
* be 0 regarding to standard host controller spec 2.1.3.