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authorRoger Hsieh <rhsieh@nvidia.com>2011-07-11 14:42:40 +0800
committerNiket Sirsi <nsirsi@nvidia.com>2011-07-26 15:40:19 -0700
commiteb7639ad28dae74d982b29f6caa7c98ec0baa501 (patch)
tree3d68b197a886e54f5cb75f161c85e732daf8a84a /drivers
parent453bc4499adaeaa78dcd3f2870c9315e2abc4d15 (diff)
arm: tegra: correct 3D power gate WAR.
3D power gate should be always disabled to keep the power. Set T20 enabled by default. Bug 843271 Change-Id: Icf464cd107e65636440f8103ac6b104e2939e8b9 Reviewed-on: http://git-master/r/40342 Reviewed-on: http://git-master/r/43175 Reviewed-by: David Schalig <dschalig@nvidia.com> Tested-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers')
-rwxr-xr-x[-rw-r--r--]drivers/video/tegra/host/nvhost_acm.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/video/tegra/host/nvhost_acm.c b/drivers/video/tegra/host/nvhost_acm.c
index bde5a7f9ffc8..4fd1820df0b5 100644..100755
--- a/drivers/video/tegra/host/nvhost_acm.c
+++ b/drivers/video/tegra/host/nvhost_acm.c
@@ -32,7 +32,6 @@
#define ACM_TIMEOUT_MSEC 40
-#define DISABLE_3D_POWERGATING
#define DISABLE_MPE_POWERGATING
void nvhost_module_busy(struct nvhost_module *mod)
@@ -152,7 +151,7 @@ int nvhost_module_init(struct nvhost_module *mod, const char *name,
mod->powered = false;
mod->powergate_id = get_module_powergate_id(name);
-#ifdef DISABLE_3D_POWERGATING
+#if CONFIG_DISABLE_3D_POWERGATING
/*
* It is possible for the 3d block to generate an invalid memory
* request during the power up sequence in some cases. Workaround