diff options
| author | Justin Waters <justin.waters@timesys.com> | 2008-02-26 13:07:02 -0500 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2008-02-26 13:07:02 -0500 |
| commit | b80a32b9cc634adfa8eaef33ec981e7febf2ade2 (patch) | |
| tree | f256bce13ba11f514a388160df84e1410bedbe2b /include/asm-blackfin/mach-bf561/cdefBF561.h | |
| parent | 594133ef22fae0d737bd1b57352cf3f48a192c63 (diff) | |
Update the i.MX31 Kernel to 2.6.232.6.23-mx31ads-2008022618072.6.23-mx31-200802261807
This is the result of a brute-force attempt to update the kernel to 2.6.23.
Now that we have a git tree, our effort will be a little nicer in the future.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf561/cdefBF561.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/cdefBF561.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index b14f872e5703..73d4d65249cd 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -57,12 +57,14 @@ /* Writing to VR_CTL initiates a PLL relock sequence. */ static __inline__ void bfin_write_VR_CTL(unsigned int val) { - unsigned long flags, iwr; + unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SICA_IWR0); + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); __builtin_bfin_ssync(); @@ -70,7 +72,8 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); - bfin_write32(SICA_IWR0, iwr); + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) @@ -78,6 +81,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) #define bfin_read_CHIPID() bfin_read32(CHIPID) +/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ +#define bfin_read_SWRST() bfin_read_SICA_SWRST() +#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) +#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() +#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) + /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) |