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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-11-01 21:51:23 +0900
committerRalf Baechle <ralf@linux-mips.org>2007-11-02 16:13:48 +0000
commit9aa4cc11b22ec447b42c5df03fdab5eb748971e2 (patch)
tree9547849f3716ca354d4d4dea4691dd71c737ba40 /include/asm-mips/mach-cobalt
parentdb0c19e1a6abd9a9bdbf3ffbabc1e8e4995cb462 (diff)
[MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-cobalt')
-rw-r--r--include/asm-mips/mach-cobalt/irq.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
index 179d0e850b59..57c8c9ac5851 100644
--- a/include/asm-mips/mach-cobalt/irq.h
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -35,7 +35,7 @@
* 4 - ethernet
* 5 - 16550 UART
* 6 - cascade i8259
- * 7 - CP0 counter (unused)
+ * 7 - CP0 counter
*/
#define MIPS_CPU_IRQ_BASE 16
@@ -48,7 +48,6 @@
#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
-
#define GT641XX_IRQ_BASE 24
#include <asm/irq_gt641xx.h>