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authorDavid S. Miller <davem@sunset.davemloft.net>2005-09-27 22:50:06 -0700
committerDavid S. Miller <davem@sunset.davemloft.net>2005-09-27 22:50:06 -0700
commitd2212bc7db13268bef0799d9ff4b2e511c284885 (patch)
tree8f1ff9d5b790272de29381f3d707251f0dc43c5d /include/asm-sparc64
parentf16af555cc46a724507da371fbac94b430c93315 (diff)
[SPARC64]: Add missing IDs for newer cpus.
Also, the us3_cpufreq driver can work on Ultra-IV and IV+. They use the SAFARI bus register to control the clock divider just like Ultra-III and III+ do. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64')
-rw-r--r--include/asm-sparc64/head.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-sparc64/head.h b/include/asm-sparc64/head.h
index b63a33cf4971..0abd3a674e8f 100644
--- a/include/asm-sparc64/head.h
+++ b/include/asm-sparc64/head.h
@@ -12,9 +12,12 @@
#define __JALAPENO_ID 0x003e0016
#define CHEETAH_MANUF 0x003e
-#define CHEETAH_IMPL 0x0014
-#define CHEETAH_PLUS_IMPL 0x0015
-#define JALAPENO_IMPL 0x0016
+#define CHEETAH_IMPL 0x0014 /* Ultra-III */
+#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
+#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
+#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
+#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
+#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
rdpr %ver, %tmp1; \