diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-02-15 13:40:16 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-02-15 16:37:42 +0800 |
| commit | 8fa8f318eeac939604e2616fd7a6e1fd10d837a0 (patch) | |
| tree | dc9e6b5594c4f80fc8d69a0faf75db536f5d4caf /include/dt-bindings | |
| parent | 3283efbeadbc11cb38146cb7874becfecf27f981 (diff) | |
MLK-20930-1 arm64: dts: freescale: update resource ID
Update resource ID table to SCFW commit:
004247e14afc ("SCF-341 Fix bug in setting large slice clock divider")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/soc/imx_rsrc.h | 33 |
1 files changed, 16 insertions, 17 deletions
diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h index f4d1ca49759a..7561ded1c5a6 100644 --- a/include/dt-bindings/soc/imx_rsrc.h +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -36,15 +36,15 @@ #define SC_R_DC_0_BLIT1 20 #define SC_R_DC_0_BLIT2 21 #define SC_R_DC_0_BLIT_OUT 22 -#define SC_R_DC_0_CAPTURE0 23 -#define SC_R_DC_0_CAPTURE1 24 +#define SC_R_PERF 23 +#define SC_R_UNUSED5 24 #define SC_R_DC_0_WARP 25 -#define SC_R_DC_0_INTEGRAL0 26 -#define SC_R_DC_0_INTEGRAL1 27 +#define SC_R_UNUSED7 26 +#define SC_R_UNUSED8 27 #define SC_R_DC_0_VIDEO0 28 #define SC_R_DC_0_VIDEO1 29 #define SC_R_DC_0_FRAC0 30 -#define SC_R_DC_0_FRAC1 31 +#define SC_R_UNUSED6 31 #define SC_R_DC_0 32 #define SC_R_GPU_2_PID0 33 #define SC_R_DC_0_PLL_0 34 @@ -53,17 +53,17 @@ #define SC_R_DC_1_BLIT1 37 #define SC_R_DC_1_BLIT2 38 #define SC_R_DC_1_BLIT_OUT 39 -#define SC_R_DC_1_CAPTURE0 40 -#define SC_R_DC_1_CAPTURE1 41 +#define SC_R_UNUSED9 40 +#define SC_R_UNUSED10 41 #define SC_R_DC_1_WARP 42 -#define SC_R_DC_1_INTEGRAL0 43 -#define SC_R_DC_1_INTEGRAL1 44 +#define SC_R_UNUSED11 43 +#define SC_R_UNUSED12 44 #define SC_R_DC_1_VIDEO0 45 #define SC_R_DC_1_VIDEO1 46 #define SC_R_DC_1_FRAC0 47 -#define SC_R_DC_1_FRAC1 48 +#define SC_R_UNUSED13 48 #define SC_R_DC_1 49 -#define SC_R_GPU_3_PID0 50 +#define SC_R_UNUSED14 50 #define SC_R_DC_1_PLL_0 51 #define SC_R_DC_1_PLL_1 52 #define SC_R_SPI_0 53 @@ -303,8 +303,8 @@ #define SC_R_M4_0_UART 287 #define SC_R_M4_0_I2C 288 #define SC_R_M4_0_INTMUX 289 -#define SC_R_M4_0_SIM 290 -#define SC_R_M4_0_WDOG 291 +#define SC_R_UNUSED15 290 +#define SC_R_UNUSED16 291 #define SC_R_M4_0_MU_0B 292 #define SC_R_M4_0_MU_0A0 293 #define SC_R_M4_0_MU_0A1 294 @@ -323,8 +323,8 @@ #define SC_R_M4_1_UART 307 #define SC_R_M4_1_I2C 308 #define SC_R_M4_1_INTMUX 309 -#define SC_R_M4_1_SIM 310 -#define SC_R_M4_1_WDOG 311 +#define SC_R_UNUSED17 310 +#define SC_R_UNUSED18 311 #define SC_R_M4_1_MU_0B 312 #define SC_R_M4_1_MU_0A0 313 #define SC_R_M4_1_MU_0A1 314 @@ -559,8 +559,7 @@ #define SC_R_DMA_5_CH2 543 #define SC_R_DMA_5_CH3 544 #define SC_R_ATTESTATION 545 -#define SC_R_PERF 546 -#define SC_R_LAST 547 +#define SC_R_LAST 546 #endif /* DT_BINDINGS_RSCRC_IMX_H */ |