diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-04-02 22:38:22 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:10:36 -0700 |
| commit | c1478a808d6ac91a447a5ccc3486966d1b7f9297 (patch) | |
| tree | 3a3f13c46f591cb25ef600c7366f8bf8abaa90d1 /include/linux/clk | |
| parent | bf295974ab610aaf18619f9b3332782cf0ed23a9 (diff) | |
ARM: tegra11: clock: Add DFLL clock source
Added dynamic frequency lock loop (DFLL) clock to Tegra11 clock tree.
Define DFLL enable, disable, set rate operations are wrappers around
the respective CL-DVFS APIs.
Removed debugfs nodes (as they duplicate DFLL clock debugfs now):
/d/tegra_cl_dvfs/cl_dvfs_enable
/d/tegra_cl_dvfs/cl_dvfs_request
Change-Id: Ibb9f2265c11cdc3231d6bc4a8dcf001fe0295929
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/94602
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Rebase-Id: R6d00deedc32fa41af7e349b95ed41293f83df95e
Diffstat (limited to 'include/linux/clk')
| -rw-r--r-- | include/linux/clk/tegra.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 735a6d17571c..7b3ceab6a80a 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -127,6 +127,7 @@ enum tegra_clk_ex_param { TEGRA_CLK_PLLD_CSI_OUT_ENB, TEGRA_CLK_PLLD_DSI_OUT_ENB, TEGRA_CLK_PLLD_MIPI_MUX_SEL, + TEGRA_CLK_DFLL_LOCK, }; void tegra_periph_reset_deassert(struct clk *c); |