diff options
| author | Changyeon Jo <cjo@nvidia.com> | 2011-07-28 09:45:50 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:20 -0800 |
| commit | a739e43b679ab7291b91da74a069f32bae40ccd6 (patch) | |
| tree | 1041a8ce56115d08386456a91bc5735cb4fe7b3b /include/media | |
| parent | c59144a19c9c43c99043623a020208e05bf30d63 (diff) | |
media: video: ov5650: add 2x2 binning mode control
Add IOCTL (OV5650_IOCTL_SET_BINNING) that user code
can access to registers which have 2x2 binning control
bits.
Bug 835589
Original-Change-Id: I07f8d3536fcdb92e8bae0af294d1a0f8523cefbc
Reviewed-on: http://git-master/r/43727
Tested-by: Changyeon Jo <cjo@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R36b1a800652a73e5b51dd56f30e0f56f6dda7d36
Diffstat (limited to 'include/media')
| -rw-r--r-- | include/media/ov5650.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/include/media/ov5650.h b/include/media/ov5650.h index d45a952eecf2..00efcec61a5f 100644 --- a/include/media/ov5650.h +++ b/include/media/ov5650.h @@ -27,10 +27,36 @@ #define OV5650_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) #define OV5650_IOCTL_SET_GAIN _IOW('o', 4, __u16) #define OV5650_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV5650_IOCTL_SET_BINNING _IOW('o', 6, __u8) #define OV5650_IOCTL_TEST_PATTERN _IOW('o', 7, enum ov5650_test_pattern) #define OV5650_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) #define OV5650_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) +/* OV5650 registers */ +#define OV5650_SRM_GRUP_ACCESS (0x3212) +#define OV5650_ARRAY_CONTROL_01 (0x3621) +#define OV5650_ANALOG_CONTROL_D (0x370D) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_CONTROL_HS_HIGH (0x3800) +#define OV5650_TIMING_CONTROL_HS_LOW (0x3801) +#define OV5650_TIMING_CONTROL_VS_HIGH (0x3802) +#define OV5650_TIMING_CONTROL_VS_LOW (0x3803) +#define OV5650_TIMING_HW_HIGH (0x3804) +#define OV5650_TIMING_HW_LOW (0x3805) +#define OV5650_TIMING_VH_HIGH (0x3806) +#define OV5650_TIMING_VH_LOW (0x3807) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_HREFST_MAN_HIGH (0x3824) +#define OV5650_TIMING_HREFST_MAN_LOW (0x3825) +#define OV5650_H_BINNING_BIT (1 << 7) +#define OV5650_H_SUBSAMPLING_BIT (1 << 6) +#define OV5650_V_BINNING_BIT (1 << 6) +#define OV5650_V_SUBSAMPLING_BIT (1 << 0) +#define OV5650_GROUP_HOLD_BIT (1 << 7) +#define OV5650_GROUP_LAUNCH_BIT (1 << 5) +#define OV5650_GROUP_HOLD_END_BIT (1 << 4) +#define OV5650_GROUP_ID(id) (id) + enum ov5650_test_pattern { TEST_PATTERN_NONE, TEST_PATTERN_COLORBARS, |