diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-02-09 19:54:15 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:36:03 +0800 |
| commit | 594b74f6622bf7e44c26bdfbfd51a33abf7defba (patch) | |
| tree | 3ef686028805d34f61ba3900b8af14a85d8d6865 /include/soc | |
| parent | 955b970c335c4e12697c89b16e953c95b7fde9aa (diff) | |
MLK-20899 soc: imx: update SCFW APIs
Update SCFW APIs to SCFW commit:
5c03342369e8 ("SCF-105: Change links in wiki index.")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/imx8/sc/ipc.h | 5 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/irq/api.h | 80 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/misc/api.h | 322 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/pad/api.h | 125 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/pm/api.h | 230 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/rm/api.h | 104 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/seco/api.h | 512 | ||||
| -rw-r--r-- | include/soc/imx8/sc/svc/timer/api.h | 57 | ||||
| -rw-r--r-- | include/soc/imx8/sc/types.h | 297 |
9 files changed, 1060 insertions, 672 deletions
diff --git a/include/soc/imx8/sc/ipc.h b/include/soc/imx8/sc/ipc.h index 332e2023f86f..de55ce73fbeb 100644 --- a/include/soc/imx8/sc/ipc.h +++ b/include/soc/imx8/sc/ipc.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -67,4 +67,5 @@ void sc_ipc_write(sc_ipc_t ipc, const void *data); int register_scu_notifier(struct notifier_block *nb); int unregister_scu_notifier(struct notifier_block *nb); -#endif /* SC_IPC_H */ +#endif /* SC_IPC_H */ + diff --git a/include/soc/imx8/sc/svc/irq/api.h b/include/soc/imx8/sc/svc/irq/api.h index 9506655f1f9d..2200e7523d77 100644 --- a/include/soc/imx8/sc/svc/irq/api.h +++ b/include/soc/imx8/sc/svc/irq/api.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -25,75 +25,78 @@ /* Defines */ -#define SC_IRQ_NUM_GROUP 6U /* Number of groups */ +#define SC_IRQ_NUM_GROUP 7U /* Number of groups */ /*! * @name Defines for sc_irq_group_t */ /*@{*/ -#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */ -#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */ -#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */ -#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */ -#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */ -#define SC_IRQ_GROUP_REBOOTED 5U /*!< Partition reboot complete */ +#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */ +#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */ +#define SC_IRQ_GROUP_REBOOTED 5U /* Partition reboot complete */ +#define SC_IRQ_GROUP_REBOOT 6U /* Partition reboot starting */ /*@}*/ /*! * @name Defines for sc_irq_temp_t */ /*@{*/ -#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */ -#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */ -#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */ -#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */ -#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */ -#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */ -#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */ -#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */ -#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */ -#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */ -#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */ -#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */ -#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */ -#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */ -#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */ -#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */ -#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */ -#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */ -#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */ -#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */ -#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */ -#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */ /*@}*/ /*! * @name Defines for sc_irq_wdog_t */ /*@{*/ -#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */ +#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */ /*@}*/ /*! * @name Defines for sc_irq_rtc_t */ /*@{*/ -#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */ +#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */ /*@}*/ /*! * @name Defines for sc_irq_wake_t */ /*@{*/ -#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */ -#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */ +#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */ +#define SC_IRQ_USR1 (1U << 2U) /* User defined 1 */ +#define SC_IRQ_USR2 (1U << 3U) /* User defined 2 */ /*@}*/ /*! * @name Defines for sc_irq_sysctr_t */ /*@{*/ -#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */ +#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */ /*@}*/ /* Types */ @@ -141,7 +144,7 @@ typedef uint8_t sc_irq_wake_t; * - SC_PARM if group invalid */ sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, - sc_irq_group_t group, uint32_t mask, sc_bool_t enable); + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); /*! * This function returns the current interrupt status (regardless if @@ -161,8 +164,9 @@ sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, * currently masked. */ sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, - sc_irq_group_t group, uint32_t *status); + sc_irq_group_t group, uint32_t *status); -#endif /* SC_IRQ_API_H */ +#endif /* SC_IRQ_API_H */ /**@}*/ + diff --git a/include/soc/imx8/sc/svc/misc/api.h b/include/soc/imx8/sc/svc/misc/api.h index bddd68ade3ba..381ed04cf03b 100644 --- a/include/soc/imx8/sc/svc/misc/api.h +++ b/include/soc/imx8/sc/svc/misc/api.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -30,7 +30,7 @@ * @name Defines for type widths */ /*@{*/ -#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */ +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */ /*@}*/ /*! Max DMA channel priority group */ @@ -40,40 +40,40 @@ * @name Defines for sc_misc_boot_status_t */ /*@{*/ -#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ -#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ /*@}*/ /*! * @name Defines for sc_misc_temp_t */ /*@{*/ -#define SC_MISC_TEMP 0U /* Temp sensor */ -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ /*@}*/ /*! * @name Defines for sc_misc_seco_auth_cmd_t */ /*@{*/ -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ -#define SC_MISC_REL_CONTAINER 2U /* Release container */ -#define SC_MISC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ +#define SC_MISC_REL_CONTAINER 2U /* Release container */ +#define SC_MISC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ /*@}*/ /*! * @name Defines for sc_misc_bt_t */ /*@{*/ -#define SC_MISC_BT_PRIMARY 0U -#define SC_MISC_BT_SECONDARY 1U -#define SC_MISC_BT_RECOVERY 2U -#define SC_MISC_BT_MANUFACTURE 3U -#define SC_MISC_BT_SERIAL 4U +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /* Serial boot */ /*@}*/ /* Types */ @@ -128,7 +128,7 @@ typedef uint8_t sc_misc_bt_t; * Refer to the [Control List](@ref CONTROLS) for valid control values. */ sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, - sc_ctrl_t ctrl, uint32_t val); + sc_ctrl_t ctrl, uint32_t val); /*! * This function gets a miscellaneous control value. @@ -148,7 +148,7 @@ sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, * Refer to the [Control List](@ref CONTROLS) for valid control values. */ sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, - sc_ctrl_t ctrl, uint32_t *val); + sc_ctrl_t ctrl, uint32_t *val); /* @} */ @@ -176,7 +176,7 @@ sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, * Default is the max priority group for the parent partition of \a pt. */ sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, - sc_misc_dma_group_t max); + sc_misc_dma_group_t max); /*! * This function configures the priority group for a DMA channel. @@ -197,7 +197,7 @@ sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, * sc_misc_set_max_dma_group(). */ sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, - sc_misc_dma_group_t group); + sc_misc_dma_group_t group); /* @} */ @@ -207,278 +207,76 @@ sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, */ /*! - * This function loads a SECO image. - * - * @param[in] ipc IPC handle - * @param[in] addr_src address of image source - * @param[in] addr_dst address of image destination - * @param[in] len lenth of image to load - * @param[in] fw SC_TRUE = firmware load - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if word fuse index param out of range or invalid - * - SC_ERR_UNAVAILABLE if SECO not available - * - * This is used to load images via the SECO. Examples include SECO - * Firmware and IVT/CSF data used for authentication. These are usually - * loaded into SECO TCM. \a addr_src is in secure memory. - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_image_load() instead. */ sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, - sc_faddr_t addr_dst, uint32_t len, - sc_bool_t fw); + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); /*! - * This function is used to authenticate a SECO image or command. - * - * @param[in] ipc IPC handle - * @param[in] cmd authenticate command - * @param[in] addr address of/or metadata - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if word fuse index param out of range or invalid - * - SC_ERR_UNAVAILABLE if SECO not available - * - * This is used to authenticate a SECO image or issue a security - * command. \a addr often points to an container. It is also - * just data (or even unused) for some commands. - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_authenticate() instead. */ sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc, - sc_misc_seco_auth_cmd_t cmd, - sc_faddr_t addr); + sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr); /*! - * This function securely writes a group of fuse words. - * - * @param[in] ipc IPC handle - * @param[in] addr address of message block - * - * @return Returns and error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_UNAVAILABLE if SECO not available - * - * Note \a addr must be a pointer to a signed message block. - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_fuse_write() instead. */ sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); /*! - * This function securely enables debug. - * - * @param[in] ipc IPC handle - * @param[in] addr address of message block - * - * @return Returns and error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_UNAVAILABLE if SECO not available - * - * Note \a addr must be a pointer to a signed message block. - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_enable_debug() instead. */ sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); /*! - * This function updates the lifecycle of the device. - * - * @param[in] ipc IPC handle - * @param[in] change desired lifecycle transistion - * - * @return Returns and error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_UNAVAILABLE if SECO not available - * - * This message is used for going from Open to NXP Closed to OEM Closed. - * Note \a change is NOT the new desired lifecycle. It is a lifecycle - * transition as documented in the Security Reference Manual (SRM). - * - * If any SECO request fails or only succeeds because the part is in an - * "OEM open" lifecycle, then a request to transition from "NXP closed" - * to "OEM closed" will also fail. For example, booting a signed container - * when the OEM SRK is not fused will succeed, but as it is an abnormal - * situation, a subsequent request to transition the lifecycle will return - * an error. + * @deprecated Use sc_seco_forward_lifecycle() instead. */ sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change); /*! - * This function updates the lifecycle to one of the return lifecycles. - * - * @param[in] ipc IPC handle - * @param[in] addr address of message block - * - * @return Returns and error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_UNAVAILABLE if SECO not available - * - * Note \a addr must be a pointer to a signed message block. - * - * To switch back to NXP states (Full Field Return), message must be signed - * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM - * SRK. - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_return_lifecycle() instead. */ sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); /*! - * This function is used to return the SECO FW build info. - * - * @param[in] ipc IPC handle - * @param[out] version pointer to return build number - * @param[out] commit pointer to return commit ID (git SHA-1) + * @deprecated Use sc_seco_build_info() instead. */ -void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit); +void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); /*! - * This function is used to return SECO chip info. - * - * @param[in] ipc IPC handle - * @param[out] lc pointer to return lifecycle - * @param[out] monotonic pointer to return monotonic counter - * @param[out] uid_l pointer to return UID (lower 32 bits) - * @param[out] uid_h pointer to return UID (upper 32 bits) + * @deprecated Use sc_seco_chip_info() instead. */ sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, - uint16_t *monotonic, uint32_t *uid_l, - uint32_t *uid_h); + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h); /*! - * This function is used to set the attestation mode. Only the owner of - * the SC_R_ATTESTATION resource may make this call. - * - * @param[in] ipc IPC handle - * @param[in] mode mode - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if \a mode is invalid - * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller - * - SC_ERR_UNAVAILABLE if SECO not available - * - * This is used to set the SECO attestation mode. This can be prover - * or verfier. See the Security Reference Manual (SRM) for more on the - * suported modes, mode values, and mode behavior. + * @deprecated Use sc_seco_attest_mode() instead. */ sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode); /*! - * This function is used to request atestation. Only the owner of - * the SC_R_ATTESTATION resource may make this call. - * - * @param[in] ipc IPC handle - * @param[in] nonce unique value - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller - * - SC_ERR_UNAVAILABLE if SECO not available - * - * This is used to ask SECO to perform an attestation. The result depends - * on the attestation mode. After this call, the signature can be - * requested or a verify can be requested. - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_attest() instead. */ sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce); /*! - * This function is used to retrieve the attestation public key. - * Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource - * may make this call. - * - * @param[in] ipc IPC handle - * @param[in] addr address to write response - * - * Result will be written to \a addr. The \a addr parmater must point - * to an address SECO can access. It must be 64-bit aligned. There - * should be 96 bytes of space. - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if \a addr bad or attestation has not been requested - * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller - * - SC_ERR_UNAVAILABLE if SECO not available - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_get_attest_pkey() instead. */ sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr); /*! - * This function is used to retrieve attestation signature and parameters. - * Mode must be provider. Only the owner of the SC_R_ATTESTATION resource - * may make this call. - * - * @param[in] ipc IPC handle - * @param[in] addr address to write response - * - * Result will be written to \a addr. The \a addr parmater must point - * to an address SECO can access. It must be 64-bit aligned. There - * should be 120 bytes of space. - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if \a addr bad or attestation has not been requested - * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller - * - SC_ERR_UNAVAILABLE if SECO not available - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_get_attest_sign() instead. */ sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr); /*! - * This function is used to verify attestation. Mode must be verifier. - * Only the owner of the SC_R_ATTESTATION resource may make this call. - * - * @param[in] ipc IPC handle - * @param[in] addr address of signature - * - * The \a addr parmater must point to an address SECO can access. It must be - * 64-bit aligned. - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if \a addr bad or attestation has not been requested - * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller - * - SC_ERR_UNAVAILABLE if SECO not available - * - SC_ERR_FAIL if signature doesn't match - * - * See the Security Reference Manual (SRM) for more info. + * @deprecated Use sc_seco_attest_verify() instead. */ sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr); /*! - * This function is used to commit into the fuses any new SRK revocation - * and FW version information that have been found in the primary and - * secondary containers. - * - * @param[in] ipc IPC handle - * @param[in,out] info pointer to information type to be committed - * - * The return \a info will contain what was actually committed. - * - * @return Returns an error code (SC_ERR_NONE = success). - * - * Return errors codes: - * - SC_ERR_PARM if \a info is invalid - * - SC_ERR_UNAVAILABLE if SECO not available + * @deprecated Use sc_seco_commit() instead. */ sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info); @@ -517,7 +315,8 @@ sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable); * @param[out] build pointer to return build number * @param[out] commit pointer to return commit ID (git SHA-1) */ -void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit); +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, + uint32_t *commit); /*! * This function is used to return the device's unique ID. @@ -526,7 +325,8 @@ void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit); * @param[out] id_l pointer to return lower 32-bit of ID [31:0] * @param[out] id_h pointer to return upper 32-bits of ID [63:32] */ -void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h); +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, + uint32_t *id_h); /* @} */ @@ -556,8 +356,7 @@ void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h); * FISType and PM_Port. */ sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, - sc_rsrc_t resource_mst, uint16_t ari, - sc_bool_t enable); + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable); /*! * This function reports boot status. @@ -606,7 +405,9 @@ sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu); sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); /*! - * This function writes a given fuse word index. + * This function writes a given fuse word index. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. * * @param[in] ipc IPC handle * @param[in] word fuse word index @@ -621,6 +422,7 @@ sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); * * Return errors codes: * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access * - SC_ERR_NOACCESS if write operation failed * - SC_ERR_LOCKED if write operation is locked */ @@ -643,9 +445,11 @@ sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val); * * Return errors codes: * - SC_ERR_PARM if parameters invalid + * - SC_ERR_NOACCESS if caller does not own the resource + * - SC_ERR_NOPOWER if power domain of resource not powered */ sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, - sc_misc_temp_t temp, int16_t celsius, int8_t tenths); + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); /*! * This function gets a temp sensor value. @@ -661,10 +465,10 @@ sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, * Return errors codes: * - SC_ERR_PARM if parameters invalid * - SC_ERR_BUSY if temp not ready yet (time delay after power on) + * - SC_ERR_NOPOWER if power domain of resource not powered */ sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, - sc_misc_temp_t temp, int16_t * celsius, - int8_t * tenths); + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths); /*! * This function returns the boot device. @@ -705,8 +509,22 @@ void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); */ sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum); +/*! + * This function calls the board IOCTL function. + * + * @param[in] ipc IPC handle + * @param[in,out] parm1 pointer to pass parameter 1 + * @param[in,out] parm2 pointer to pass parameter 2 + * @param[in,out] parm3 pointer to pass parameter 3 + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3); + /* @} */ -#endif /* SC_MISC_API_H */ +#endif /* SC_MISC_API_H */ /**@}*/ + diff --git a/include/soc/imx8/sc/svc/pad/api.h b/include/soc/imx8/sc/svc/pad/api.h index 975ce08957dd..2bcf109ea0a3 100644 --- a/include/soc/imx8/sc/svc/pad/api.h +++ b/include/soc/imx8/sc/svc/pad/api.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -70,79 +70,79 @@ * @name Defines for type widths */ /*@{*/ -#define SC_PAD_MUX_W 3U /* Width of mux parameter */ +#define SC_PAD_MUX_W 3U /* Width of mux parameter */ /*@}*/ /*! * @name Defines for sc_pad_config_t */ /*@{*/ -#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ -#define SC_PAD_CONFIG_OD 1U /* Open Drain */ -#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ -#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ +#define SC_PAD_CONFIG_OD 1U /* Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ /*@}*/ /*! * @name Defines for sc_pad_iso_t */ /*@{*/ -#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ -#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ -#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ -#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ /*@}*/ /*! * @name Defines for sc_pad_28fdsoi_dse_t */ /*@{*/ -#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ -#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */ -#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ -#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */ -#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */ /*@}*/ /*! * @name Defines for sc_pad_28fdsoi_ps_t */ /*@{*/ -#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ -#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ -#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ -#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ /*@}*/ /*! * @name Defines for sc_pad_28fdsoi_pus_t */ /*@{*/ -#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ -#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ -#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ -#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ /*@}*/ /*! * @name Defines for sc_pad_wakeup_t */ /*@{*/ -#define SC_PAD_WAKEUP_OFF 0U /* Off */ -#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ -#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ -#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ -#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ -#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ +#define SC_PAD_WAKEUP_OFF 0U /* Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ /*@}*/ /* Types */ @@ -216,7 +216,7 @@ typedef uint8_t sc_pad_wakeup_t; * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, - uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); /*! * This function gets the mux settings for a pad. This includes @@ -237,8 +237,7 @@ sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, - uint8_t *mux, sc_pad_config_t *config, - sc_pad_iso_t *iso); + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso); /*! * This function configures the general purpose pad control. This @@ -295,7 +294,8 @@ sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl); * * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ -sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup); +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t wakeup); /*! * This function gets the wakeup mode of a pad. @@ -312,7 +312,8 @@ sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup); * * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ -sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup); +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t *wakeup); /*! * This function configures a pad. @@ -340,8 +341,8 @@ sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup); * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, - sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, - sc_pad_wakeup_t wakeup); + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup); /*! * This function gets a pad's config. @@ -366,8 +367,8 @@ sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, - sc_pad_config_t *config, sc_pad_iso_t *iso, - uint32_t *ctrl, sc_pad_wakeup_t *wakeup); + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup); /* @} */ @@ -437,8 +438,7 @@ sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, - sc_pad_28fdsoi_dse_t dse, - sc_pad_28fdsoi_ps_t ps); + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps); /*! * This function gets the pad control specific to 28FDSOI. @@ -458,8 +458,7 @@ sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, - sc_pad_28fdsoi_dse_t *dse, - sc_pad_28fdsoi_ps_t *ps); + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps); /*! * This function configures the pad control specific to 28FDSOI. @@ -482,9 +481,8 @@ sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, - sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, - sc_pad_28fdsoi_pus_t pus, sc_bool_t pke, - sc_bool_t pue); + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue); /*! * This function gets the pad control specific to 28FDSOI. @@ -507,9 +505,8 @@ sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, - sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, - sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke, - sc_bool_t *pue); + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue); /*! * This function configures the compensation control specific to 28FDSOI. @@ -536,9 +533,8 @@ sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, * operation (e.g. some Ethernet pads). */ sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, - uint8_t compen, sc_bool_t fastfrz, - uint8_t rasrcp, uint8_t rasrcn, - sc_bool_t nasrc_sel, sc_bool_t psw_ovr); + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); /*! * This function gets the compensation control specific to 28FDSOI. @@ -564,13 +560,12 @@ sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, * Refer to the SoC [Pad List](@ref PADS) for valid pad values. */ sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, - uint8_t *compen, sc_bool_t *fastfrz, - uint8_t *rasrcp, uint8_t *rasrcn, - sc_bool_t *nasrc_sel, sc_bool_t *compok, - uint8_t *nasrc, sc_bool_t *psw_ovr); + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr); /* @} */ -#endif /* SC_PAD_API_H */ +#endif /* SC_PAD_API_H */ /**@}*/ + diff --git a/include/soc/imx8/sc/svc/pm/api.h b/include/soc/imx8/sc/svc/pm/api.h index cd201ba29b83..48b296e76024 100644 --- a/include/soc/imx8/sc/svc/pm/api.h +++ b/include/soc/imx8/sc/svc/pm/api.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -33,10 +33,10 @@ * @name Defines for type widths */ /*@{*/ -#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ -#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ -#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ -#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ /*@}*/ /*! @@ -49,108 +49,108 @@ * @name Defines for ALL parameters */ /*@{*/ -#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */ +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */ /*@}*/ /*! * @name Defines for sc_pm_power_mode_t */ /*@{*/ -#define SC_PM_PW_MODE_OFF 0U /* Power off */ -#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ -#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ -#define SC_PM_PW_MODE_ON 3U /* Power on */ +#define SC_PM_PW_MODE_OFF 0U /* Power off */ +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /* Power on */ /*@}*/ /*! * @name Defines for sc_pm_clk_t */ /*@{*/ -#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ -#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ -#define SC_PM_CLK_PER 2U /* Peripheral clock */ -#define SC_PM_CLK_PHY 3U /* Phy clock */ -#define SC_PM_CLK_MISC 4U /* Misc clock */ -#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ -#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ -#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ -#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ -#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ -#define SC_PM_CLK_CPU 2U /* CPU clock */ -#define SC_PM_CLK_PLL 4U /* PLL */ -#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ +#define SC_PM_CLK_PER 2U /* Peripheral clock */ +#define SC_PM_CLK_PHY 3U /* Phy clock */ +#define SC_PM_CLK_MISC 4U /* Misc clock */ +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /* CPU clock */ +#define SC_PM_CLK_PLL 4U /* PLL */ +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ /*@}*/ /*! * @name Defines for sc_pm_clk_mode_t */ /*@{*/ -#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ -#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ -#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ -#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ -#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ -#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ /*@}*/ /*! * @name Defines for sc_pm_clk_parent_t */ /*@{*/ -#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL. */ -#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */ -#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */ -#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */ -#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */ +#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */ /*@}*/ /*! * @name Defines for sc_pm_reset_type_t */ /*@{*/ -#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ -#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ -#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ /*@}*/ /*! * @name Defines for sc_pm_reset_reason_t */ /*@{*/ -#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ -#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ -#define SC_PM_RESET_REASON_SW 2U /* Software reset */ -#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ -#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ -#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ -#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ -#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ -#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ -#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ -#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ -#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ -#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ /*@}*/ /*! * @name Defines for sc_pm_sys_if_t */ /*@{*/ -#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ -#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ -#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ -#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ /*@}*/ /*! * @name Defines for sc_pm_wake_src_t */ /*@{*/ -#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */ -#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ -#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ -#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ -#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */ +#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */ /*@}*/ /* Types */ @@ -247,7 +247,7 @@ sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode); * individual resource mode set using sc_pm_set_resource_power_mode(). */ sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, - sc_pm_power_mode_t mode); + sc_pm_power_mode_t mode); /*! * This function gets the power mode of a partition. @@ -262,7 +262,7 @@ sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, * - SC_ERR_PARM if invalid partition */ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, - sc_pm_power_mode_t *mode); + sc_pm_power_mode_t *mode); /*! * This function sets the power mode of a resource. @@ -300,7 +300,7 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, * infrastructure (bus fabrics, clock domains, etc.). */ sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_power_mode_t mode); + sc_pm_power_mode_t mode); /*! * This function sets the power mode for all the resources owned @@ -326,9 +326,7 @@ sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, * implement some aspects of virtualization. */ sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, - sc_rm_pt_t pt, - sc_pm_power_mode_t mode, - sc_rsrc_t exclude); + sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude); /*! * This function gets the power mode of a resource. @@ -343,7 +341,7 @@ sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, * returned does not reflect the power mode of the partition.. */ sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_power_mode_t *mode); + sc_pm_power_mode_t *mode); /*! * This function requests the low power mode some of the resources @@ -364,7 +362,7 @@ sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, * */ sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_power_mode_t mode); + sc_pm_power_mode_t mode); /*! * This function requests low-power mode entry for CPU/cluster @@ -387,8 +385,7 @@ sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, * */ sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_power_mode_t mode, - sc_pm_wake_src_t wake_src); + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); /*! * This function is used to set the resume address of a CPU. @@ -405,7 +402,7 @@ sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, * resource (CPU) owner */ sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, - sc_faddr_t address); + sc_faddr_t address); /*! * This function is used to set parameters for CPU resume from @@ -424,7 +421,7 @@ sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, * resource (CPU) owner */ sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, - sc_bool_t isPrimary, sc_faddr_t address); + sc_bool_t isPrimary, sc_faddr_t address); /*! * This function requests the power mode configuration for system-level @@ -444,9 +441,7 @@ sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, * */ sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_sys_if_t sys_if, - sc_pm_power_mode_t hpm, - sc_pm_power_mode_t lpm); + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); /* @} */ @@ -475,7 +470,7 @@ sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. */ sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); /*! * This function gets the rate of a resource's clock/PLL. @@ -496,7 +491,7 @@ sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. */ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); /*! * This function enables/disables a resource's clock. @@ -524,7 +519,7 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, * Refer to the [Clock List](@ref CLOCKS) for valid clock values. */ sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); /*! * This function sets the parent of a resource's clock. @@ -548,7 +543,7 @@ sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, * Refer to the [Clock List](@ref CLOCKS) for valid clock values. */ sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_clk_t clk, sc_pm_clk_parent_t parent); + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); /*! * This function gets the parent of a resource's clock. @@ -569,7 +564,7 @@ sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, * Refer to the [Clock List](@ref CLOCKS) for valid clock values. */ sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, - sc_pm_clk_t clk, sc_pm_clk_parent_t * parent); + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); /* @} */ @@ -601,7 +596,7 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); * This function gets a caller's reset reason. * * @param[in] ipc IPC handle - * @param[out] reason pointer to return reset reason + * @param[out] reason pointer to return the reset reason * * This function returns the reason a partition was reset. If the reason * is POR, then the system reset reason will be returned. @@ -615,6 +610,24 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); /*! + * This function gets the partition that caused a reset. + * + * @param[in] ipc IPC handle + * @param[out] pt pointer to return the resetting partition + * + * If the reset reason obtained via sc_pm_reset_reason() is POR then the + * result from this function will be 0. Some SECO causes of reset will + * also return 0. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the partition info will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! * This function is used to boot a partition. * * @param[in] ipc IPC handle @@ -636,8 +649,8 @@ sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); * sc_pm_reboot_partition(). */ sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, - sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, - sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); /*! * This function is used to reboot the caller's partition. @@ -650,12 +663,8 @@ sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, * power, clocks, etc.) is reset. The boot SW of the booting CPU must be * able to handle peripherals that that are not reset. * - * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset. - * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW - * of the booting CPU must be able to handle peripherals and SC state that - * that are not reset. - * - * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. * * If this function returns, then the reset did not occur due to an * invalid parameter. @@ -674,12 +683,8 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); * power, clocks, etc.) is reset. The boot SW of the booting CPU must be * able to handle peripherals that that are not reset. * - * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset. - * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW - * of the booting CPU must be able to handle peripherals and SC state that - * that are not reset. - * - * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. * * @return Returns an error code (SC_ERR_NONE = success). * @@ -692,9 +697,26 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); * possible. SC state (partitions, power, clocks, etc.) is reset. The * boot SW of the booting CPU must be able to handle peripherals that * that are not reset. + * + * If board_reboot_part() returns a non-0 mask, then the reboot will + * be delayed until all partitions indicated in the mask have called + * sc_pm_reboot_continue() to continue the boot. */ sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, - sc_pm_reset_type_t type); + sc_pm_reset_type_t type); + +/*! + * This function is used to continue the reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to continue + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt); /*! * This function is used to start/stop a CPU. @@ -722,7 +744,7 @@ sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, * sc_pm_boot(). */ sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, - sc_faddr_t address); + sc_faddr_t address); /*! * This function is used to reset a CPU. @@ -743,8 +765,22 @@ sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, */ void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address); +/*! + * This function returns a bool indicating if a partition was started. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to check + * + * @return Returns a bool (SC_TRUE = started). + * + * Note this indicates if a partition was started. It does not indicate if a + * partition is currently running or in a low power state. + */ +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); + /* @} */ -#endif /* SC_PM_API_H */ +#endif /* SC_PM_API_H */ /**@}*/ + diff --git a/include/soc/imx8/sc/svc/rm/api.h b/include/soc/imx8/sc/svc/rm/api.h index 7bd2bf4d84ec..0491c8d8f844 100644 --- a/include/soc/imx8/sc/svc/rm/api.h +++ b/include/soc/imx8/sc/svc/rm/api.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -32,44 +32,44 @@ * @name Defines for type widths */ /*@{*/ -#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ -#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ -#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ -#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ -#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ -#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ /*@}*/ /*! * @name Defines for ALL parameters */ /*@{*/ -#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */ -#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */ +#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */ /*@}*/ /*! * @name Defines for sc_rm_spa_t */ /*@{*/ -#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ -#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ -#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ -#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ /*@}*/ /*! * @name Defines for sc_rm_perm_t */ /*@{*/ -#define SC_RM_PERM_NONE 0U /* No access */ -#define SC_RM_PERM_SEC_R 1U /* Secure RO */ -#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ -#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ -#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ -#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ -#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ -#define SC_RM_PERM_FULL 7U /* Full access */ +#define SC_RM_PERM_NONE 0U /* No access */ +#define SC_RM_PERM_SEC_R 1U /* Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /* Full access */ /*@}*/ /* Types */ @@ -148,8 +148,7 @@ typedef uint8_t sc_rm_perm_t; * controls of that master. */ sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, - sc_bool_t isolated, sc_bool_t restricted, - sc_bool_t grant, sc_bool_t coherent); + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent); /*! * This function makes a partition confidential. @@ -224,7 +223,8 @@ sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc); * Assumes no assigned resources or memory regions yet! The number of static * DID is fixed by the SC at boot. */ -sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did); +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_did_t did); /*! * This function locks a partition. @@ -269,7 +269,8 @@ sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, * - SC_ERR_LOCKED if either partition is locked */ -sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent); /*! * This function moves all movable resources/pads owned by a source partition @@ -299,7 +300,7 @@ sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); * - SC_ERR_LOCKED if either partition is locked */ sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, - sc_bool_t move_rsrc, sc_bool_t move_pads); + sc_bool_t move_rsrc, sc_bool_t move_pads); /* @} */ @@ -332,7 +333,8 @@ sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, * of the owner, * - SC_ERR_LOCKED if the owning partition or \a pt is locked */ -sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource); /*! * This function flags resources as movable or not. @@ -355,7 +357,7 @@ sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); * resources from moving. */ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, - sc_rsrc_t resource_lst, sc_bool_t movable); + sc_rsrc_t resource_lst, sc_bool_t movable); /*! * This function flags all of a subsystem's resources as movable @@ -374,7 +376,7 @@ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, * resources owned by the caller are set. */ sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, - sc_bool_t movable); + sc_bool_t movable); /*! * This function sets attributes for a resource which is a bus master (i.e. @@ -399,8 +401,7 @@ sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, * changed if the caller's partition is secure. */ sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, - sc_rm_spa_t sa, sc_rm_spa_t pa, - sc_bool_t smmu_bypass); + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass); /*! * This function sets the StreamID for a resource which is a bus master (i.e. @@ -424,7 +425,7 @@ sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, * bypass. */ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, - sc_rm_sid_t sid); + sc_rm_sid_t sid); /*! * This function sets access permissions for a peripheral resource. @@ -448,7 +449,7 @@ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, * also allows the access permissions of SC_R_SYSTEM to be set. */ sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, - sc_rm_pt_t pt, sc_rm_perm_t perm); + sc_rm_pt_t pt, sc_rm_perm_t perm); /*! * This function gets ownership status of a resource. @@ -463,6 +464,23 @@ sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); /*! + * This function is used to get the owner of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * @param[out] pt pointer to return owning partition + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid + * + * If \a resource is out of range then SC_ERR_PARM is returned. + */ +sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/*! * This function is used to test if a resource is a bus master. * * @param[in] ipc IPC handle @@ -499,7 +517,7 @@ sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource); * - SC_PARM if \a resource is out of range */ sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, - sc_rm_sid_t *sid); + sc_rm_sid_t *sid); /* @} */ @@ -534,7 +552,7 @@ sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, * caller to access. */ sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, - sc_faddr_t addr_start, sc_faddr_t addr_end); + sc_faddr_t addr_start, sc_faddr_t addr_end); /*! * This function requests that the SC split a memory region. @@ -561,8 +579,7 @@ sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, * Note the new region must start or end on the split region. */ sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, - sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, - sc_faddr_t addr_end); + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end); /*! * This function requests that the SC fragment a memory region. @@ -588,7 +605,7 @@ sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, * It then splits it as required and returns the extracted region. */ sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret, - sc_faddr_t addr_start, sc_faddr_t addr_end); + sc_faddr_t addr_start, sc_faddr_t addr_end); /*! * This function frees a memory region. @@ -629,7 +646,7 @@ sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr); * region containing the range specified. */ sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, - sc_faddr_t addr_start, sc_faddr_t addr_end); + sc_faddr_t addr_start, sc_faddr_t addr_end); /*! * This function assigns ownership of a memory region. @@ -672,7 +689,7 @@ sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr); * memory region based on the attributes of a transaction from bus master. */ sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, - sc_rm_pt_t pt, sc_rm_perm_t perm); + sc_rm_pt_t pt, sc_rm_perm_t perm); /*! * This function gets ownership status of a memory region. @@ -701,7 +718,7 @@ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); * - SC_PARM if \a mr is out of range */ sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, - sc_faddr_t *addr_start, sc_faddr_t *addr_end); + sc_faddr_t *addr_start, sc_faddr_t *addr_end); /* @} */ @@ -750,7 +767,7 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); * pads from moving. */ sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, - sc_pad_t pad_lst, sc_bool_t movable); + sc_pad_t pad_lst, sc_bool_t movable); /*! * This function gets ownership status of a pad. @@ -780,6 +797,7 @@ void sc_rm_dump(sc_ipc_t ipc); /* @} */ -#endif /* SC_RM_API_H */ +#endif /* SC_RM_API_H */ /**@}*/ + diff --git a/include/soc/imx8/sc/svc/seco/api.h b/include/soc/imx8/sc/svc/seco/api.h new file mode 100644 index 000000000000..54c911a32ae9 --- /dev/null +++ b/include/soc/imx8/sc/svc/seco/api.h @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/*! + * Header file containing the public API for the System Controller (SC) + * Security (SECO) function. + * + * @addtogroup SECO_SVC (SVC) Security Service + * + * Module for the Security (SECO) service. + * + * @{ + */ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include <soc/imx8/sc/types.h> +#include <soc/imx8/sc/svc/rm/api.h> + +/* Defines */ + +/*! + * @name Defines for sc_seco_auth_cmd_t + */ +/*@{*/ +#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */ +#define SC_SECO_REL_CONTAINER 2U /* Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +/*@}*/ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef uint8_t sc_seco_auth_cmd_t; + +/* Functions */ + +/*! + * @name Image Functions + * @{ + */ + +/*! + * This function loads a SECO image. + * + * @param[in] ipc IPC handle + * @param[in] addr_src address of image source + * @param[in] addr_dst address of image destination + * @param[in] len lenth of image to load + * @param[in] fw SC_TRUE = firmware load + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to load images via the SECO. Examples include SECO + * Firmware and IVT/CSF data used for authentication. These are usually + * loaded into SECO TCM. \a addr_src is in secure memory. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * This function is used to authenticate a SECO image or command. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to authenticate a SECO image or issue a security + * command. \a addr often points to an container. It is also + * just data (or even unused) for some commands. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/* @} */ + +/*! + * @name Lifecycle Functions + * @{ + */ + +/*! + * This function updates the lifecycle of the device. + * + * @param[in] ipc IPC handle + * @param[in] change desired lifecycle transistion + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This message is used for going from Open to NXP Closed to OEM Closed. + * Note \a change is NOT the new desired lifecycle. It is a lifecycle + * transition as documented in the Security Reference Manual (SRM). + * + * If any SECO request fails or only succeeds because the part is in an + * "OEM open" lifecycle, then a request to transition from "NXP closed" + * to "OEM closed" will also fail. For example, booting a signed container + * when the OEM SRK is not fused will succeed, but as it is an abnormal + * situation, a subsequent request to transition the lifecycle will return + * an error. + */ +sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change); + +/*! + * This function updates the lifecycle to one of the return lifecycles. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer to a signed message block. + * + * To switch back to NXP states (Full Field Return), message must be signed + * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM + * SRK. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to commit into the fuses any new SRK revocation + * and FW version information that have been found in the primary and + * secondary containers. + * + * @param[in] ipc IPC handle + * @param[in,out] info pointer to information type to be committed + * + * The return \a info will contain what was actually committed. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a info is invalid + * - SC_ERR_UNAVAILABLE if SECO not available + */ +sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info); + +/* @} */ + +/*! + * @name Attestation Functions + * @{ + */ + +/*! + * This function is used to set the attestation mode. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] mode mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a mode is invalid + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to set the SECO attestation mode. This can be prover + * or verfier. See the Security Reference Manual (SRM) for more on the + * suported modes, mode values, and mode behavior. + */ +sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode); + +/*! + * This function is used to request atestation. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] nonce unique value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This is used to ask SECO to perform an attestation. The result depends + * on the attestation mode. After this call, the signature can be + * requested or a verify can be requested. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce); + +/*! + * This function is used to retrieve the attestation public key. + * Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 96 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to retrieve attestation signature and parameters. + * Mode must be provider. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 120 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to verify attestation. Mode must be verifier. + * Only the owner of the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address of signature + * + * The \a addr parmater must point to an address SECO can access. It must be + * 64-bit aligned. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller + * - SC_ERR_UNAVAILABLE if SECO not available + * - SC_ERR_FAIL if signature doesn't match + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr); + +/* @} */ + +/*! + * @name Key Functions + * @{ + */ + +/*! + * This function is used to generate a SECO key blob. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] load_addr load address + * @param[in] export_addr export address + * @param[in] max_size max export size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is used to encapsulate sensitive keys in a specific structure + * called a blob, which provides both confidentiality and integrity protection. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size); + +/*! + * This function is used to load a SECO key. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] addr key address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is used to install private cryptographic keys encapsulated + * in a blob previously generated by SECO. The controller can be either the + * IEE or the VPU. The blob header carries the controller type and the key + * size, as provided by the user when generating the key blob. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id, + sc_faddr_t addr); + +/* @} */ + +/*! + * @name Manufacturing Protection Functions + * @{ + */ + +/*! + * This function is used to get the manufacturing protection public key. + * + * @param[in] ipc IPC handle + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is supported only in OEM-closed lifecycle. It generates + * the mfg public key and stores it in a specific location in the secure + * memory. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + uint16_t dst_size); + +/*! + * This function is used to update the manufacturing protection message + * register. + * + * @param[in] ipc IPC handle + * @param[in] addr data address + * @param[in] size size + * @param[in] lock lock_reg + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is supported only in OEM-closed lifecycle. It updates the + * content of the MPMR (Manufacturing Protection Message register of 256 + * bits). This register will be appended to the input-data message when + * generating the signature. Please refer to the CAAM block guide for details. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + uint8_t size, uint8_t lock); + +/*! + * This function is used to get the manufacturing protection signature. + * + * @param[in] ipc IPC handle + * @param[in] msg_addr message address + * @param[in] msg_size message size + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_UNAVAILABLE if SECO not available + * + * This function is used to generate an ECDSA signature for an input-data + * message and to store it in a specific location in the secure memory. It + * is only supported in OEM-closed lifecycle. In order to get the ECDSA + * signature, the RNG must be initialized. In case it has not been started + * an error will be returned. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size); + +/* @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used to return the SECO FW build info. + * + * @param[in] ipc IPC handle + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); + +/*! + * This function is used to return SECO chip info. + * + * @param[in] ipc IPC handle + * @param[out] lc pointer to return lifecycle + * @param[out] monotonic pointer to return monotonic counter + * @param[out] uid_l pointer to return UID (lower 32 bits) + * @param[out] uid_h pointer to return UID (upper 32 bits) + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h); + +/*! + * This function securely enables debug. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer to a signed message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to return an event from the SECO error log. + * + * @param[in] ipc IPC handle + * @param[out] idx index of event to return + * @param[out] event pointer to return event + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Read of \a idx 0 captures events from SECO. Loop starting + * with 0 until an error is returned to dump all events. + */ +sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, + uint32_t *event); + +/* @} */ + +/*! + * @name Miscellaneous Functions + * @{ + */ + +/*! + * This function securely writes a group of fuse words. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available + * + * Note \a addr must be a pointer to a signed message block. + * + * See the Security Reference Manual (SRM) for more info. + */ +sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); + +/* @} */ + +#endif /* SC_SECO_API_H */ + +/**@}*/ + diff --git a/include/soc/imx8/sc/svc/timer/api.h b/include/soc/imx8/sc/svc/timer/api.h index a38afc3d1db5..6c80ceaf53f6 100644 --- a/include/soc/imx8/sc/svc/timer/api.h +++ b/include/soc/imx8/sc/svc/timer/api.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -32,18 +32,18 @@ * @name Defines for type widths */ /*@{*/ -#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ /*@}*/ /*! * @name Defines for sc_timer_wdog_action_t */ /*@{*/ -#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ -#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ -#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ -#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ -#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ /*@}*/ /* Types */ @@ -76,7 +76,8 @@ typedef uint32_t sc_timer_wdog_time_t; * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED * = locked). */ -sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout); +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t timeout); /*! * This function sets the watchdog pre-timeout in milliseconds. If not @@ -93,7 +94,7 @@ sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout); * @return Returns an error code (SC_ERR_NONE = success). */ sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, - sc_timer_wdog_time_t pre_timeout); + sc_timer_wdog_time_t pre_timeout); /*! * This function starts the watchdog. @@ -141,9 +142,8 @@ sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc); * @return Returns an error code (SC_ERR_NONE = success). */ sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, - sc_timer_wdog_time_t *timeout, - sc_timer_wdog_time_t *max_timeout, - sc_timer_wdog_time_t *remaining_time); + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time); /*! * This function gets the status of the watchdog of a partition. All @@ -158,10 +158,8 @@ sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, * * @return Returns an error code (SC_ERR_NONE = success). */ -sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, - sc_bool_t *enb, - sc_timer_wdog_time_t *timeout, - sc_timer_wdog_time_t *remaining_time); +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time); /*! * This function configures the action to be taken when a watchdog @@ -181,7 +179,7 @@ sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, * - SC_ERR_LOCKED if the watchdog is locked */ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, - sc_rm_pt_t pt, sc_timer_wdog_action_t action); + sc_rm_pt_t pt, sc_timer_wdog_action_t action); /* @} */ @@ -210,8 +208,7 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, * - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM */ sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, - uint8_t day, uint8_t hour, uint8_t min, - uint8_t sec); + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); /*! * This function gets the RTC time. @@ -227,8 +224,7 @@ sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, * @return Returns an error code (SC_ERR_NONE = success). */ sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, - uint8_t *day, uint8_t *hour, uint8_t *min, - uint8_t *sec); + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec); /*! * This function gets the RTC time in seconds since 1/1/1970. @@ -251,7 +247,8 @@ sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); * @param[in] min minute (0-59) * @param[in] sec second (0-59) * - * Note this alarm setting clears when the alarm is triggered. + * Note this alarm setting clears when the alarm is triggered. This is an + * absolute time. * * @return Returns an error code (SC_ERR_NONE = success). * @@ -259,8 +256,7 @@ sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); * - SC_ERR_PARM if invalid time/date parameters */ sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, - uint8_t day, uint8_t hour, uint8_t min, - uint8_t sec); + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); /*! * This function sets the RTC alarm (periodic mode). @@ -270,6 +266,8 @@ sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, * * @return Returns an error code (SC_ERR_NONE = success). * + * Note this is a relative time. + * * Return errors: * - SC_ERR_PARM if invalid time/date parameters */ @@ -318,7 +316,8 @@ sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count); * @param[in] ipc IPC handle * @param[in] ticks number of 8MHz cycles * - * Note this alarm setting clears when the alarm is triggered. + * Note the \a ticks parameter is an absolute time. This alarm + * setting clears when the alarm is triggered. * * @return Returns an error code (SC_ERR_NONE = success). * @@ -333,12 +332,15 @@ sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks); * @param[in] ipc IPC handle * @param[in] ticks number of 8MHz cycles * + * Note the \a ticks parameter is a relative time. + * * @return Returns an error code (SC_ERR_NONE = success). * * Return errors: * - SC_ERR_PARM if invalid time/date parameters */ -sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks); +sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, + uint64_t ticks); /*! * This function cancels the SYSCTR alarm. @@ -356,6 +358,7 @@ sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc); /* @} */ -#endif /* SC_TIMER_API_H */ +#endif /* SC_TIMER_API_H */ /**@}*/ + diff --git a/include/soc/imx8/sc/types.h b/include/soc/imx8/sc/types.h index 9d4f22ec7e1f..e7ef9a4b645b 100644 --- a/include/soc/imx8/sc/types.h +++ b/include/soc/imx8/sc/types.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,156 +22,156 @@ * @name Defines for common frequencies */ /*@{*/ -#define SC_32KHZ 32768U /* 32KHz */ -#define SC_10MHZ 10000000U /* 10MHz */ -#define SC_20MHZ 20000000U /* 20MHz */ -#define SC_25MHZ 25000000U /* 25MHz */ -#define SC_27MHZ 27000000U /* 27MHz */ -#define SC_40MHZ 40000000U /* 40MHz */ -#define SC_45MHZ 45000000U /* 45MHz */ -#define SC_50MHZ 50000000U /* 50MHz */ -#define SC_60MHZ 60000000U /* 60MHz */ -#define SC_66MHZ 66666666U /* 66MHz */ -#define SC_74MHZ 74250000U /* 74.25MHz */ -#define SC_80MHZ 80000000U /* 80MHz */ -#define SC_83MHZ 83333333U /* 83MHz */ -#define SC_84MHZ 84375000U /* 84.37MHz */ -#define SC_100MHZ 100000000U /* 100MHz */ -#define SC_125MHZ 125000000U /* 125MHz */ -#define SC_133MHZ 133333333U /* 133MHz */ -#define SC_135MHZ 135000000U /* 135MHz */ -#define SC_150MHZ 150000000U /* 150MHz */ -#define SC_160MHZ 160000000U /* 160MHz */ -#define SC_166MHZ 166666666U /* 166MHz */ -#define SC_175MHZ 175000000U /* 175MHz */ -#define SC_180MHZ 180000000U /* 180MHz */ -#define SC_200MHZ 200000000U /* 200MHz */ -#define SC_250MHZ 250000000U /* 250MHz */ -#define SC_266MHZ 266666666U /* 266MHz */ -#define SC_300MHZ 300000000U /* 300MHz */ -#define SC_312MHZ 312500000U /* 312.5MHZ */ -#define SC_320MHZ 320000000U /* 320MHz */ -#define SC_325MHZ 325000000U /* 325MHz */ -#define SC_333MHZ 333333333U /* 333MHz */ -#define SC_350MHZ 350000000U /* 350MHz */ -#define SC_372MHZ 372000000U /* 372MHz */ -#define SC_375MHZ 375000000U /* 375MHz */ -#define SC_400MHZ 400000000U /* 400MHz */ -#define SC_500MHZ 500000000U /* 500MHz */ -#define SC_594MHZ 594000000U /* 594MHz */ -#define SC_625MHZ 625000000U /* 625MHz */ -#define SC_640MHZ 640000000U /* 640MHz */ -#define SC_648MHZ 648000000U /* 648MHz */ -#define SC_650MHZ 650000000U /* 650MHz */ -#define SC_667MHZ 666666667U /* 667MHz */ -#define SC_675MHZ 675000000U /* 675MHz */ -#define SC_700MHZ 700000000U /* 700MHz */ -#define SC_720MHZ 720000000U /* 720MHz */ -#define SC_750MHZ 750000000U /* 750MHz */ -#define SC_753MHZ 753000000U /* 753MHz */ -#define SC_793MHZ 793000000U /* 793MHz */ -#define SC_800MHZ 800000000U /* 800MHz */ -#define SC_850MHZ 850000000U /* 850MHz */ -#define SC_858MHZ 858000000U /* 858MHz */ -#define SC_900MHZ 900000000U /* 900MHz */ -#define SC_953MHZ 953000000U /* 953MHz */ -#define SC_963MHZ 963000000U /* 963MHz */ -#define SC_1000MHZ 1000000000U /* 1GHz */ -#define SC_1060MHZ 1060000000U /* 1.06GHz */ -#define SC_1068MHZ 1068000000U /* 1.068GHz */ -#define SC_1121MHZ 1121000000U /* 1.121GHz */ -#define SC_1173MHZ 1173000000U /* 1.173GHz */ -#define SC_1188MHZ 1188000000U /* 1.188GHz */ -#define SC_1260MHZ 1260000000U /* 1.26GHz */ -#define SC_1278MHZ 1278000000U /* 1.278GHz */ -#define SC_1280MHZ 1280000000U /* 1.28GHz */ -#define SC_1300MHZ 1300000000U /* 1.3GHz */ -#define SC_1313MHZ 1313000000U /* 1.313GHz */ -#define SC_1345MHZ 1345000000U /* 1.345GHz */ -#define SC_1400MHZ 1400000000U /* 1.4GHz */ -#define SC_1500MHZ 1500000000U /* 1.5GHz */ -#define SC_1600MHZ 1600000000U /* 1.6GHz */ -#define SC_1800MHZ 1800000000U /* 1.8GHz */ -#define SC_2000MHZ 2000000000U /* 2.0GHz */ -#define SC_2112MHZ 2112000000U /* 2.12GHz */ +#define SC_32KHZ 32768U /* 32KHz */ +#define SC_10MHZ 10000000U /* 10MHz */ +#define SC_20MHZ 20000000U /* 20MHz */ +#define SC_25MHZ 25000000U /* 25MHz */ +#define SC_27MHZ 27000000U /* 27MHz */ +#define SC_40MHZ 40000000U /* 40MHz */ +#define SC_45MHZ 45000000U /* 45MHz */ +#define SC_50MHZ 50000000U /* 50MHz */ +#define SC_60MHZ 60000000U /* 60MHz */ +#define SC_66MHZ 66666666U /* 66MHz */ +#define SC_74MHZ 74250000U /* 74.25MHz */ +#define SC_80MHZ 80000000U /* 80MHz */ +#define SC_83MHZ 83333333U /* 83MHz */ +#define SC_84MHZ 84375000U /* 84.37MHz */ +#define SC_100MHZ 100000000U /* 100MHz */ +#define SC_125MHZ 125000000U /* 125MHz */ +#define SC_133MHZ 133333333U /* 133MHz */ +#define SC_135MHZ 135000000U /* 135MHz */ +#define SC_150MHZ 150000000U /* 150MHz */ +#define SC_160MHZ 160000000U /* 160MHz */ +#define SC_166MHZ 166666666U /* 166MHz */ +#define SC_175MHZ 175000000U /* 175MHz */ +#define SC_180MHZ 180000000U /* 180MHz */ +#define SC_200MHZ 200000000U /* 200MHz */ +#define SC_250MHZ 250000000U /* 250MHz */ +#define SC_266MHZ 266666666U /* 266MHz */ +#define SC_300MHZ 300000000U /* 300MHz */ +#define SC_312MHZ 312500000U /* 312.5MHZ */ +#define SC_320MHZ 320000000U /* 320MHz */ +#define SC_325MHZ 325000000U /* 325MHz */ +#define SC_333MHZ 333333333U /* 333MHz */ +#define SC_350MHZ 350000000U /* 350MHz */ +#define SC_372MHZ 372000000U /* 372MHz */ +#define SC_375MHZ 375000000U /* 375MHz */ +#define SC_400MHZ 400000000U /* 400MHz */ +#define SC_500MHZ 500000000U /* 500MHz */ +#define SC_594MHZ 594000000U /* 594MHz */ +#define SC_625MHZ 625000000U /* 625MHz */ +#define SC_640MHZ 640000000U /* 640MHz */ +#define SC_648MHZ 648000000U /* 648MHz */ +#define SC_650MHZ 650000000U /* 650MHz */ +#define SC_667MHZ 666666667U /* 667MHz */ +#define SC_675MHZ 675000000U /* 675MHz */ +#define SC_700MHZ 700000000U /* 700MHz */ +#define SC_720MHZ 720000000U /* 720MHz */ +#define SC_750MHZ 750000000U /* 750MHz */ +#define SC_753MHZ 753000000U /* 753MHz */ +#define SC_793MHZ 793000000U /* 793MHz */ +#define SC_800MHZ 800000000U /* 800MHz */ +#define SC_850MHZ 850000000U /* 850MHz */ +#define SC_858MHZ 858000000U /* 858MHz */ +#define SC_900MHZ 900000000U /* 900MHz */ +#define SC_953MHZ 953000000U /* 953MHz */ +#define SC_963MHZ 963000000U /* 963MHz */ +#define SC_1000MHZ 1000000000U /* 1GHz */ +#define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1068MHZ 1068000000U /* 1.068GHz */ +#define SC_1121MHZ 1121000000U /* 1.121GHz */ +#define SC_1173MHZ 1173000000U /* 1.173GHz */ +#define SC_1188MHZ 1188000000U /* 1.188GHz */ +#define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1278MHZ 1278000000U /* 1.278GHz */ +#define SC_1280MHZ 1280000000U /* 1.28GHz */ +#define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1313MHZ 1313000000U /* 1.313GHz */ +#define SC_1345MHZ 1345000000U /* 1.345GHz */ +#define SC_1400MHZ 1400000000U /* 1.4GHz */ +#define SC_1500MHZ 1500000000U /* 1.5GHz */ +#define SC_1600MHZ 1600000000U /* 1.6GHz */ +#define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_2000MHZ 2000000000U /* 2.0GHz */ +#define SC_2112MHZ 2112000000U /* 2.12GHz */ /*@}*/ /*! * @name Defines for 24M related frequencies */ /*@{*/ -#define SC_8MHZ 8000000U /* 8MHz */ -#define SC_12MHZ 12000000U /* 12MHz */ -#define SC_19MHZ 19800000U /* 19.8MHz */ -#define SC_24MHZ 24000000U /* 24MHz */ -#define SC_48MHZ 48000000U /* 48MHz */ -#define SC_120MHZ 120000000U /* 120MHz */ -#define SC_132MHZ 132000000U /* 132MHz */ -#define SC_144MHZ 144000000U /* 144MHz */ -#define SC_192MHZ 192000000U /* 192MHz */ -#define SC_211MHZ 211200000U /* 211.2MHz */ -#define SC_240MHZ 240000000U /* 240MHz */ -#define SC_264MHZ 264000000U /* 264MHz */ -#define SC_352MHZ 352000000U /* 352MHz */ -#define SC_360MHZ 360000000U /* 360MHz */ -#define SC_384MHZ 384000000U /* 384MHz */ -#define SC_396MHZ 396000000U /* 396MHz */ -#define SC_432MHZ 432000000U /* 432MHz */ -#define SC_480MHZ 480000000U /* 480MHz */ -#define SC_600MHZ 600000000U /* 600MHz */ -#define SC_744MHZ 744000000U /* 744MHz */ -#define SC_792MHZ 792000000U /* 792MHz */ -#define SC_864MHZ 864000000U /* 864MHz */ -#define SC_960MHZ 960000000U /* 960MHz */ -#define SC_1056MHZ 1056000000U /* 1056MHz */ -#define SC_1104MHZ 1104000000U /* 1104MHz */ -#define SC_1200MHZ 1200000000U /* 1.2GHz */ -#define SC_1464MHZ 1464000000U /* 1.464GHz */ -#define SC_2400MHZ 2400000000U /* 2.4GHz */ +#define SC_8MHZ 8000000U /* 8MHz */ +#define SC_12MHZ 12000000U /* 12MHz */ +#define SC_19MHZ 19800000U /* 19.8MHz */ +#define SC_24MHZ 24000000U /* 24MHz */ +#define SC_48MHZ 48000000U /* 48MHz */ +#define SC_120MHZ 120000000U /* 120MHz */ +#define SC_132MHZ 132000000U /* 132MHz */ +#define SC_144MHZ 144000000U /* 144MHz */ +#define SC_192MHZ 192000000U /* 192MHz */ +#define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_240MHZ 240000000U /* 240MHz */ +#define SC_264MHZ 264000000U /* 264MHz */ +#define SC_352MHZ 352000000U /* 352MHz */ +#define SC_360MHZ 360000000U /* 360MHz */ +#define SC_384MHZ 384000000U /* 384MHz */ +#define SC_396MHZ 396000000U /* 396MHz */ +#define SC_432MHZ 432000000U /* 432MHz */ +#define SC_480MHZ 480000000U /* 480MHz */ +#define SC_600MHZ 600000000U /* 600MHz */ +#define SC_744MHZ 744000000U /* 744MHz */ +#define SC_792MHZ 792000000U /* 792MHz */ +#define SC_864MHZ 864000000U /* 864MHz */ +#define SC_960MHZ 960000000U /* 960MHz */ +#define SC_1056MHZ 1056000000U /* 1056MHz */ +#define SC_1104MHZ 1104000000U /* 1104MHz */ +#define SC_1200MHZ 1200000000U /* 1.2GHz */ +#define SC_1464MHZ 1464000000U /* 1.464GHz */ +#define SC_2400MHZ 2400000000U /* 2.4GHz */ /*@}*/ /*! * @name Defines for A/V related frequencies */ /*@{*/ -#define SC_62MHZ 62937500U /* 62.9375MHz */ -#define SC_755MHZ 755250000U /* 755.25MHz */ +#define SC_62MHZ 62937500U /* 62.9375MHz */ +#define SC_755MHZ 755250000U /* 755.25MHz */ /*@}*/ /*! * @name Defines for type widths */ /*@{*/ -#define SC_BOOL_W 1U /* Width of sc_bool_t */ -#define SC_ERR_W 4U /* Width of sc_err_t */ -#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ -#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ +#define SC_BOOL_W 1U /* Width of sc_bool_t */ +#define SC_ERR_W 4U /* Width of sc_err_t */ +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ /*@}*/ /*! * @name Defines for sc_bool_t */ /*@{*/ -#define SC_FALSE ((sc_bool_t) 0U) /* False */ -#define SC_TRUE ((sc_bool_t) 1U) /* True */ +#define SC_FALSE ((sc_bool_t) 0U) /* False */ +#define SC_TRUE ((sc_bool_t) 1U) /* True */ /*@}*/ /*! * @name Defines for sc_err_t. */ /*@{*/ -#define SC_ERR_NONE 0U /* Success */ -#define SC_ERR_VERSION 1U /* Incompatible API version */ -#define SC_ERR_CONFIG 2U /* Configuration error */ -#define SC_ERR_PARM 3U /* Bad parameter */ -#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ -#define SC_ERR_LOCKED 5U /* Permission error (locked) */ -#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ -#define SC_ERR_NOTFOUND 7U /* Not found */ -#define SC_ERR_NOPOWER 8U /* No power */ -#define SC_ERR_IPC 9U /* Generic IPC error */ -#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ -#define SC_ERR_FAIL 11U /* General I/O failure */ +#define SC_ERR_NONE 0U /* Success */ +#define SC_ERR_VERSION 1U /* Incompatible API version */ +#define SC_ERR_CONFIG 2U /* Configuration error */ +#define SC_ERR_PARM 3U /* Bad parameter */ +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ +#define SC_ERR_LOCKED 5U /* Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /* Not found */ +#define SC_ERR_NOPOWER 8U /* No power */ +#define SC_ERR_IPC 9U /* Generic IPC error */ +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /* General I/O failure */ #define SC_ERR_LAST 12U /*@}*/ @@ -727,7 +727,7 @@ #define SC_R_ATTESTATION 545U #define SC_R_PERF 546U #define SC_R_LAST 547U -#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /* All resources */ +#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /* All resources */ /*@}*/ /* NOTE - please add by replacing some of the UNUSED from above! */ @@ -793,7 +793,7 @@ #define SC_C_SYNC_CTRL 55U #define SC_C_LAST 56U -#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /* All pads */ +#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /* All pads */ /* Types */ @@ -834,45 +834,46 @@ typedef uint16_t sc_pad_t; /* Extra documentation of standard types */ #ifdef DOXYGEN - /*! - * Type used to declare an 8-bit integer. - */ +/*! + * Type used to declare an 8-bit integer. + */ typedef __INT8_TYPE__ int8_t; - /*! - * Type used to declare a 16-bit integer. - */ +/*! + * Type used to declare a 16-bit integer. + */ typedef __INT16_TYPE__ int16_t; - /*! - * Type used to declare a 32-bit integer. - */ +/*! + * Type used to declare a 32-bit integer. + */ typedef __INT32_TYPE__ int32_t; - /*! - * Type used to declare a 64-bit integer. - */ +/*! + * Type used to declare a 64-bit integer. + */ typedef __INT64_TYPE__ int64_t; - /*! - * Type used to declare an 8-bit unsigned integer. - */ +/*! + * Type used to declare an 8-bit unsigned integer. + */ typedef __UINT8_TYPE__ uint8_t; - /*! - * Type used to declare a 16-bit unsigned integer. - */ +/*! + * Type used to declare a 16-bit unsigned integer. + */ typedef __UINT16_TYPE__ uint16_t; - /*! - * Type used to declare a 32-bit unsigned integer. - */ +/*! + * Type used to declare a 32-bit unsigned integer. + */ typedef __UINT32_TYPE__ uint32_t; - /*! - * Type used to declare a 64-bit unsigned integer. - */ +/*! + * Type used to declare a 64-bit unsigned integer. + */ typedef __UINT64_TYPE__ uint64_t; #endif -#endif /* SC_TYPES_H */ +#endif /* SC_TYPES_H */ + |