dt-bindings: pinctrl: imx8mm: fix 2a762bfc93fe

Correct copy/past errors with UART2 pinfunctions.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 14 insertions, 11 deletions

diff --git a/include/dt-bindings/pinctrl/pins-imx8mm.h b/include/dt-bindings/pinctrl/pins-imx8mm.h
index bbefaf721712..3c638e6cf2e2 100644
--- a/include/dt-bindings/pinctrl/pins-imx8mm.h
+++ b/include/dt-bindings/pinctrl/pins-imx8mm.h
@@ -481,34 +481,37 @@
 #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 	                                    0x1D0 0x438 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
-#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x1 0x0
-#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x1 0x2
-#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x1 0x2
-#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x4 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x4 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x4 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B                               0x1D0 0x438 0x4F8 0x1 0x3
-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B                               0x1D0 0x438 0x000 0x1 0x0
-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D0 0x438 0x000 0x1 0x0
-#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B                               0x1D0 0x438 0x4F8 0x1 0x3
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B                               0x1D4 0x43C 0x4F8 0x4 0x3
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B                               0x1D4 0x43C 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B                               0x1D4 0x43C 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B                               0x1D4 0x43C 0x4F8 0x4 0x3
 #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2                                0x1D8 0x440 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
-#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0x1D8 0x440 0x4FC 0x4 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX                                 0x1D8 0x440 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX                                 0x1D8 0x440 0x4FC 0x4 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_RX                                 0x1D8 0x440 0x4FC 0x4 0x2
 #define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX                                 0x1D8 0x440 0x000 0x4 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
-#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX                                  0x1DC 0x444 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX                                  0x1DC 0x444 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX                                  0x1DC 0x444 0x4FC 0x4 0x3
 #define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX                                  0x1DC 0x444 0x4FC 0x4 0x3
+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_TX                                  0x1DC 0x444 0x000 0x4 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0