diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2015-02-28 16:27:12 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2015-05-08 17:23:17 +0800 |
| commit | c25fa07591482ac78d07f7d6fca05a858d36bd6e (patch) | |
| tree | 17e5a1d6275ca867675153577a67e1b860d98f50 /include | |
| parent | 3de0bbde05177170a0f19542f80f997f826327b5 (diff) | |
MLK-10475-2 ARM: imx6q: Add PRE/PRG mux bits to GPR syscon definition
We've got the following mux options for PRE and PRG embedded in i.MX6Q R2.
------------------------------------------------------------------
|\ | PRG0/IPU0 | PRG1/IPU1 |
| mux |-----------------------------------------------------------|
| \ |ch0/ch23 |ch1/ch27 |ch2/ch28 |ch0/ch23 |ch1/ch27 |ch2/ch28 |
|------------------------------------------------------------------|
| PRE0 | fixed | n/a | n/a | n/a | n/a | n/a |
|------------------------------------------------------------------|
| PRE1 | n/a | A(2b'00)| A(2b'01)| n/a | A(2b'10)| A(2b'11)|
|------------------------------------------------------------------|
| PRE2 | n/a | B(2b'00)| B(2b'01)| n/a | B(2b'10)| B(2b'11)|
|------------------------------------------------------------------|
| PRE3 | n/a | n/a | n/a | fixed | n/a | n/a |
------------------------------------------------------------------
(Note - A: GPR5 bit12-13, B: GPR5 bit14-15)
This patch adds the PRE and PRG muxing bits and masks/shifts to GPR syscon
definition.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index 7f1b362c0faa..02657cc28678 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -244,6 +244,18 @@ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) #define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) +#define IMX6Q_GPR5_PRE_PRG_SEL0_MASK (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_SHIFT 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN1 (0x0 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN2 (0x1 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN1 (0x2 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN2 (0x3 << 12) +#define IMX6Q_GPR5_PRE_PRG_SEL1_MASK (0x3 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_SHIFT 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN1 (0x0 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN2 (0x1 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN1 (0x2 << 14) +#define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN2 (0x3 << 14) #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) |