diff options
author | Adam Jiang <chaoj@nvidia.com> | 2012-02-29 11:07:36 +0900 |
---|---|---|
committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-03-15 08:31:24 -0700 |
commit | 570a5790a9ce288c093ea9ae838cf8e7e8aa8fe6 (patch) | |
tree | 39a149a6becfdc385a4fa12f82565194a5ff5298 /include | |
parent | 9c75057dfff925b4e42e8a07ffb2a2efa9e6bd14 (diff) |
dtv: Added description for interface configuration
fixed bug 947324
Change-Id: Ib85ee5d7e67def321cbde49ad41e2b194e1bd2e8
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/86483
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'include')
-rw-r--r-- | include/media/tegra_dtv.h | 56 |
1 files changed, 43 insertions, 13 deletions
diff --git a/include/media/tegra_dtv.h b/include/media/tegra_dtv.h index 5ecaa47dea82..798e3e3bf9c0 100644 --- a/include/media/tegra_dtv.h +++ b/include/media/tegra_dtv.h @@ -24,19 +24,19 @@ #define TEGRA_DTV_IOCTL_STOP _IO(TEGRA_DTV_MAGIC, 1) struct tegra_dtv_hw_config { - int clk_edge; - int byte_swz_enabled; - int bit_swz_enabled; - - int protocol_sel; - int clk_mode; - int fec_size; - int body_size; - int body_valid_sel; - int start_sel; - int err_pol; - int psync_pol; - int valid_pol; + int clk_edge; /*< clock edge to be used to sample DTV input signals */ + int byte_swz_enabled; /*< byte order during deserialization */ + int bit_swz_enabled; /*< bit order during deserialization */ + + int protocol_sel; /*< VD pin configuration. */ + int clk_mode; /*< input clock characteristics */ + int fec_size; /*< FEC size */ + int body_size; /*< BODY size */ + int body_valid_sel; /*< VALID signal gate */ + int start_sel; /*< START of the package */ + int err_pol; /*< ERROR pin polarity */ + int psync_pol; /*< PSYNC pin polarity */ + int valid_pol; /*< VALID pin polarity */ }; #define TEGRA_DTV_IOCTL_SET_HW_CONFIG _IOW(TEGRA_DTV_MAGIC, 2, \ @@ -44,6 +44,36 @@ struct tegra_dtv_hw_config { #define TEGRA_DTV_IOCTL_GET_HW_CONFIG _IOR(TEGRA_DTV_MAGIC, 3, \ struct tegra_dtv_hw_config *) +/** + * clock edge settings for clk_edge + * + * RISE_EDGE: sample input signal at rising edge + * FALL_EDGE: sample input signal at falling edge + */ +enum { + TEGRA_DTV_CLK_RISE_EDGE = 0, + TEGRA_DTV_CLK_FALL_EDGE, +}; + +/** + * swizzle settings for byte_swz and bit_swz + * + * ENABLE: enable swizzle during deserialization + * DISABLE: disable swizzle during deserialization + * + * If swizzling is enabled then deserialized data will be re-ordered to + * fit the required format for tegra. + * + * For example, if raw BGR data is inputed into DTV interface, the data + * could be swizzled into RGB. + * + * For TS/MPEG-2 stream, please disable this feature. + */ +enum { + TEGRA_DTV_SWZ_DISABLE = 0, + TEGRA_DTV_SWZ_ENABLE, +}; + /* for selecting the pin configuration for VD(valid). * NONE : ERROR is tied to 0, PSYNC is tied to 0 * ERROR: ERROR is tied to VD, PSYNC is tied to 0 |