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authorNick Piggin <npiggin@suse.de>2008-05-22 00:10:56 +1000
committerPaul Mackerras <paulus@samba.org>2008-06-16 15:00:20 +1000
commit598056d5af8fef1dbe8f96f5c2b641a528184e5a (patch)
tree4839b7a63cade4751527f94307a05687710311ad /include
parenta9653cf540d407fb75deb3db65a1be6c81d53ee0 (diff)
[POWERPC] Fix rmb to order cacheable vs. noncacheable
lwsync is explicitly defined not to have any effect on the ordering of accesses to device memory, so it cannot be used for rmb(). sync appears to be the only barrier which fits the bill. Signed-off-by: Nick Piggin <npiggin@suse.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/system.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 2b6559a6d113..5235f875b932 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -34,7 +34,7 @@
* SMP since it is only used to order updates to system memory.
*/
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
-#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
+#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
#define read_barrier_depends() do { } while(0)