diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2013-12-19 13:54:28 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2013-12-23 11:38:28 +0800 |
| commit | 18f2def0ce32866de1005567978bdc731dc24175 (patch) | |
| tree | 4d99e2b586f746a45e6d2dcc1c5ecec327a213b0 /include | |
| parent | 5cdc6210832b02ccebd325819ff27ca0479e7562 (diff) | |
ENGR00292775 mipi csi2: Refine register access
The original mipi csi2 driver uses readl()/writel()
to access the 32 bit mipi csi2 registers in the
following way where info->mipi_csi2_base is a pointer
which points to a 32 bit I/O memory cell of the mipi
csi2's base address:
writel(value, info->mipi_csi2_base + offset);
readl(info->mipi_csi2_base + offset);
This makes the register offset values shrink 4 times,
comparing to the offset values documented in the
reference manual. For example, we need to change the
offset value from 0x004 to 0x001 so that we may access
the register MIPI_CSI2_N_LANES correctly.
This patch redefines the type of info->mipi_csi2_base
to 'void __iomem *', then the offset values can be the
same to what they are documented. Also, the macro names
for the registers are aligned to the documentation.
Acked-by: Robby Cai <R63905@freescale.com>
Cc: Oliver Brown <oliver.brown@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mipi_csi2.h | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/include/linux/mipi_csi2.h b/include/linux/mipi_csi2.h index 9cc1f89ef964..7dc76fd293f8 100644 --- a/include/linux/mipi_csi2.h +++ b/include/linux/mipi_csi2.h @@ -19,22 +19,24 @@ #ifndef __INCLUDE_MIPI_CSI2_H #define __INCLUDE_MIPI_CSI2_H -/* mipi csi2 register */ -#define CSI2_VERSION 0x000 -#define CSI2_N_LANES (0x004/4) -#define CSI2_PHY_SHUTDOWNZ (0x008/4) -#define CSI2_DPHY_RSTZ (0x00c/4) -#define CSI2_RESETN (0x010/4) -#define CSI2_PHY_STATE (0x014/4) -#define CSI2_DATA_IDS_1 (0x018/4) -#define CSI2_DATA_IDS_2 (0x01c/4) -#define CSI2_ERR1 (0x020/4) -#define CSI2_ERR2 (0x024/4) -#define CSI2_MSK1 (0x028/4) -#define CSI2_MSK2 (0x02c/4) -#define CSI2_PHY_TST_CTRL0 (0x030/4) -#define CSI2_PHY_TST_CTRL1 (0x034/4) -#define CSI2_SFT_RESET (0xf00/4) +/* MIPI CSI2 registers */ +#define MIPI_CSI2_REG(offset) (offset) + +#define MIPI_CSI2_VERSION MIPI_CSI2_REG(0x000) +#define MIPI_CSI2_N_LANES MIPI_CSI2_REG(0x004) +#define MIPI_CSI2_PHY_SHUTDOWNZ MIPI_CSI2_REG(0x008) +#define MIPI_CSI2_DPHY_RSTZ MIPI_CSI2_REG(0x00c) +#define MIPI_CSI2_CSI2_RESETN MIPI_CSI2_REG(0x010) +#define MIPI_CSI2_PHY_STATE MIPI_CSI2_REG(0x014) +#define MIPI_CSI2_DATA_IDS_1 MIPI_CSI2_REG(0x018) +#define MIPI_CSI2_DATA_IDS_2 MIPI_CSI2_REG(0x01c) +#define MIPI_CSI2_ERR1 MIPI_CSI2_REG(0x020) +#define MIPI_CSI2_ERR2 MIPI_CSI2_REG(0x024) +#define MIPI_CSI2_MASK1 MIPI_CSI2_REG(0x028) +#define MIPI_CSI2_MASK2 MIPI_CSI2_REG(0x02c) +#define MIPI_CSI2_PHY_TST_CTRL0 MIPI_CSI2_REG(0x030) +#define MIPI_CSI2_PHY_TST_CTRL1 MIPI_CSI2_REG(0x034) +#define MIPI_CSI2_SFT_RESET MIPI_CSI2_REG(0xf00) /* mipi data type */ #define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */ |