diff options
| author | Richard Zhu <richard.zhu@freescale.com> | 2014-10-16 14:54:40 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:01:37 -0600 |
| commit | 3ddb6b40b078da8c9a0122bda02faad7a9bced78 (patch) | |
| tree | 9782abac56e4cb731bdedaa51166b8a37d4ceca9 /include | |
| parent | 128a269b183441b4fe89ba82e99084011921c047 (diff) | |
MLK-10009-2 ARM: imx6sx: Add imx6sx pcie related gpr bits definitions
Add imx6sx pcie related gpr bits definitions.
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
(cherry picked from commit 991fb25d62e3e2f550f98732f5bc00eeb98f78e3)
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index b0608dafe874..0730e2aad5af 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -319,6 +319,7 @@ #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) +#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) @@ -461,6 +462,14 @@ #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) +#define IMX6SX_GPR5_PCIE_BTNRST BIT(19) +#define IMX6SX_GPR5_PCIE_PERST BIT(18) + +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) +#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30) +#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0) +#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0) + /* For imx6dl iomux gpr register field definitions */ #define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) #define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) |