diff options
| author | Andy Duan <fugang.duan@nxp.com> | 2017-02-10 16:25:14 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2017-06-08 20:59:52 +0800 |
| commit | de0c0f85fe4fa170e85786bbda77f4351637ecef (patch) | |
| tree | 2f402979734ae1c4dbd52f0365db7202cfd1e354 /include | |
| parent | e9ab08af76ec9f3e2a90e16a8fb70ebe15370537 (diff) | |
MLK-13910: ARM: imx7d: clk: correct enet clock CCGR register offset
Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
IMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.
IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/imx7d-clock.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index 4fce0647b97c..0afab1be1f12 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -453,6 +454,8 @@ #define IMX7D_CAAM_CLK 440 #define IMX7D_PXP_IPG_CLK 441 #define IMX7D_PXP_AXI_CLK 442 -#define IMX7D_CLK_END 443 +#define IMX7D_ENET1_IPG_ROOT_CLK 443 +#define IMX7D_ENET2_IPG_ROOT_CLK 444 +#define IMX7D_CLK_END 445 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ |