diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-08-30 15:34:04 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2018-10-29 11:10:38 +0800 |
| commit | 50d889f517095736c399d46143ba02ce3abfba6f (patch) | |
| tree | dafad6920dbb6519ba71aa684939c73c1f4ea8d7 /include | |
| parent | 0c7f97668a1e516d014d327826620bf8f8190f47 (diff) | |
MLK-19413-24 gpu: imx: dpu: common: Add store9 support for sync mode fixup
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/video/dpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/video/dpu.h b/include/video/dpu.h index c23a14e7e6c1..0cf4671ebcd4 100644 --- a/include/video/dpu.h +++ b/include/video/dpu.h @@ -667,6 +667,12 @@ u32 layerblend_perfresult(struct dpu_layerblend *lb); struct dpu_layerblend *dpu_lb_get(struct dpu_soc *dpu, int id); void dpu_lb_put(struct dpu_layerblend *lb); +/* Store Unit */ +struct dpu_store; +void store_pixengcfg_syncmode_fixup(struct dpu_store *st, bool enable); +struct dpu_store *dpu_st_get(struct dpu_soc *dpu, int id); +void dpu_st_put(struct dpu_store *st); + /* Timing Controller Unit */ struct dpu_tcon; int tcon_set_fmt(struct dpu_tcon *tcon, u32 bus_format); |