diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-07-01 19:50:59 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-25 18:43:48 -0700 |
| commit | d580981423e8c40218badcc1ba9a11c32ad96dec (patch) | |
| tree | b74712e56ab418684638c400a99ecdf00ad9df89 /include | |
| parent | 486ad27011945b5f7b1d622780eeea7a49e0872d (diff) | |
mmc: core: SDXC speed class support
Unlike SDSC and SDHC, for SDXC cards CMD20 needs to be
issued to meet the class performance for speed class
recording. Adding mmc_speed_class_control() which should
be used by an AV recording app/utility before starting
recording on an SDXC card.
Bug 820469
Bug 769962
Change-Id: Ic89fd6e475e6bf7ea610e43c78a752dcb444d477
Reviewed-on: http://git-master/r/39394
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mmc/host.h | 3 | ||||
| -rw-r--r-- | include/linux/mmc/sd.h | 11 |
2 files changed, 14 insertions, 0 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 62ffcb05fb78..8c0c7a2728b0 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -328,6 +328,9 @@ int mmc_host_enable(struct mmc_host *host); int mmc_host_disable(struct mmc_host *host); int mmc_host_lazy_disable(struct mmc_host *host); int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *); +int mmc_speed_class_control(struct mmc_host *host, + unsigned int speed_class_ctrl_arg); + static inline void mmc_set_disable_delay(struct mmc_host *host, unsigned int disable_delay) diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h index 0f70416b0a49..b4dbcd39379a 100644 --- a/include/linux/mmc/sd.h +++ b/include/linux/mmc/sd.h @@ -18,7 +18,10 @@ #define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ #define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ #define SD_VOLTAGE_SWITCH 11 /* ac R1 */ + + /* class 2 */ #define SD_SEND_TUNING_PATTERN 19 /* adtc R1 */ +#define SD_SPEED_CLASS_CONTROL 20 /* ac R1b */ /* class 10 */ #define SD_SWITCH 6 /* adtc [31:0] See below R1 */ @@ -86,5 +89,13 @@ #define SD_SWITCH_ACCESS_DEF 0 #define SD_SWITCH_ACCESS_HS 1 +/* + * SD_SPEED_CLASS_CONTROL definitions + */ +#define SD_SPEED_CLASS_CONTROL_START_REC 0 +#define SD_SPEED_CLASS_CONTROL_CREATE_DIR 1 +#define SD_SPEED_CLASS_CONTROL_END_REC_WITHOUT_MOVE 2 +#define SD_SPEED_CLASS_CONTROL_END_REC_WITH_MOVE 3 + #endif |