diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-02-06 16:42:46 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2015-04-24 23:01:35 +0800 |
| commit | 1d8e30150b252409cbadcc545c9c5464ae0df598 (patch) | |
| tree | b8b3c57d39fb8b02b6fe097d545783a8b116dbb9 /include | |
| parent | a3847045f894cea3d0ffc523412a4f1c56073230 (diff) | |
MLK-10463-1 ARM: imx: init ENET RGMII tx clock source
Init ENET RGMII tx clock source, set GPR5[9] to select clock from
internal PLL_enet. And set phy VDDIO to 1.8V that get better signal
quality.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index f6515b5dd369..7f1b362c0faa 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -243,6 +243,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) |