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authorWayne Zou <b36644@freescale.com>2012-04-13 08:19:46 +0800
committerFrank Li <Frank.Li@freescale.com>2012-04-13 18:56:36 +0800
commit4d5c8d7aa0d5137d337048dd82c71c77c3954fa5 (patch)
tree8e9548191bddbe1e087fcfeb87e739f7db7740b8 /include
parent256588d1074c4f168b7391e7962502b95a46de49 (diff)
ENGR00179513-2 IPU: Add TILED_NV12_FRAME_SIZE macro for consistency
VPU needs 4K align buffer address for tiled format data output. Use this macro for IPU/V4L2/Apps to calculate the frame/field size. Signed-off-by: Wayne Zou <b36644@freescale.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/ipu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/ipu.h b/include/linux/ipu.h
index 973cfe9b45a5..e0c9e90c2804 100644
--- a/include/linux/ipu.h
+++ b/include/linux/ipu.h
@@ -141,6 +141,8 @@ typedef enum {
#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
/*! @} */
#define IPU_PIX_FMT_TILED_NV12_MBALIGN (16)
+#define TILED_NV12_FRAME_SIZE(w, h) \
+ (ALIGN((w) * (h), SZ_4K) + ALIGN((w) * (h) / 2, SZ_4K))
/* IPU device */
typedef enum {
RGB_CS,