diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2015-04-21 18:14:21 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2015-05-08 16:35:02 +0800 |
| commit | f3234805919f2bdc7480faed92815faa8fa81074 (patch) | |
| tree | bbc6b55168b1e86ae9c2a03c7adf6c284b3f57c8 /include | |
| parent | 7f7adf482dd8fd4a92f99b46bde822037acceb07 (diff) | |
MLK-10712 mxc IPUv3: PRG: Fix PRE/PRG muxing
The i.MX6QP IOMUX_GPR5 PRE_PRG_SEL0/1 fields control the PRE/PRG muxing.
The muxing could be described by the following table.
------------------------------------------------------------------
|\ | PRG0/IPU0 | PRG1/IPU1 |
| mux |-----------------------------------------------------------|
| \ |ch0/ch23 |ch1/ch27 |ch2/ch28 |ch0/ch23 |ch1/ch27 |ch2/ch28 |
|------------------------------------------------------------------|
| PRE0 | fixed | n/a | n/a | n/a | n/a | n/a |
|------------------------------------------------------------------|
| PRE1 | n/a | A(2b'00)| A(2b'01)| n/a | A(2b'10)| A(2b'11)|
|------------------------------------------------------------------|
| PRE2 | n/a | B(2b'00)| B(2b'01)| n/a | B(2b'10)| B(2b'11)|
|------------------------------------------------------------------|
| PRE3 | n/a | n/a | n/a | fixed | n/a | n/a |
------------------------------------------------------------------
(Note - A: GPR5 bit12-13, B: GPR5 bit14-15)
We should bind PRG[x] channel[y] with IPU[x] channel[y+26] statically
instead of dynamically, where x=0or1, y=1or2. Also, the values for A/B
cannot be the same due to a SoC design requirement(even if one of the
PRE1/PRE2 is disabled, the two values cannot be the same). This patch
fixes the PRE/PRG muxing logic.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index 7ab1e199f031..af0dba7bf437 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -248,12 +248,16 @@ #define IMX6Q_GPR5_ENET_TX_CLK_SEL BIT(9) #define IMX6Q_GPR5_PRE_PRG_SEL0_MASK (0x3 << 12) #define IMX6Q_GPR5_PRE_PRG_SEL0_SHIFT 12 +#define IMX6Q_GPR5_PRE_PRG_SEL0_MSB 13 +#define IMX6Q_GPR5_PRE_PRG_SEL0_LSB 12 #define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN1 (0x0 << 12) #define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG0_CHAN2 (0x1 << 12) #define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN1 (0x2 << 12) #define IMX6Q_GPR5_PRE_PRG_SEL0_PRE1_PRG1_CHAN2 (0x3 << 12) #define IMX6Q_GPR5_PRE_PRG_SEL1_MASK (0x3 << 14) #define IMX6Q_GPR5_PRE_PRG_SEL1_SHIFT 14 +#define IMX6Q_GPR5_PRE_PRG_SEL1_MSB 15 +#define IMX6Q_GPR5_PRE_PRG_SEL1_LSB 14 #define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN1 (0x0 << 14) #define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG0_CHAN2 (0x1 << 14) #define IMX6Q_GPR5_PRE_PRG_SEL1_PRE2_PRG1_CHAN1 (0x2 << 14) |