diff options
| author | Sumit Bhattacharya <sumitb@nvidia.com> | 2011-12-15 18:33:06 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-21 12:06:27 +0530 |
| commit | 34e784bd579bc71302562e789925aad71d046d19 (patch) | |
| tree | a24f868b69f97fa26572a31b182c0badeb6f20e5 /sound/pci/hda/hda_intel.c | |
| parent | 7c43ad504033d90c14c13fef72c924a74d6db981 (diff) | |
ALSA: HDA: Disable all references of clocks at end of suspend
HDA driver used to enable clocks during suspend only if there is no
active clock. But this logic causes a race condition when hda codec
power work thread disables the active instance of hda clocks in
middle of suspend. To avoid this race condition always enable
HDA clocks at start of suspend operation and disable all active
references of HDA clocks at end of suspend. Since HDA driver
suspend also suspends all active codecs there is no chance of
getting HDA clock disable call after completion of suspend.
Bug 915436
Change-Id: I4956ba28488d6d445ea2d53fb2592897a2ad83bb
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/70315
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Diffstat (limited to 'sound/pci/hda/hda_intel.c')
| -rw-r--r-- | sound/pci/hda/hda_intel.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 973e46706cdb..79af22905195 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -2421,7 +2421,7 @@ static int azx_suspend(struct azx *chip, pm_message_t state) #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \ defined(CONFIG_SND_HDA_POWER_SAVE) - if (!chip->platform_clk_enable) + if (chip->pdev) azx_platform_enable_clocks(chip); #endif @@ -2447,8 +2447,11 @@ static int azx_suspend(struct azx *chip, pm_message_t state) } #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER - if (chip->pdev) - azx_platform_disable_clocks(chip); + if (chip->pdev) { + /* Disable all clk references */ + while (chip->platform_clk_enable) + azx_platform_disable_clocks(chip); + } #endif return 0; |