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authorEric Nelson <eric.nelson@boundarydevices.com>2015-01-30 14:07:55 -0700
committerMark Brown <broonie@kernel.org>2015-02-03 13:08:41 +0000
commit58cc9c9a175885bbf6bae3acf18233d0a8229a84 (patch)
tree4d65ef4a48db605d32b2dc4013e6236a59b1ba5f /sound/soc/codecs/sgtl5000.c
parent9ee802ec5b1ae0ee468b6acf1bf489347997893b (diff)
ASoC: sgtl5000: add delay before first I2C access
To quote from section 1.3.1 of the data sheet: The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time, communication can start ... 1.0us represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
Diffstat (limited to 'sound/soc/codecs/sgtl5000.c')
-rw-r--r--sound/soc/codecs/sgtl5000.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index 7665016a79ce..aa98be32bb60 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -1462,6 +1462,9 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
if (ret)
return ret;
+ /* Need 8 clocks before I2C accesses */
+ udelay(1);
+
/* read chip information */
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
if (ret)