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authorEric Nelson <eric@nelint.com>2016-06-07 01:14:51 +0200
committerMark Brown <broonie@kernel.org>2016-06-15 14:09:26 +0100
commit08dea16e0960ea5caf7876045b747145cb677096 (patch)
treefe82f1e933151b82d45e1378e7055af6a5d38c0c /sound/soc/codecs/sgtl5000.c
parent3d632cc87204b51a4b32bdaa970fe6b8d879347e (diff)
ASoC: sgtl5000: Disable internal PLL early
To handle the soft reboot case, the internal PLL must be disabled in SGTL5000_CHIP_CLK_CTRL before clearing bits SGTL5000_VCOAMP_POWERUP and SGTL5000_PLL_POWERUP in register SGTL5000_CHIP_ANA_POWER. Signed-off-by: Eric Nelson <eric@nelint.com> Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/sgtl5000.c')
-rw-r--r--sound/soc/codecs/sgtl5000.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index 42f2eb62664e..0916bb46ccf2 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -38,7 +38,6 @@
/* default value of sgtl5000 registers */
static const struct reg_default sgtl5000_reg_defaults[] = {
{ SGTL5000_CHIP_DIG_POWER, 0x0000 },
- { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
{ SGTL5000_CHIP_I2S_CTRL, 0x0010 },
{ SGTL5000_CHIP_SSS_CTRL, 0x0010 },
{ SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
@@ -1279,6 +1278,14 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
sgtl5000->revision = rev;
+ /* reconfigure the clocks in case we're using the PLL */
+ ret = regmap_write(sgtl5000->regmap,
+ SGTL5000_CHIP_CLK_CTRL,
+ SGTL5000_CHIP_CLK_CTRL_DEFAULT);
+ if (ret)
+ dev_err(&client->dev,
+ "Error %d initializing CHIP_CLK_CTRL\n", ret);
+
/* Follow section 2.2.1.1 of AN3663 */
ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
if (sgtl5000->num_supplies <= VDDD) {