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authorPeter Ujfalusi <peter.ujfalusi@nokia.com>2010-03-19 12:27:31 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-03-19 11:14:39 +0000
commit299a151f53ed9272af616076305d3ee762c2eba0 (patch)
tree729bee8e725c7244b9bf3a9cdd35daa3f0c0469e /sound/soc/omap
parent9fc71e8f586efc99472337a8b089a4915877b4b8 (diff)
ASoC: omap-mcbsp: Add support for Left Justified format
Basic support for Left Justified coding for OMAP McBSP. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/omap')
-rw-r--r--sound/soc/omap/omap-mcbsp.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 2952fb046ed6..0199e95a5d63 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -331,7 +331,8 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
wpf = channels = params_channels(params);
- if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
+ if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
+ format == SND_SOC_DAIFMT_LEFT_J)) {
/* Use dual-phase frames */
regs->rcr2 |= RPHASE;
regs->xcr2 |= XPHASE;
@@ -376,6 +377,7 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
/* Set FS period and length in terms of bit clock periods */
switch (format) {
case SND_SOC_DAIFMT_I2S:
+ case SND_SOC_DAIFMT_LEFT_J:
regs->srgr2 |= FPER(framesize - 1);
regs->srgr1 |= FWID((framesize >> 1) - 1);
break;
@@ -427,6 +429,14 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
regs->rcr2 |= RDATDLY(1);
regs->xcr2 |= XDATDLY(1);
break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ /* 0-bit data delay */
+ regs->rcr2 |= RDATDLY(0);
+ regs->xcr2 |= XDATDLY(0);
+ regs->spcr1 |= RJUST(2);
+ /* Invert FS polarity configuration */
+ temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
+ break;
case SND_SOC_DAIFMT_DSP_A:
/* 1-bit data delay */
regs->rcr2 |= RDATDLY(1);