ENGR00179601 Synopsys approved hdmi fifo workaround - rev 3

This patch includes some of the clk enable/disable changes from rev2

Check the version of the HDMI IP to determine whether the fifo
threshold needs to be high.  The i.Mx6dl version of the HDMI doesn't
need the workaround.  All other parts of the workaround are used
for both parts for code simplicity.

----------------------------------------------------------
For i.Mxq, set the Threshold of audio fifo as: FIFO depth - 2 (fixed
and independent of the number of channels actually used).

Use unspecified length ahb bursts (using fixed INCRx will make the
audio dma fail).

Additionally and in order to get it working on all conditions it will
be necessary to run the following sw steps at startup of video and audio
(or when video changes or audio changes):

1-Configure AUD_N1 and AUD_CTS1 registers with final value and let the
  AUD_N2, AUD_N3, AUD_CTS2 and AUD_CTS3 to 0s.
2-Configure start and end addresses of audio DMA registers.
3-Start DMA operation
4-Configure the AUD_CTS2 and AUD_CTS3 with the final value.
5-Configure the AUD_N2 and AUD_N3 with final value.

Signed-off-by: Alan Tull <r80115@freescale.com>

1 files changed, 29 insertions, 6 deletions

diff --git a/sound/soc/imx/imx-hdmi-dma.c b/sound/soc/imx/imx-hdmi-dma.c
index c8e88ff79e3b..1bd36ca1ea57 100644
--- a/sound/soc/imx/imx-hdmi-dma.c
+++ b/sound/soc/imx/imx-hdmi-dma.c
@@ -35,6 +35,11 @@
 #include <mach/mxc_hdmi.h>
 #include "imx-hdmi.h"
 
+#define HDMI_DMA_BURST_UNSPECIFIED_LEGNTH	0
+#define HDMI_DMA_BURST_INCR4			1
+#define HDMI_DMA_BURST_INCR8			2
+#define HDMI_DMA_BURST_INCR16			3
+
 struct imx_hdmi_dma_runtime_data {
 	struct snd_pcm_substream *tx_substream;
 
@@ -315,16 +320,16 @@ static void hdmi_dma_set_incr_type(int incr_type)
 			  HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK);
 
 	switch (incr_type) {
-	case 1:
+	case HDMI_DMA_BURST_UNSPECIFIED_LEGNTH:
 		break;
-	case 4:
+	case HDMI_DMA_BURST_INCR4:
 		value |= HDMI_AHB_DMA_CONF0_BURST_MODE;
 		break;
-	case 8:
+	case HDMI_DMA_BURST_INCR8:
 		value |= HDMI_AHB_DMA_CONF0_BURST_MODE |
 			 HDMI_AHB_DMA_CONF0_INCR8;
 		break;
-	case 16:
+	case HDMI_DMA_BURST_INCR16:
 		value |= HDMI_AHB_DMA_CONF0_BURST_MODE |
 			 HDMI_AHB_DMA_CONF0_INCR16;
 		break;
@@ -359,11 +364,27 @@ static void hdmi_dma_enable_channels(int channels)
 	}
 }
 
+static void hdmi_dma_set_thrsld(void)
+{
+	int rev = hdmi_readb(HDMI_REVISION_ID);
+
+	switch (rev) {
+	case 0x0a:
+		hdmi_writeb(126, HDMI_AHB_DMA_THRSLD);
+		break;
+	default:
+		hdmi_writeb(64, HDMI_AHB_DMA_THRSLD);
+		break;
+	}
+
+	pr_debug("HDMI_AHB_DMA_THRSLD          0x%02x\n", hdmi_readb(HDMI_AHB_DMA_THRSLD));
+}
+
 static void hdmi_dma_configure_dma(int channels)
 {
 	hdmi_dma_enable_hlock(1);
-	hdmi_dma_set_incr_type(4);
-	hdmi_writeb(64, HDMI_AHB_DMA_THRSLD);
+	hdmi_dma_set_incr_type(HDMI_DMA_BURST_UNSPECIFIED_LEGNTH);
+	hdmi_dma_set_thrsld();
 	hdmi_dma_enable_channels(channels);
 }
 
@@ -548,6 +569,7 @@ static int hdmi_dma_trigger(struct snd_pcm_substream *substream, int cmd)
 		hdmi_dma_irq_mask(0);
 		hdmi_dma_priv->tx_active = true;
 		hdmi_dma_start();
+		hdmi_set_dma_mode(1);
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
@@ -555,6 +577,7 @@ static int hdmi_dma_trigger(struct snd_pcm_substream *substream, int cmd)
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		hdmi_dma_priv->tx_active = false;
 		hdmi_dma_stop();
+		hdmi_set_dma_mode(0);
 		hdmi_dma_irq_mask(1);
 		break;