ASoC: Tegra: Spdif: Add Tegra30 spdif driver

Bug 872652

Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>

Change-Id: I2c5006a68d590b9215db056a614566b926287fda
Reviewed-on: http://git-master/r/54954
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Gerrit_Virtual_Submit

Rebase-Id: R89c166fa6563318dcbb0ca6e25f7dcce6db3c134

4 files changed, 1300 insertions, 1 deletions

diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index 18577909f666..f474ee16ac52 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -36,7 +36,16 @@ config SND_SOC_TEGRA20_SPDIF
 	depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
 	default m
 	help
-	  Say Y or M if you want to add support for the SPDIF interface.
+	  Say Y or M if you want to add support for the TEGRA20 SPDIF interface.
+	  You will also need to select the individual machine drivers to support
+	  below.
+
+config SND_SOC_TEGRA30_SPDIF
+	tristate
+	depends on SND_SOC_TEGRA && ARCH_TEGRA_3x_SOC
+	select SND_SOC_TEGRA30_AHUB
+	help
+	  Say Y or M if you want to add support for the TEGRA30 SPDIF interface.
 	  You will also need to select the individual machine drivers to support
 	  below.
 
diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile
index 675515ac22d5..0c4fc1e78cf8 100644
--- a/sound/soc/tegra/Makefile
+++ b/sound/soc/tegra/Makefile
@@ -6,6 +6,7 @@ snd-soc-tegra20-das-objs := tegra20_das.o
 snd-soc-tegra20-i2s-objs := tegra20_i2s.o
 snd-soc-tegra30-ahub-objs := tegra30_ahub.o
 snd-soc-tegra30-i2s-objs := tegra30_i2s.o
+snd-soc-tegra30-spdif-objs := tegra30_spdif.o
 
 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o
 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-utils.o
@@ -14,6 +15,7 @@ obj-$(CONFIG_SND_SOC_TEGRA20_I2S) += snd-soc-tegra20-i2s.o
 obj-$(CONFIG_SND_SOC_TEGRA30_AHUB) += snd-soc-tegra30-ahub.o
 obj-$(CONFIG_SND_SOC_TEGRA30_I2S) += snd-soc-tegra30-i2s.o
 obj-$(CONFIG_SND_SOC_TEGRA20_SPDIF) += snd-soc-tegra20-spdif.o
+obj-$(CONFIG_SND_SOC_TEGRA30_SPDIF) += snd-soc-tegra30-spdif.o
 
 # Tegra machine Support
 snd-soc-tegra-wm8903-objs := tegra_wm8903.o
diff --git a/sound/soc/tegra/tegra30_spdif.c b/sound/soc/tegra/tegra30_spdif.c
new file mode 100644
index 000000000000..a1f97fb4fa73
--- /dev/null
+++ b/sound/soc/tegra/tegra30_spdif.c
@@ -0,0 +1,510 @@
+/*
+ * tegra30_spdif.c - Tegra30 SPDIF driver
+ *
+ * Author: Sumit Bhattacharya <sumitb@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * Copyright (c) 2009-2011, NVIDIA Corporation.
+ * Scott Peterson <speterson@nvidia.com>
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Iliyan Malchev <malchev@google.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <mach/iomap.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include "tegra30_spdif.h"
+
+#define DRV_NAME "tegra30-spdif"
+
+static inline void tegra30_spdif_write(struct tegra30_spdif *spdif,
+						u32 reg, u32 val)
+{
+	__raw_writel(val, spdif->regs + reg);
+}
+
+static inline u32 tegra30_spdif_read(struct tegra30_spdif *spdif, u32 reg)
+{
+	return __raw_readl(spdif->regs + reg);
+}
+
+static void tegra30_spdif_enable_clocks(struct tegra30_spdif *spdif)
+{
+	clk_enable(spdif->clk_spdif_out);
+	clk_enable(spdif->clk_hda2codec);
+	tegra30_ahub_enable_clocks();
+}
+
+static void tegra30_spdif_disable_clocks(struct tegra30_spdif *spdif)
+{
+	tegra30_ahub_disable_clocks();
+	clk_disable(spdif->clk_hda2codec);
+	clk_disable(spdif->clk_spdif_out);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int tegra30_spdif_show(struct seq_file *s, void *unused)
+{
+#define REG(r) { r, #r }
+	static const struct {
+		int offset;
+		const char *name;
+	} regs[] = {
+		REG(TEGRA30_SPDIF_CTRL),
+		REG(TEGRA30_SPDIF_STROBE_CTRL),
+		REG(TEGRA30_SPDIF_CIF_TXD_CTRL),
+		REG(TEGRA30_SPDIF_CIF_RXD_CTRL),
+		REG(TEGRA30_SPDIF_CIF_TXU_CTRL),
+		REG(TEGRA30_SPDIF_CIF_RXU_CTRL),
+		REG(TEGRA30_SPDIF_CH_STA_RX_A),
+		REG(TEGRA30_SPDIF_CH_STA_RX_B),
+		REG(TEGRA30_SPDIF_CH_STA_RX_C),
+		REG(TEGRA30_SPDIF_CH_STA_RX_D),
+		REG(TEGRA30_SPDIF_CH_STA_RX_E),
+		REG(TEGRA30_SPDIF_CH_STA_RX_F),
+		REG(TEGRA30_SPDIF_CH_STA_TX_A),
+		REG(TEGRA30_SPDIF_CH_STA_TX_B),
+		REG(TEGRA30_SPDIF_CH_STA_TX_C),
+		REG(TEGRA30_SPDIF_CH_STA_TX_D),
+		REG(TEGRA30_SPDIF_CH_STA_TX_E),
+		REG(TEGRA30_SPDIF_CH_STA_TX_F),
+		REG(TEGRA30_SPDIF_FLOWCTL_CTRL),
+		REG(TEGRA30_SPDIF_TX_STEP),
+		REG(TEGRA30_SPDIF_FLOW_STATUS),
+		REG(TEGRA30_SPDIF_FLOW_TOTAL),
+		REG(TEGRA30_SPDIF_FLOW_OVER),
+		REG(TEGRA30_SPDIF_FLOW_UNDER),
+		REG(TEGRA30_SPDIF_LCOEF_1_4_0),
+		REG(TEGRA30_SPDIF_LCOEF_1_4_1),
+		REG(TEGRA30_SPDIF_LCOEF_1_4_2),
+		REG(TEGRA30_SPDIF_LCOEF_1_4_3),
+		REG(TEGRA30_SPDIF_LCOEF_1_4_4),
+		REG(TEGRA30_SPDIF_LCOEF_1_4_5),
+		REG(TEGRA30_SPDIF_LCOEF_2_4_0),
+		REG(TEGRA30_SPDIF_LCOEF_2_4_1),
+		REG(TEGRA30_SPDIF_LCOEF_2_4_2),
+	};
+#undef REG
+
+	struct tegra30_spdif *spdif = s->private;
+	int i;
+
+	tegra30_spdif_enable_clocks(spdif);
+
+	for (i = 0; i < ARRAY_SIZE(regs); i++) {
+		u32 val = tegra30_spdif_read(spdif, regs[i].offset);
+		seq_printf(s, "%s = %08x\n", regs[i].name, val);
+	}
+
+	tegra30_spdif_disable_clocks(spdif);
+
+	return 0;
+}
+
+static int tegra30_spdif_debug_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, tegra30_spdif_show, inode->i_private);
+}
+
+static const struct file_operations tegra30_spdif_debug_fops = {
+	.open    = tegra30_spdif_debug_open,
+	.read    = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+static void tegra30_spdif_debug_add(struct tegra30_spdif *spdif)
+{
+	char name[] = DRV_NAME;
+
+	spdif->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
+					spdif, &tegra30_spdif_debug_fops);
+}
+
+static void tegra30_spdif_debug_remove(struct tegra30_spdif *spdif)
+{
+	if (spdif->debug)
+		debugfs_remove(spdif->debug);
+}
+#else
+static inline void tegra30_spdif_debug_add(struct tegra30_spdif *spdif)
+{
+}
+
+static inline void tegra30_spdif_debug_remove(struct tegra30_spdif *spdif)
+{
+}
+#endif
+
+int tegra30_spdif_startup(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+	int ret = 0;
+
+	tegra30_spdif_enable_clocks(spdif);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		ret = tegra30_ahub_allocate_tx_fifo(&spdif->txcif,
+					&spdif->playback_dma_data.addr,
+					&spdif->playback_dma_data.req_sel);
+		spdif->playback_dma_data.wrap = 4;
+		spdif->playback_dma_data.width = 32;
+		tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_SPDIF_RX0,
+					       spdif->txcif);
+	}
+
+	tegra30_spdif_disable_clocks(spdif);
+
+	return ret;
+}
+
+void tegra30_spdif_shutdown(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+
+	tegra30_spdif_enable_clocks(spdif);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_SPDIF_RX0);
+		tegra30_ahub_free_tx_fifo(spdif->txcif);
+	}
+
+	tegra30_spdif_disable_clocks(spdif);
+}
+
+static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct device *dev = substream->pcm->card->dev;
+	struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+	int ret, srate, spdifclock;
+
+	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
+		dev_err(dev, "spdif capture is not supported\n");
+		return -EINVAL;
+	}
+
+	spdif->reg_ctrl &= ~TEGRA30_SPDIF_CTRL_BIT_MODE_MASK;
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_PACK_ENABLE;
+		spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	srate = params_rate(params);
+	spdif->reg_ch_sta_a &= ~TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK;
+	spdif->reg_ch_sta_b &= ~TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK;
+	switch (srate) {
+	case 32000:
+		spdifclock = 4096000;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000;
+		break;
+	case 44100:
+		spdifclock = 5644800;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100;
+		break;
+	case 48000:
+		spdifclock = 6144000;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000;
+		break;
+	case 88200:
+		spdifclock = 11289600;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200;
+		break;
+	case 96000:
+		spdifclock = 12288000;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000;
+		break;
+	case 176400:
+		spdifclock = 22579200;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400;
+		break;
+	case 192000:
+		spdifclock = 24576000;
+		spdif->reg_ch_sta_a |=
+			TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000;
+		spdif->reg_ch_sta_b |=
+			TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
+	if (ret) {
+		dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
+		return ret;
+	}
+
+	tegra30_spdif_enable_clocks(spdif);
+
+	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_A,
+						spdif->reg_ch_sta_a);
+	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_B,
+						spdif->reg_ch_sta_b);
+
+	tegra30_spdif_disable_clocks(spdif);
+
+	return 0;
+}
+
+static void tegra30_spdif_start_playback(struct tegra30_spdif *spdif)
+{
+	tegra30_ahub_enable_tx_fifo(spdif->txcif);
+	spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_TX_EN_ENABLE |
+				TEGRA30_SPDIF_CTRL_TC_EN_ENABLE;
+	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CTRL, spdif->reg_ctrl);
+}
+
+static void tegra30_spdif_stop_playback(struct tegra30_spdif *spdif)
+{
+	tegra30_ahub_disable_tx_fifo(spdif->txcif);
+	spdif->reg_ctrl &= ~(TEGRA30_SPDIF_CTRL_TX_EN_ENABLE |
+				TEGRA30_SPDIF_CTRL_TC_EN_ENABLE);
+	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CTRL, spdif->reg_ctrl);
+}
+
+static int tegra30_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
+				struct snd_soc_dai *dai)
+{
+	struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+	case SNDRV_PCM_TRIGGER_RESUME:
+		tegra30_spdif_enable_clocks(spdif);
+		tegra30_spdif_start_playback(spdif);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+		tegra30_spdif_stop_playback(spdif);
+		tegra30_spdif_disable_clocks(spdif);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tegra30_spdif_probe(struct snd_soc_dai *dai)
+{
+	struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
+
+	dai->playback_dma_data = &spdif->playback_dma_data;
+	dai->capture_dma_data = NULL;
+
+	return 0;
+}
+
+static struct snd_soc_dai_ops tegra30_spdif_dai_ops = {
+	.startup	= tegra30_spdif_startup,
+	.shutdown	= tegra30_spdif_shutdown,
+	.hw_params	= tegra30_spdif_hw_params,
+	.trigger	= tegra30_spdif_trigger,
+};
+
+struct snd_soc_dai_driver tegra30_spdif_dai = {
+	.name = DRV_NAME,
+	.probe = tegra30_spdif_probe,
+	.playback = {
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
+				SNDRV_PCM_RATE_48000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	},
+	.ops = &tegra30_spdif_dai_ops,
+};
+
+static __devinit int tegra30_spdif_platform_probe(struct platform_device *pdev)
+{
+	struct tegra30_spdif *spdif;
+	struct resource *mem, *memregion;
+	int ret;
+	u32 reg_val;
+
+	spdif = kzalloc(sizeof(struct tegra30_spdif), GFP_KERNEL);
+	if (!spdif) {
+		dev_err(&pdev->dev, "Can't allocate tegra30_spdif\n");
+		ret = -ENOMEM;
+		goto exit;
+	}
+	dev_set_drvdata(&pdev->dev, spdif);
+
+	spdif->clk_spdif_out = clk_get(&pdev->dev, "spdif_out");
+	if (IS_ERR(spdif->clk_spdif_out)) {
+		dev_err(&pdev->dev, "Can't retrieve spdif clock\n");
+		ret = PTR_ERR(spdif->clk_spdif_out);
+		goto err_free;
+	}
+
+	spdif->clk_hda2codec = clk_get_sys("hda2codec_2x", NULL);
+	if (IS_ERR(spdif->clk_hda2codec)) {
+		dev_err(&pdev->dev, "Can't retrieve hda2codec clock\n");
+		ret = PTR_ERR(spdif->clk_hda2codec);
+		goto err_clk_put_spdif;
+	}
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "No memory resource\n");
+		ret = -ENODEV;
+		goto err_clk_put_hda;
+	}
+
+	memregion = request_mem_region(mem->start, resource_size(mem),
+					DRV_NAME);
+	if (!memregion) {
+		dev_err(&pdev->dev, "Memory region already claimed\n");
+		ret = -EBUSY;
+		goto err_clk_put_hda;
+	}
+
+	spdif->regs = ioremap(mem->start, resource_size(mem));
+	if (!spdif->regs) {
+		dev_err(&pdev->dev, "ioremap failed\n");
+		ret = -ENOMEM;
+		goto err_release;
+	}
+
+	tegra30_spdif_enable_clocks(spdif);
+
+	reg_val = TEGRA30_SPDIF_CIF_TXD_CTRL_DIRECTION_RXCIF |
+		TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT16 |
+		TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT16 |
+		TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH2 |
+		TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH2 |
+		(3 << TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT);
+
+	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CIF_TXD_CTRL, reg_val);
+
+	tegra30_spdif_disable_clocks(spdif);
+
+	ret = snd_soc_register_dai(&pdev->dev, &tegra30_spdif_dai);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
+		ret = -ENOMEM;
+		goto err_unmap;
+	}
+
+	tegra30_spdif_debug_add(spdif);
+
+	return 0;
+
+err_unmap:
+	iounmap(spdif->regs);
+err_release:
+	release_mem_region(mem->start, resource_size(mem));
+err_clk_put_hda:
+	clk_put(spdif->clk_hda2codec);
+err_clk_put_spdif:
+	clk_put(spdif->clk_spdif_out);
+err_free:
+	kfree(spdif);
+exit:
+	return ret;
+}
+
+static int __devexit tegra30_spdif_platform_remove(struct platform_device *pdev)
+{
+	struct tegra30_spdif *spdif = dev_get_drvdata(&pdev->dev);
+	struct resource *res;
+
+	snd_soc_unregister_dai(&pdev->dev);
+
+	tegra30_spdif_debug_remove(spdif);
+
+	iounmap(spdif->regs);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, resource_size(res));
+
+	clk_put(spdif->clk_spdif_out);
+	clk_put(spdif->clk_hda2codec);
+
+	kfree(spdif);
+
+	return 0;
+}
+
+static struct platform_driver tegra30_spdif_driver = {
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+	},
+	.probe = tegra30_spdif_platform_probe,
+	.remove = __devexit_p(tegra30_spdif_platform_remove),
+};
+
+static int __init snd_tegra30_spdif_init(void)
+{
+	return platform_driver_register(&tegra30_spdif_driver);
+}
+module_init(snd_tegra30_spdif_init);
+
+static void __exit snd_tegra30_spdif_exit(void)
+{
+	platform_driver_unregister(&tegra30_spdif_driver);
+}
+module_exit(snd_tegra30_spdif_exit);
+
+MODULE_AUTHOR("Sumit Bhattacharya <sumitb@nvidia.com>");
+MODULE_DESCRIPTION("Tegra30 SPDIF ASoC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/tegra/tegra30_spdif.h b/sound/soc/tegra/tegra30_spdif.h
new file mode 100644
index 000000000000..ce449c5edad4
--- /dev/null
+++ b/sound/soc/tegra/tegra30_spdif.h
@@ -0,0 +1,778 @@
+/*
+ * tegra30_spdif.h - Definitions for Tegra30 SPDIF driver
+ *
+ * Author: Sumit Bhattacharya <sumitb@nvidia.com>
+ * Copyright (C) 2011 - NVIDIA, Inc.
+ *
+ * Based on code copyright/by:
+ *
+ * Copyright (c) 2009-2011, NVIDIA Corporation.
+ * Scott Peterson <speterson@nvidia.com>
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Iliyan Malchev <malchev@google.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __TEGRA30_SPDIF_H__
+#define __TEGRA30_SPDIF_H__
+
+#include "tegra_pcm.h"
+#include "tegra30_ahub.h"
+
+/* Register offsets from TEGRA_SPDIF_BASE */
+
+#define TEGRA30_SPDIF_CTRL			0x0
+#define TEGRA30_SPDIF_STROBE_CTRL		0x4
+#define TEGRA30_SPDIF_CIF_TXD_CTRL		0x08
+#define TEGRA30_SPDIF_CIF_RXD_CTRL		0x0C
+#define TEGRA30_SPDIF_CIF_TXU_CTRL		0x10
+#define TEGRA30_SPDIF_CIF_RXU_CTRL		0x14
+#define TEGRA30_SPDIF_CH_STA_RX_A		0x18
+#define TEGRA30_SPDIF_CH_STA_RX_B		0x1C
+#define TEGRA30_SPDIF_CH_STA_RX_C		0x20
+#define TEGRA30_SPDIF_CH_STA_RX_D		0x24
+#define TEGRA30_SPDIF_CH_STA_RX_E		0x28
+#define TEGRA30_SPDIF_CH_STA_RX_F		0x2C
+#define TEGRA30_SPDIF_CH_STA_TX_A		0x30
+#define TEGRA30_SPDIF_CH_STA_TX_B		0x34
+#define TEGRA30_SPDIF_CH_STA_TX_C		0x38
+#define TEGRA30_SPDIF_CH_STA_TX_D		0x3C
+#define TEGRA30_SPDIF_CH_STA_TX_E		0x40
+#define TEGRA30_SPDIF_CH_STA_TX_F		0x44
+#define TEGRA30_SPDIF_FLOWCTL_CTRL		0x70
+#define TEGRA30_SPDIF_TX_STEP			0x74
+#define TEGRA30_SPDIF_FLOW_STATUS		0x78
+#define TEGRA30_SPDIF_FLOW_TOTAL		0x7c
+#define TEGRA30_SPDIF_FLOW_OVER			0x80
+#define TEGRA30_SPDIF_FLOW_UNDER		0x84
+#define TEGRA30_SPDIF_LCOEF_1_4_0		0x88
+#define TEGRA30_SPDIF_LCOEF_1_4_1		0x8c
+#define TEGRA30_SPDIF_LCOEF_1_4_2		0x90
+#define TEGRA30_SPDIF_LCOEF_1_4_3		0x94
+#define TEGRA30_SPDIF_LCOEF_1_4_4		0x98
+#define TEGRA30_SPDIF_LCOEF_1_4_5		0x9c
+#define TEGRA30_SPDIF_LCOEF_2_4_0		0xa0
+#define TEGRA30_SPDIF_LCOEF_2_4_1		0xa4
+#define TEGRA30_SPDIF_LCOEF_2_4_2		0xa8
+
+/* Fields in TEGRA30_SPDIF_CTRL */
+#define TEGRA30_SPDIF_CTRL_FLOWCTL_EN_ENABLE	(1<<31)
+#define TEGRA30_SPDIF_CTRL_CAP_LC_LEFT_CH	(1<<30)
+#define TEGRA30_SPDIF_CTRL_RX_EN_ENABLE		(1<<29)
+#define TEGRA30_SPDIF_CTRL_TX_EN_ENABLE		(1<<28)
+#define TEGRA30_SPDIF_CTRL_TC_EN_ENABLE		(1<<27)
+#define TEGRA30_SPDIF_CTRL_TU_EN_ENABLE		(1<<26)
+#define TEGRA30_SPDIF_CTRL_IE_P_RSVD_ENABLE	(1<<23)
+#define TEGRA30_SPDIF_CTRL_IE_B_RSVD_ENABLE	(1<<22)
+#define TEGRA30_SPDIF_CTRL_IE_C_RSVD_ENABLE	(1<<21)
+#define TEGRA30_SPDIF_CTRL_IE_U_RSVD_ENABLE	(1<<20)
+#define TEGRA30_SPDIF_CTRL_LBK_EN_ENABLE	(1<<15)
+#define TEGRA30_SPDIF_CTRL_PACK_ENABLE		(1<<14)
+
+#define TEGRA30_SPDIF_BIT_MODE16		0
+#define TEGRA30_SPDIF_BIT_MODE20		1
+#define TEGRA30_SPDIF_BIT_MODE24		2
+#define TEGRA30_SPDIF_BIT_MODERAW		3
+
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT	12
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_MASK	(3                         << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT	(TEGRA30_SPDIF_BIT_MODE16  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_20BIT	(TEGRA30_SPDIF_BIT_MODE20  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_24BIT	(TEGRA30_SPDIF_BIT_MODE24  << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+#define TEGRA30_SPDIF_CTRL_BIT_MODE_RAW		(TEGRA30_SPDIF_BIT_MODERAW << TEGRA30_SPDIF_CTRL_BIT_MODE_SHIFT)
+
+#define TEGRA30_SPDIF_CTRL_CG_EN_ENABLE		(1<<11)
+
+#define TEGRA30_SPDIF_CTRL_OBS_SEL_SHIFT	8
+#define TEGRA30_SPDIF_CTRL_OBS_SEL_NASK		(0x7 << TEGRA30_SPDIF_CTRL_OBS_SEL_SHIFT)
+
+#define TEGRA30_SPDIF_CTRL_SOFT_RESET_ENABLE	(1<<7)
+
+/* Fields in TEGRA30_SPDIF_STROBE_CTRL */
+#define TEGRA30_SPDIF_STROBE_CTRL_PERIOD_SHIFT		16
+#define TEGRA30_SPDIF_STROBE_CTRL_PERIOD_MASK		(0xff << TEGRA30_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_STROBE		(1<<15)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT	8
+#define TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_MASK	(0x1f << TEGRA30_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
+
+#define TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT	0
+#define TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK	(0x3f << TEGRA30_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CIF_TXD_CTRL */
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_MONO_CONV_COPY	(1<<0)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_TRUNCATE_CHOP	(1<<1)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_DIRECTION_RXCIF	(1<<2)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_REPLICATE_ENABLE	(1<<3)
+
+#define TEGRA30_SPDIF_CIF_STEREO_CH0			0
+#define TEGRA30_SPDIF_CIF_STEREO_CH1			1
+#define TEGRA30_SPDIF_CIF_STEREO_AVG			2
+#define TEGRA30_SPDIF_CIF_STEREO_RSVD			3
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT	4
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_MASK	\
+		(0x3                           << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_CH0	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_CH1	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_AVG	\
+		(TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_RSVD	\
+		(TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_TXD_CTRL_STEREO_CONV_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_EXPAND_ZERO			0
+#define TEGRA30_SPDIF_CIF_EXPAND_ONE			1
+#define TEGRA30_SPDIF_CIF_EXPAND_LFSR			2
+#define TEGRA30_SPDIF_CIF_EXPAND_RSVD 			3
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT		6
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_MASK		\
+		(0x3                           << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_ZERO		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_ONE		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_LFSR		\
+		(TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_RSVD		\
+		(TEGRA30_SPDIF_CIF_EXPAND_RSVD << TEGRA30_SPDIF_CIF_TXD_CTRL_EXPAND_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_BIT4				0
+#define TEGRA30_SPDIF_CIF_BIT8				1
+#define TEGRA30_SPDIF_CIF_BIT12				2
+#define TEGRA30_SPDIF_CIF_BIT16				3
+#define TEGRA30_SPDIF_CIF_BIT20				4
+#define TEGRA30_SPDIF_CIF_BIT24				5
+#define TEGRA30_SPDIF_CIF_BIT28				6
+#define TEGRA30_SPDIF_CIF_BIT32				7
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT	8
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT	12
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_BITS_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_CH1				0
+#define TEGRA30_SPDIF_CIF_CH2				1
+#define TEGRA30_SPDIF_CIF_CH3				2
+#define TEGRA30_SPDIF_CIF_CH4				3
+#define TEGRA30_SPDIF_CIF_CH5				4
+#define TEGRA30_SPDIF_CIF_CH6				5
+#define TEGRA30_SPDIF_CIF_CH7				6
+#define TEGRA30_SPDIF_CIF_CH8				7
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT	16
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_MASK		(0x7 << TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_TEGRA30_SPDIF_CIF_RXD_CTRL */
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_MONO_CONV_COPY	(1<<0)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_TRUNCATE_CHOP	(1<<1)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_DIRECTION_RXCIF	(1<<2)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_REPLICATE_ENABLE	(1<<3)
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT	4
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_MASK	\
+		(0x3                           << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_CH0	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_CH1	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_AVG	\
+		(TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_RSVD	\
+		(TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_RXD_CTRL_STEREO_CONV_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT		6
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_MASK		\
+		(0x3                           << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_ZERO		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_ONE		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_LFSR		\
+		(TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_EXPAND_RSVD		\
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT	8
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_BITS_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT	12
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT 16
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT	24
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_MASK		(0x7  << TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_TEGRA30_SPDIF_CIF_TXU_CTRL */
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_MONO_CONV_COPY	(1<<0)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_TRUNCATE_CHOP	(1<<1)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_DIRECTION_RXCIF	(1<<2)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_REPLICATE_ENABLE	(1<<3)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_SHIFT	4
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_MASK	\
+		(0x3                                    << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_CH0	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_CH1	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_AVG	\
+		(TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_STEREO_CONV_RSVD	\
+		(TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_TXU_CTRL_0_STEREO_CONV_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT		6
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_MASK		\
+		(0x3                           << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_ZERO		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_ONE		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_LFSR		\
+		(TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_RSVD		\
+		(TEGRA30_SPDIF_CIF_EXPAND_RSVD << TEGRA30_SPDIF_CIF_TXU_CTRL_EXPAND_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT	8
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT	12
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT 16
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_MASK		(0x7 << TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_TEGRA30_SPDIF_CIF_RXU_CTRL */
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_MONO_CONV_COPY	(1<<0)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_TRUNCATE_CHOP	(1<<1)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_DIRECTION_RXCIF	(1<<2)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_REPLICATE_ENABLE	(1<<3)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_SHIFT	4
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_MASK	\
+		(0x3                           << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_CH0	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH0  << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_CH1	\
+		(TEGRA30_SPDIF_CIF_STEREO_CH1  << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_AVG	\
+		(TEGRA30_SPDIF_CIF_STEREO_AVG  << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_STEREO_CONV_RSVD	\
+		(TEGRA30_SPDIF_CIF_STEREO_RSVD << TEGRA30_SPDIF_CIF_RXU_CTRL_0_STEREO_CONV_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT		6
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_MASK		\
+		(0x3                           << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_ZERO		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ZERO << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_ONE		\
+		(TEGRA30_SPDIF_CIF_EXPAND_ONE  << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_LFSR		\
+		(TEGRA30_SPDIF_CIF_EXPAND_LFSR << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_RSVD		\
+		(TEGRA30_SPDIF_CIF_EXPAND_RSVD << TEGRA30_SPDIF_CIF_RXU_CTRL_EXPAND_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT	8
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT	12
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_MASK	\
+		(0x7                     << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT4		\
+		(TEGRA30_SPDIF_CIF_BIT4  << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT8		\
+		(TEGRA30_SPDIF_CIF_BIT8  << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT12		\
+		(TEGRA30_SPDIF_CIF_BIT12 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT16		\
+		(TEGRA30_SPDIF_CIF_BIT16 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT20		\
+		(TEGRA30_SPDIF_CIF_BIT20 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT24		\
+		(TEGRA30_SPDIF_CIF_BIT24 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT28		\
+		(TEGRA30_SPDIF_CIF_BIT28 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BIT32		\
+		(TEGRA30_SPDIF_CIF_BIT32 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_BITS_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT 16
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_MASK	\
+		(0x7                   << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH1		\
+		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH2		\
+		(TEGRA30_SPDIF_CIF_CH2 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH3		\
+		(TEGRA30_SPDIF_CIF_CH3 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH4		\
+		(TEGRA30_SPDIF_CIF_CH4 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH5		\
+		(TEGRA30_SPDIF_CIF_CH5 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH6		\
+		(TEGRA30_SPDIF_CIF_CH6 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH7		\
+		(TEGRA30_SPDIF_CIF_CH7 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH8		\
+		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_MASK		(0x7 << TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_A */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_B */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_C */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_D */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_E */
+/* Fields in TEGRA30_SPDIF_CH_STA_RX_F */
+
+/*
+ * The 6-word receive channel data page buffer holds a block (192 frames) of
+ * channel status information. The order of receive is from LSB to MSB
+ * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
+ */
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_A */
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_22050			0x4
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_24000			0x6
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_32000			0x3
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_44100			0x0
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_48000			0x2
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_88200			0x8
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_96000			0xA
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_176400			0xC
+#define TEGRA30_SPDIF_CH_STA_TX_A_SF_192000			0xE
+
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT		24
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK		\
+		(0xF                                 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_22050	\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_22050  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_24000		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_24000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_32000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_44100  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_48000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_88200  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_96000  << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_176400 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000		\
+		(TEGRA30_SPDIF_CH_STA_TX_A_SF_192000 << TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_B */
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_8000			0x6
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_11025			0xA
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_12000			0x2
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_16000			0x8
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_22050			0xB
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_24000			0x9
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_32000			0xC
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_44100			0xF
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_48000			0xD
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_88200			0x7
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_96000			0x5
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_176400			0x3
+#define TEGRA30_SPDIF_CH_STA_TX_B_SF_192000			0x1
+
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT		4
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK		\
+		(0xF                                 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_8000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_8000   << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_11025		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_11025  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_12000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_12000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_16000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_16000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_22050		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_22025  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_24000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_24000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_32000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_44100  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_48000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_88200  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_96000  << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_176400 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+#define TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000		\
+		(TEGRA30_SPDIF_CH_STA_TX_B_SF_192000 << TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_C */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_D */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_E */
+/* Fields in TEGRA30_SPDIF_CH_STA_TX_F */
+
+/* Fields in TEGRA30_SPDIF_FLOWCTL_CTRL */
+#define TEGRA30_SPDIF_FLOWCTL_CTRL_FILTER_QUAD		(1<<31)
+
+/* Fields in TEGRA30_SPDIF_TX_STEP */
+#define TEGRA30_SPDIF_TX_STEP_STEP_SIZE_SHIFT		0
+#define TEGRA30_SPDIF_TX_STEP_STEP_SIZE_MASK		(0xffff << TEGRA30_SPDIF_TX_STEP_STEP_SIZE_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_FLOW_STATUS */
+#define TEGRA30_SPDIF_FLOW_STATUS_COUNTER_EN_ENABLE	(1<<1)
+#define TEGRA30_SPDIF_FLOW_STATUS_MONITOR_CLR_CLEAR	(1<<2)
+#define TEGRA30_SPDIF_FLOW_STATUS_COUNTER_CLR_CLEAR	(1<<3)
+#define TEGRA30_SPDIF_FLOW_STATUS_MONITOR_INT_EN_ENABLE	(1<<4)
+#define TEGRA30_SPDIF_FLOW_STATUS_FLOW_OVERFLOW_OVER	(1<<30)
+#define TEGRA30_SPDIF_FLOW_STATUS_FLOW_UNDERFLOW_UNDER	(1<<31)
+
+/* Fields in TEGRA30_SPDIF_FLOW_TOTAL */
+/* Fields in TEGRA30_SPDIF_FLOW_OVER */
+/* Fields in TEGRA30_SPDIF_FLOW_UNDER */
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_0 */
+#define TEGRA30_SPDIF_LCOEF_1_4_0_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_1_4_0_COEF_MASK		(0xffff << TEGRA30_TEGRA30_SPDIF_LCOEF_1_4_0_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_1 */
+#define TEGRA30_SPDIF_LCOEF_1_4_1_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_1_4_1_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_1_4_1_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_2 */
+#define TEGRA30_SPDIF_LCOEF_1_4_2_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_1_4_2_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_1_4_2_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_3 */
+#define TEGRA30_SPDIF_LCOEF_1_4_3_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_1_4_3_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_1_4_3_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_4 */
+#define TEGRA30_SPDIF_LCOEF_1_4_4_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_1_4_4_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_1_4_4_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_1_4_5 */
+#define TEGRA30_SPDIF_LCOEF_1_4_5_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_1_4_5_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_1_4_5_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_0 */
+#define TEGRA30_SPDIF_LCOEF_2_4_0_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_2_4_0_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_2_4_0_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_1 */
+#define TEGRA30_SPDIF_LCOEF_2_4_1_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_2_4_1_COEF_MASK		(0xffff << TEGRA30_SPDIF_LCOEF_2_4_1_COEF_SHIFT)
+
+/* Fields in TEGRA30_SPDIF_LCOEF_2_4_2 */
+#define TEGRA30_SPDIF_LCOEF_2_4_2_COEF_SHIFT		0
+#define TEGRA30_SPDIF_LCOEF_2_4_2_COEF_MASK		(0xffff << SPDIF_LCOEF_2_4_2_COEF_SHIFT)
+
+struct tegra30_spdif {
+	struct clk *clk_spdif_out;
+	struct clk *clk_hda2codec;
+	enum tegra30_ahub_txcif txcif;
+	struct tegra_pcm_dma_params playback_dma_data;
+	void __iomem *regs;
+	struct dentry *debug;
+	u32 reg_ctrl;
+	u32 reg_ch_sta_a;
+	u32 reg_ch_sta_b;
+};
+
+#endif