diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-12-16 13:06:13 +0800 |
|---|---|---|
| committer | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-12-17 17:30:26 +0800 |
| commit | 9bfe1d33b984b44af011c644f995c3b406b2f3e1 (patch) | |
| tree | 4d4b98e3dbd794b160a09fe04c8ac27f643e4bfe /sound | |
| parent | 991a1f269ce4e4d0daa2cf5615169891acca0607 (diff) | |
MLK-10003-1: ASoC: fsl_sai: The record sound is faster or slower in master mode
The default setting of sai is RX sync with TX, TX output the I2S clock. So
When recording, we should set TCR2's divider, not RCR2's divider.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/fsl/fsl_sai.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 33ce076f9d07..b58dc4776fae 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -349,10 +349,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) return -EINVAL; } - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), FSL_SAI_CR2_MSEL_MASK, - FSL_SAI_CR2_MSEL(sai->mclk_id)); - regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), - FSL_SAI_CR2_DIV_MASK, savediv - 1); + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) { + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_MSEL_MASK, + FSL_SAI_CR2_MSEL(sai->mclk_id)); + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, + FSL_SAI_CR2_DIV_MASK, savediv - 1); + } else { + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_MSEL_MASK, + FSL_SAI_CR2_MSEL(sai->mclk_id)); + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, + FSL_SAI_CR2_DIV_MASK, savediv - 1); + } dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", sai->mclk_id, savediv, savesub); |