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authorRoland Dreier <rolandd@cisco.com>2009-09-05 20:24:49 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2009-09-24 08:43:59 -0700
commit0dadca5c16ebc1754b14cd6db3710ddab3c68f7d (patch)
tree30900dd393ab840c61e770631602977e5fdbb8e2 /tools
parentdb15c341d2cc6d162e3b7aa4c72bd49cf03dd30f (diff)
mlx4_core: Allocate and map sufficient ICM memory for EQ context
commit fa0681d2129732027355d6b7083dd8932b9b799d upstream. The current implementation allocates a single host page for EQ context memory, which was OK when we only allocated a few EQs. However, since we now allocate an EQ for each CPU core, this patch removes the hard-coded limit (which we exceed with 4 KB pages and 128 byte EQ context entries with 32 CPUs) and uses the same ICM table code as all other context tables, which ends up simplifying the code quite a bit while fixing the problem. This problem was actually hit in practice on a dual-socket Nehalem box with 16 real hardware threads and sufficiently odd ACPI tables that it shows on boot SMP: Allowing 32 CPUs, 16 hotplug CPUs so num_possible_cpus() ends up 32, and mlx4 ends up creating 33 MSI-X interrupts and 33 EQs. This mlx4 bug means that mlx4 can't even initialize at all on this quite mainstream system. Reported-by: Eli Cohen <eli@mellanox.co.il> Tested-by: Christoph Lameter <cl@linux-foundation.org> Signed-off-by: Roland Dreier <rolandd@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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