diff options
-rw-r--r-- | arch/arm/mach-mvf/board-twr_vf600.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-mvf/clock.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-mvf/irq.c | 8 | ||||
-rwxr-xr-x | arch/arm/plat-mxc/include/mach/common.h | 1 | ||||
-rw-r--r-- | arch/arm/plat-mxc/mvf_time.c | 25 |
5 files changed, 31 insertions, 13 deletions
diff --git a/arch/arm/mach-mvf/board-twr_vf600.c b/arch/arm/mach-mvf/board-twr_vf600.c index f5f67f79a924..066fa6b12e54 100644 --- a/arch/arm/mach-mvf/board-twr_vf600.c +++ b/arch/arm/mach-mvf/board-twr_vf600.c @@ -218,7 +218,7 @@ static void __init twr_vf600_init(void) } //extern void __iomem *twd_base; -static void __init mvf_timer_init(void) +static void __init vf600_timer_init(void) { struct clk *uart_clk; #if 0 //FIXME @@ -234,7 +234,7 @@ static void __init mvf_timer_init(void) } static struct sys_timer mxc_timer = { - .init = mvf_timer_init, + .init = vf600_timer_init, }; #if 0 //FIXME diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c index c9c26ea55f1c..945b79d79fc3 100644 --- a/arch/arm/mach-mvf/clock.c +++ b/arch/arm/mach-mvf/clock.c @@ -3481,7 +3481,7 @@ static void clk_tree_init(void) int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih, unsigned long oscl, unsigned long osch) { - //__iomem void *base; + __iomem void *base; int i; external_low_reference = ckil; @@ -3501,6 +3501,7 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih, /* keep correct count. */ clk_enable(&cpu_clk); +#if 0 /* Disable un-necessary PFDs & PLLs */ if (pll2_pfd1.usecount == 0) pll2_pfd1.disable(&pll2_pfd1); @@ -3510,6 +3511,7 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih, pll2_pfd3.disable(&pll2_pfd3); if (pll2_pfd4.usecount == 0) pll2_pfd4.disable(&pll2_pfd4); +#endif #if !defined(CONFIG_FEC_1588) pll3_pfd1.disable(&pll3_pfd1); @@ -3710,7 +3712,7 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih, 3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR11); -#if 0 //FIXME +#if 1 //FIXME base = ioremap(MVF_PIT_BASE_ADDR, SZ_4K); mvf_timer_init(&pit_clk, base, MXC_INT_PIT); #endif diff --git a/arch/arm/mach-mvf/irq.c b/arch/arm/mach-mvf/irq.c index a9cdb4f916bb..45653fe10cde 100644 --- a/arch/arm/mach-mvf/irq.c +++ b/arch/arm/mach-mvf/irq.c @@ -52,9 +52,15 @@ static int mvf_gic_irq_set_wake(struct irq_data *d, unsigned int enable) void mvf_init_irq(void) { - void __iomem *gpc_base = MVF_IO_ADDRESS(MVF_GPC_BASE_ADDR); + // void __iomem *gpc_base = MVF_IO_ADDRESS(MVF_GPC_BASE_ADDR); struct irq_desc *desc; unsigned int i; + void __iomem *mscm_base = MVF_IO_ADDRESS(MVF_MSCM_BASE_ADDR); + + /* Interrupt Ruter Shared Peripheral */ + for ( i = 0;i < 112;i++) { + __raw_writew(0x01,mscm_base + 0x880 + (i<<1)); + } /* start offset if private timer irq id, which is 29. * ID table: diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 99200d0f241e..29bdae279d13 100755 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -62,6 +62,7 @@ extern void mxc91231_init_irq(void); extern void mvf_init_irq(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); +extern void mvf_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); extern int mx25_clocks_init(void); diff --git a/arch/arm/plat-mxc/mvf_time.c b/arch/arm/plat-mxc/mvf_time.c index ebebc042ea5a..597f96cd6f02 100644 --- a/arch/arm/plat-mxc/mvf_time.c +++ b/arch/arm/plat-mxc/mvf_time.c @@ -189,17 +189,25 @@ static irqreturn_t mvf_timer_interrupt(int irq, void *dev_id) static int mvf_set_next_event(unsigned long evt, struct clock_event_device *unused) { - unsigned long tcmp; + unsigned long tcmp,tmp; tcmp = evt; /* STOP Time */ - __raw_writel(__raw_readl(PIT_TCTRL(TIMER_CH)) & ~(PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); + __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) + & ~(PIT_TCTRL_TEN), + timer_base + PIT_TCTRL(TIMER_CH)); __raw_writel(tcmp, timer_base + PIT_LDVAL(TIMER_CH)); /* Start Timer */ - __raw_writel(__raw_readl(PIT_TCTRL(TIMER_CH)) | (PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); + __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) + | (PIT_TCTRL_TEN), + timer_base + PIT_TCTRL(TIMER_CH)); +#if 0 + while(1) { + tmp = __raw_readl(timer_base + PIT_CVAL(TIMER_CH)); + printk("val = %08lx\n",tmp); + } +#endif return 0; } @@ -245,17 +253,18 @@ void __init mvf_timer_init(struct clk *timer_clk, void __iomem *base, int irq) uint32_t tctrl_val; u32 reg; -#if 0 /* Clock is fix to 50MHz */ +#if 1 /* Clock is fix to 50MHz */ clk_enable(timer_clk); #endif - + printk("PIT base = 0x%08lx",(unsigned long)base); timer_base = base; /* * Initialise to a known state (all timers off, and timing reset) */ - __raw_writel(PIT_MCR_MDIS, timer_base + PIT_MCR); /* Stop PIT */ + // __raw_writel(PIT_MCR_MDIS, timer_base + PIT_MCR); /* Stop PIT */ + __raw_writel(0, timer_base + PIT_MCR); /* Stop PIT */ /* init and register the timer to the framework */ mvf_clocksource_init(timer_clk); |