diff options
-rw-r--r-- | arch/arm/mach-tegra/Kconfig | 5 | ||||
-rw-r--r-- | arch/arm/mach-tegra/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-enterprise-memory.c | 730 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-enterprise-panel.c | 487 | ||||
-rwxr-xr-x | arch/arm/mach-tegra/board-enterprise-pinmux.c | 374 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-enterprise-sdhci.c | 174 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-enterprise.c | 399 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-enterprise.h | 40 | ||||
-rw-r--r-- | arch/arm/tools/mach-types | 1 |
9 files changed, 2215 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f8e924e5be16..26d4610f274c 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -98,6 +98,11 @@ config MACH_WARIO # Cardhu # Enterprise +config MACH_TEGRA_ENTERPRISE + bool "Tegra_enterprise board" + depends on ARCH_TEGRA_3x_SOC + help + Support for NVIDIA Tegra_enterprise development platform config TEGRA_FPGA_PLATFORM bool "Support for NVIDIA Tegra FPGA platform" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index facd459541db..149946f99286 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -105,3 +105,8 @@ obj-${CONFIG_MACH_VENTANA} += board-ventana-panel.o # Cardhu # Enterprise +obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise.o +obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-panel.o +obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-pinmux.o +obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-sdhci.o +obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-memory.o diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c new file mode 100644 index 000000000000..65d0932387e3 --- /dev/null +++ b/arch/arm/mach-tegra/board-enterprise-memory.c @@ -0,0 +1,730 @@ +/* + * Copyright (C) 2011 NVIDIA, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "board-enterprise.h" +#include "tegra3_emc.h" + + +static const struct tegra_emc_table tegra_enterprise_emc_tables_h5tc2g[] = { + { + 0x30, /* Rev 3.0 */ + 27000, /* SDRAM frquency */ + { + 0x00000001, /* EMC_RC */ + 0x00000004, /* EMC_RFC */ + 0x00000000, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000A, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000B, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000003, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000B, /* EMC_RDV */ + 0x000000CB, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000032, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000F, /* EMC_RW2PDEN */ + 0x00000005, /* EMC_TXSR */ + 0x00000005, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000001, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x000000D3, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00008088, /* EMC_FBIO_CFG5 */ + 0x00780004, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000010, /* EMC_DLL_XFORM_DQS0 */ + 0x00000010, /* EMC_DLL_XFORM_DQS1 */ + 0x00000010, /* EMC_DLL_XFORM_DQS2 */ + 0x00000010, /* EMC_DLL_XFORM_DQS3 */ + 0x00000010, /* EMC_DLL_XFORM_DQS4 */ + 0x00000010, /* EMC_DLL_XFORM_DQS5 */ + 0x00000010, /* EMC_DLL_XFORM_DQS6 */ + 0x00000010, /* EMC_DLL_XFORM_DQS7 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ + 0x000002A0, /* EMC_XM2CMDPADCTRL */ + 0x0800211D, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77FFC084, /* EMC_XM2CLKPADCTRL */ + 0x01F1F108, /* EMC_XM2COMPPADCTRL */ + 0x07075504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0800012D, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000C000C, /* EMC_MRS_WAIT_CNT */ + 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000029E, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00010001, /* MC_EMEM_ARB_CFG */ + 0x8000000A, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000F, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ + 0x0000000F, /* MC_EMEM_ARB_TIMING_W2R */ + 0x0F070506, /* MC_EMEM_ARB_DA_TURNS */ + 0x00140905, /* MC_EMEM_ARB_DA_COVERS */ + 0x78430306, /* MC_EMEM_ARB_MISC0 */ + 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ + 0x00001221, /* DDR3 Mode Register 0 */ + 0x00100003, /* DDR3 Mode Register 1 */ + 0x00200008, /* DDR3 Mode Register 2 */ + }, + { + 0x30, /* Rev 3.0 */ + 54000, /* SDRAM frquency */ + { + 0x00000002, /* EMC_RC */ + 0x00000008, /* EMC_RFC */ + 0x00000001, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000A, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000B, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000003, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000B, /* EMC_RDV */ + 0x00000198, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000066, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000F, /* EMC_RW2PDEN */ + 0x0000000A, /* EMC_TXSR */ + 0x0000000A, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000002, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x000001A6, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00008088, /* EMC_FBIO_CFG5 */ + 0x00780004, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000010, /* EMC_DLL_XFORM_DQS0 */ + 0x00000010, /* EMC_DLL_XFORM_DQS1 */ + 0x00000010, /* EMC_DLL_XFORM_DQS2 */ + 0x00000010, /* EMC_DLL_XFORM_DQS3 */ + 0x00000010, /* EMC_DLL_XFORM_DQS4 */ + 0x00000010, /* EMC_DLL_XFORM_DQS5 */ + 0x00000010, /* EMC_DLL_XFORM_DQS6 */ + 0x00000010, /* EMC_DLL_XFORM_DQS7 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ + 0x000002A0, /* EMC_XM2CMDPADCTRL */ + 0x0800211D, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77FFC084, /* EMC_XM2CLKPADCTRL */ + 0x01F1F108, /* EMC_XM2COMPPADCTRL */ + 0x07075504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0800012D, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000C000C, /* EMC_MRS_WAIT_CNT */ + 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000439, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x80000014, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000F, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ + 0x0000000F, /* MC_EMEM_ARB_TIMING_W2R */ + 0x0F070506, /* MC_EMEM_ARB_DA_TURNS */ + 0x00140905, /* MC_EMEM_ARB_DA_COVERS */ + 0x78430506, /* MC_EMEM_ARB_MISC0 */ + 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ + 0x00001221, /* DDR3 Mode Register 0 */ + 0x00100003, /* DDR3 Mode Register 1 */ + 0x00200008, /* DDR3 Mode Register 2 */ + }, + { + 0x30, /* Rev 3.0 */ + 108000, /* SDRAM frquency */ + { + 0x00000005, /* EMC_RC */ + 0x00000011, /* EMC_RFC */ + 0x00000003, /* EMC_RAS */ + 0x00000001, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000A, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000B, /* EMC_W2P */ + 0x00000001, /* EMC_RD_RCD */ + 0x00000001, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000003, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000B, /* EMC_RDV */ + 0x00000330, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000000CC, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000F, /* EMC_RW2PDEN */ + 0x00000013, /* EMC_TXSR */ + 0x00000013, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000034B, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00008088, /* EMC_FBIO_CFG5 */ + 0x00780004, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000010, /* EMC_DLL_XFORM_DQS0 */ + 0x00000010, /* EMC_DLL_XFORM_DQS1 */ + 0x00000010, /* EMC_DLL_XFORM_DQS2 */ + 0x00000010, /* EMC_DLL_XFORM_DQS3 */ + 0x00000010, /* EMC_DLL_XFORM_DQS4 */ + 0x00000010, /* EMC_DLL_XFORM_DQS5 */ + 0x00000010, /* EMC_DLL_XFORM_DQS6 */ + 0x00000010, /* EMC_DLL_XFORM_DQS7 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000018, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ + 0x000002A0, /* EMC_XM2CMDPADCTRL */ + 0x0800211D, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77FFC084, /* EMC_XM2CLKPADCTRL */ + 0x01F1F108, /* EMC_XM2COMPPADCTRL */ + 0x07075504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0800012D, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000C000C, /* EMC_MRS_WAIT_CNT */ + 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000076E, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000003, /* MC_EMEM_ARB_CFG */ + 0x80000027, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000F, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ + 0x0000000F, /* MC_EMEM_ARB_TIMING_W2R */ + 0x0F070506, /* MC_EMEM_ARB_DA_TURNS */ + 0x00140906, /* MC_EMEM_ARB_DA_COVERS */ + 0x78440A07, /* MC_EMEM_ARB_MISC0 */ + 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ + 0x00001221, /* DDR3 Mode Register 0 */ + 0x00100003, /* DDR3 Mode Register 1 */ + 0x00200008, /* DDR3 Mode Register 2 */ + }, + { + 0x30, /* Rev 3.0 */ + 333500, /* SDRAM frquency */ + { + 0x00000010, /* EMC_RC */ + 0x00000035, /* EMC_RFC */ + 0x0000000B, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000A, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x00000004, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000008, /* EMC_QSAFE */ + 0x0000000D, /* EMC_RDV */ + 0x000009E9, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000027A, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000E, /* EMC_RW2PDEN */ + 0x00000039, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x0000000A, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000A2A, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00008088, /* EMC_FBIO_CFG5 */ + 0x00260004, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000010, /* EMC_DLL_XFORM_DQS0 */ + 0x00000010, /* EMC_DLL_XFORM_DQS1 */ + 0x00000010, /* EMC_DLL_XFORM_DQS2 */ + 0x00000010, /* EMC_DLL_XFORM_DQS3 */ + 0x00000010, /* EMC_DLL_XFORM_DQS4 */ + 0x00000010, /* EMC_DLL_XFORM_DQS5 */ + 0x00000010, /* EMC_DLL_XFORM_DQS6 */ + 0x00000010, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ + 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ + 0x000002A0, /* EMC_XM2CMDPADCTRL */ + 0x0800013D, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77FFC084, /* EMC_XM2CLKPADCTRL */ + 0x01F1F508, /* EMC_XM2COMPPADCTRL */ + 0x07075504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0800011D, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x01CB000C, /* EMC_MRS_WAIT_CNT */ + 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800014D4, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000A, /* MC_EMEM_ARB_CFG */ + 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000A, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000009, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000E, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_R2W */ + 0x0000000E, /* MC_EMEM_ARB_TIMING_W2R */ + 0x0E080506, /* MC_EMEM_ARB_DA_TURNS */ + 0x00170D10, /* MC_EMEM_ARB_DA_COVERS */ + 0x784A1F11, /* MC_EMEM_ARB_MISC0 */ + 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ + 0x00001321, /* DDR3 Mode Register 0 */ + 0x00100002, /* DDR3 Mode Register 1 */ + 0x00200000, /* DDR3 Mode Register 2 */ + }, + { + 0x30, /* Rev 2.0 */ + 533000, /* SDRAM frquency */ + { + 0x00000018, /* EMC_RC */ + 0x00000054, /* EMC_RFC */ + 0x00000011, /* EMC_RAS */ + 0x00000006, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000D, /* EMC_W2P */ + 0x00000006, /* EMC_RD_RCD */ + 0x00000006, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000008, /* EMC_QUSE */ + 0x00000006, /* EMC_QRST */ + 0x0000000A, /* EMC_QSAFE */ + 0x00000010, /* EMC_RDV */ + 0x00000FFD, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000003FF, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000A, /* EMC_AR2PDEN */ + 0x00000012, /* EMC_RW2PDEN */ + 0x0000005B, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000010, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000006, /* EMC_TCLKSTOP */ + 0x0000103E, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0xF0120441, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00010000, /* EMC_DLL_XFORM_DQS0 */ + 0x00010000, /* EMC_DLL_XFORM_DQS1 */ + 0x00010000, /* EMC_DLL_XFORM_DQS2 */ + 0x00010000, /* EMC_DLL_XFORM_DQS3 */ + 0x00010000, /* EMC_DLL_XFORM_DQS4 */ + 0x00010000, /* EMC_DLL_XFORM_DQS5 */ + 0x00010000, /* EMC_DLL_XFORM_DQS6 */ + 0x00010000, /* EMC_DLL_XFORM_DQS7 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00008000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00020000, /* EMC_DLL_XFORM_DQ0 */ + 0x00020000, /* EMC_DLL_XFORM_DQ1 */ + 0x00020000, /* EMC_DLL_XFORM_DQ2 */ + 0x00020000, /* EMC_DLL_XFORM_DQ3 */ + 0x000202A0, /* EMC_XM2CMDPADCTRL */ + 0x0800013D, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77FFD884, /* EMC_XM2CLKPADCTRL */ + 0x01F1F508, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0800011D, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x012B000C, /* EMC_MRS_WAIT_CNT */ + 0xA0F10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800020AE, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000008, /* MC_EMEM_ARB_CFG */ + 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000D, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090D, /* MC_EMEM_ARB_DA_COVERS */ + 0x7028180E, /* MC_EMEM_ARB_MISC0 */ + 0x001F0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000010, /* EMC_AUTO_CAL_INTERVAL */ + 0x00001941, /* DDR3 Mode Register 0 */ + 0x00100002, /* DDR3 Mode Register 1 */ + 0x00200008, /* DDR3 Mode Register 2 */ + }, + { + 0x30, /* Rev 3.0 */ + 667000, /* SDRAM frquency */ + { + 0x00000021, /* EMC_RC */ + 0x00000073, /* EMC_RFC */ + 0x00000018, /* EMC_RAS */ + 0x0000000A, /* EMC_RP */ + 0x00000006, /* EMC_R2W */ + 0x0000000E, /* EMC_W2R */ + 0x00000005, /* EMC_R2P */ + 0x00000013, /* EMC_W2P */ + 0x0000000A, /* EMC_RD_RCD */ + 0x0000000A, /* EMC_WR_RCD */ + 0x00000004, /* EMC_RRD */ + 0x00000003, /* EMC_REXT */ + 0x00000002, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000A, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x00000008, /* EMC_QSAFE */ + 0x00000013, /* EMC_RDV */ + 0x000013AE, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000006, /* EMC_PDEX2WR */ + 0x00000006, /* EMC_PDEX2RD */ + 0x00000005, /* EMC_PCHG2PDEN */ + 0x00000004, /* EMC_ACT2PDEN */ + 0x00000010, /* EMC_AR2PDEN */ + 0x0000001A, /* EMC_RW2PDEN */ + 0x0000007C, /* EMC_TXSR */ + 0x0000020A, /* EMC_TXSRDLL */ + 0x00000009, /* EMC_TCKE */ + 0x00000019, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000008, /* EMC_TCLKSTABLE */ + 0x00000009, /* EMC_TCLKSTOP */ + 0x000014B7, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00009088, /* EMC_FBIO_CFG5 */ + 0xF00B0401, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00010000, /* EMC_DLL_XFORM_DQS0 */ + 0x00010000, /* EMC_DLL_XFORM_DQS1 */ + 0x00010000, /* EMC_DLL_XFORM_DQS2 */ + 0x00010000, /* EMC_DLL_XFORM_DQS3 */ + 0x00010000, /* EMC_DLL_XFORM_DQS4 */ + 0x00010000, /* EMC_DLL_XFORM_DQS5 */ + 0x00010000, /* EMC_DLL_XFORM_DQS6 */ + 0x00010000, /* EMC_DLL_XFORM_DQS7 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00014000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000400C, /* EMC_DLL_XFORM_DQ0 */ + 0x0000400C, /* EMC_DLL_XFORM_DQ1 */ + 0x0000400C, /* EMC_DLL_XFORM_DQ2 */ + 0x0000400C, /* EMC_DLL_XFORM_DQ3 */ + 0x000002A0, /* EMC_XM2CMDPADCTRL */ + 0x0800013D, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77FFC084, /* EMC_XM2CLKPADCTRL */ + 0x01F1F508, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0800011D, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x0196000C, /* EMC_MRS_WAIT_CNT */ + 0xA0F10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800028A5, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000A, /* MC_EMEM_ARB_CFG */ + 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000012, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000B, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000C, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000C, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000003, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ + 0x09050303, /* MC_EMEM_ARB_DA_TURNS */ + 0x00170F12, /* MC_EMEM_ARB_DA_COVERS */ + 0x706A1F13, /* MC_EMEM_ARB_MISC0 */ + 0x001F0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x00000010, /* EMC_AUTO_CAL_INTERVAL */ + 0x00001b71, /* DDR3 Mode Register 0 */ + 0x00100002, /* DDR3 Mode Register 1 */ + 0x00200018, /* DDR3 Mode Register 2 */ + } +}; + +int tegra_enterprise_emc_init(void) +{ + tegra_init_emc(tegra_enterprise_emc_tables_h5tc2g, + ARRAY_SIZE(tegra_enterprise_emc_tables_h5tc2g)); + return 0; +} diff --git a/arch/arm/mach-tegra/board-enterprise-panel.c b/arch/arm/mach-tegra/board-enterprise-panel.c new file mode 100644 index 000000000000..4bb40f7ebb3b --- /dev/null +++ b/arch/arm/mach-tegra/board-enterprise-panel.c @@ -0,0 +1,487 @@ +/* + * arch/arm/mach-tegra/board-enterprise-panel.c + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/resource.h> +#include <asm/mach-types.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <asm/atomic.h> +#include <mach/nvhost.h> +#include <mach/nvmap.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/dc.h> +#include <mach/fb.h> + +#include "board.h" +#include "board-enterprise.h" +#include "devices.h" +#include "gpio-names.h" + +/* Select panel to be used. */ +#define AVDD_LCD PMU_TCA6416_GPIO_PORT17 +#define DSI_PANEL_RESET 0 + +#define tegra_enterprise_lvds_shutdown TEGRA_GPIO_PL2 +#define tegra_enterprise_bl_enb TEGRA_GPIO_PH2 +#define tegra_enterprise_bl_pwm TEGRA_GPIO_PH0 +#define tegra_enterprise_hdmi_hpd TEGRA_GPIO_PN7 + +#define tegra_enterprise_dsia_bl_enb TEGRA_GPIO_PW1 +#define tegra_enterprise_dsi_panel_reset TEGRA_GPIO_PW0 + +static struct regulator *tegra_enterprise_hdmi_reg = NULL; +static struct regulator *tegra_enterprise_hdmi_pll = NULL; +static struct regulator *tegra_enterprise_hdmi_vddio = NULL; + +static atomic_t sd_brightness = ATOMIC_INIT(255); + +static int tegra_enterprise_backlight_init(struct device *dev) +{ + int ret; + + /* Enable back light for DSIa panel */ + printk("tegra_enterprise_dsi_backlight_init\n"); + + ret = gpio_request(tegra_enterprise_dsia_bl_enb, "dsia_bl_enable"); + if (ret < 0) + return ret; + + ret = gpio_direction_output(tegra_enterprise_dsia_bl_enb, 1); + if (ret < 0) + gpio_free(tegra_enterprise_dsia_bl_enb); + else + tegra_gpio_enable(tegra_enterprise_dsia_bl_enb); + + return ret; +} + +static void tegra_enterprise_backlight_exit(struct device *dev) +{ + /* Disable back light for DSIa panel */ + gpio_set_value(tegra_enterprise_dsia_bl_enb, 0); + gpio_free(tegra_enterprise_dsia_bl_enb); + tegra_gpio_disable(tegra_enterprise_dsia_bl_enb); + + gpio_set_value(TEGRA_GPIO_PL2, 1); + mdelay(20); +} + +static int tegra_enterprise_backlight_notify(struct device *unused, int brightness) +{ + int cur_sd_brightness = atomic_read(&sd_brightness); + int orig_brightness = brightness; + + /* DSIa */ + gpio_set_value(tegra_enterprise_dsia_bl_enb, !!brightness); + + /* SD brightness is a percentage, 8-bit value. */ + brightness = (brightness * cur_sd_brightness) / 255; + if (cur_sd_brightness != 255) { + printk("NVSD BL - in: %d, sd: %d, out: %d\n", + orig_brightness, cur_sd_brightness, brightness); + } + + return brightness; +} + +static struct platform_pwm_backlight_data tegra_enterprise_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 224, + .pwm_period_ns = 5000000, + .init = tegra_enterprise_backlight_init, + .exit = tegra_enterprise_backlight_exit, + .notify = tegra_enterprise_backlight_notify, +}; + +static struct platform_device tegra_enterprise_backlight_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &tegra_enterprise_backlight_data, + }, +}; + +static int tegra_enterprise_hdmi_enable(void) +{ + int ret; + if (!tegra_enterprise_hdmi_reg) { + tegra_enterprise_hdmi_reg = regulator_get(NULL, "avdd_hdmi"); + if (IS_ERR_OR_NULL(tegra_enterprise_hdmi_reg)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); + tegra_enterprise_hdmi_reg = NULL; + return PTR_ERR(tegra_enterprise_hdmi_reg); + } + } + ret = regulator_enable(tegra_enterprise_hdmi_reg); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); + return ret; + } + if (!tegra_enterprise_hdmi_pll) { + tegra_enterprise_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll"); + if (IS_ERR_OR_NULL(tegra_enterprise_hdmi_pll)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); + tegra_enterprise_hdmi_pll = NULL; + regulator_put(tegra_enterprise_hdmi_reg); + tegra_enterprise_hdmi_reg = NULL; + return PTR_ERR(tegra_enterprise_hdmi_pll); + } + } + ret = regulator_enable(tegra_enterprise_hdmi_pll); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); + return ret; + } + if (!tegra_enterprise_hdmi_vddio) { + tegra_enterprise_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con"); + if (IS_ERR_OR_NULL(tegra_enterprise_hdmi_vddio)) { + pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n"); + tegra_enterprise_hdmi_vddio = NULL; + regulator_put(tegra_enterprise_hdmi_pll); + tegra_enterprise_hdmi_pll = NULL; + regulator_put(tegra_enterprise_hdmi_reg); + tegra_enterprise_hdmi_reg = NULL; + + return PTR_ERR(tegra_enterprise_hdmi_vddio); + } + } + ret = regulator_enable(tegra_enterprise_hdmi_vddio); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n"); + return ret; + } + return 0; +} + +static int tegra_enterprise_hdmi_disable(void) +{ + + regulator_disable(tegra_enterprise_hdmi_reg); + regulator_put(tegra_enterprise_hdmi_reg); + tegra_enterprise_hdmi_reg = NULL; + + regulator_disable(tegra_enterprise_hdmi_pll); + regulator_put(tegra_enterprise_hdmi_pll); + tegra_enterprise_hdmi_pll = NULL; + + regulator_disable(tegra_enterprise_hdmi_vddio); + regulator_put(tegra_enterprise_hdmi_vddio); + tegra_enterprise_hdmi_vddio = NULL; + return 0; +} +static struct resource tegra_enterprise_disp1_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_GENERAL, + .end = INT_DISPLAY_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY_BASE, + .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .start = 0, /* Filled in by tegra_enterprise_panel_init() */ + .end = 0, /* Filled in by tegra_enterprise_panel_init() */ + .flags = IORESOURCE_MEM, + }, + { + .name = "dsi_regs", + .start = TEGRA_DSI_BASE, + .end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource tegra_enterprise_disp2_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_B_GENERAL, + .end = INT_DISPLAY_B_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY2_BASE, + .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .flags = IORESOURCE_MEM, + .start = 0, + .end = 0, + }, + { + .name = "hdmi_regs", + .start = TEGRA_HDMI_BASE, + .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct tegra_dc_sd_settings tegra_enterprise_sd_settings = { + .enable = 1, /* Normal mode operation */ + .use_auto_pwm = false, + .hw_update_delay = 0, + .bin_width = 0, + .aggressiveness = 5, + .use_vid_luma = true, + /* Default video coefficients */ + .coeff = {5, 9, 2}, + .fc = {0, 0}, + /* Immediate backlight changes */ + .blp = {1024, 255}, + /* Default BL TF */ + .bltf = { + {128, 136, 144, 152}, + {160, 168, 176, 184}, + {192, 200, 208, 216}, + {224, 232, 240, 248} + }, + /* Default LUT */ + .lut = { + {255, 255, 255}, + {199, 199, 199}, + {153, 153, 153}, + {116, 116, 116}, + {85, 85, 85}, + {59, 59, 59}, + {36, 36, 36}, + {17, 17, 17}, + {0, 0, 0} + }, + .sd_brightness = &sd_brightness, + .bl_device = &tegra_enterprise_backlight_device, +}; + +static struct tegra_fb_data tegra_enterprise_hdmi_fb_data = { + .win = 0, + .xres = 1366, + .yres = 768, + .bits_per_pixel = 16, +}; + +static struct tegra_dc_out tegra_enterprise_disp2_out = { + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, + + .dcc_bus = 3, + .hotplug_gpio = tegra_enterprise_hdmi_hpd, + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + + .enable = tegra_enterprise_hdmi_enable, + .disable = tegra_enterprise_hdmi_disable, +}; + +static struct tegra_dc_platform_data tegra_enterprise_disp2_pdata = { + .flags = 0, + .default_out = &tegra_enterprise_disp2_out, + .fb = &tegra_enterprise_hdmi_fb_data, + .emc_clk_rate = 300000000, +}; + +static int tegra_enterprise_dsi_panel_enable(void) +{ + static struct regulator *reg = NULL; + + if (reg == NULL) { + reg = regulator_get(NULL, "avdd_dsi_csi"); + if (IS_ERR_OR_NULL(reg)) { + pr_err("dsi: Could not get regulator avdd_dsi_csi\n"); + reg = NULL; + return PTR_ERR(reg); + } + } + regulator_enable(reg); + + return 0; +} + +static int tegra_enterprise_dsi_panel_disable(void) +{ + return 0; +} + +static struct tegra_dsi_cmd dsi_init_cmd[]= { + DSI_CMD_SHORT(0x05, 0x11, 0x00), + DSI_DLY_MS(150), + DSI_CMD_SHORT(0x05, 0x29, 0x00), + DSI_DLY_MS(20), +}; + +struct tegra_dsi_out tegra_enterprise_dsi = { + .n_data_lanes = 2, + .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P, + .refresh_rate = 60, + .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0, + + .panel_has_frame_buffer = true, + .dsi_instance = 0, + .n_init_cmd = ARRAY_SIZE(dsi_init_cmd), + .dsi_init_cmd = dsi_init_cmd, + + .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, +}; + +static struct tegra_dc_mode tegra_enterprise_dsi_modes[] = { + { + .pclk = 10000000, + .h_ref_to_sync = 4, + .v_ref_to_sync = 1, + .h_sync_width = 16, + .v_sync_width = 1, + .h_back_porch = 32, + .v_back_porch = 1, + .h_active = 540, + .v_active = 960, + .h_front_porch = 32, + .v_front_porch = 2, + }, +}; + + +static struct tegra_fb_data tegra_enterprise_dsi_fb_data = { + .win = 0, + .xres = 540, + .yres = 960, + .bits_per_pixel = 32, +}; + + +static struct tegra_dc_out tegra_enterprise_disp1_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .sd_settings = &tegra_enterprise_sd_settings, + + .type = TEGRA_DC_OUT_DSI, + + .modes = tegra_enterprise_dsi_modes, + .n_modes = ARRAY_SIZE(tegra_enterprise_dsi_modes), + + .dsi = &tegra_enterprise_dsi, + + .enable = tegra_enterprise_dsi_panel_enable, + .disable = tegra_enterprise_dsi_panel_disable, +}; +static struct tegra_dc_platform_data tegra_enterprise_disp1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &tegra_enterprise_disp1_out, + .emc_clk_rate = 300000000, + .fb = &tegra_enterprise_dsi_fb_data, +}; +static struct nvhost_device tegra_enterprise_disp1_device = { + .name = "tegradc", + .id = 0, + .resource = tegra_enterprise_disp1_resources, + .num_resources = ARRAY_SIZE(tegra_enterprise_disp1_resources), + .dev = { + .platform_data = &tegra_enterprise_disp1_pdata, + }, +}; + +static struct nvhost_device tegra_enterprise_disp2_device = { + .name = "tegradc", + .id = 1, + .resource = tegra_enterprise_disp2_resources, + .num_resources = ARRAY_SIZE(tegra_enterprise_disp2_resources), + .dev = { + .platform_data = &tegra_enterprise_disp2_pdata, + }, +}; + +static struct nvmap_platform_carveout tegra_enterprise_carveouts[] = { + [0] = { + .name = "iram", + .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, + .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, + .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, + .buddy_size = 0, /* no buddy allocation for IRAM */ + }, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .base = 0, /* Filled in by tegra_enterprise_panel_init() */ + .size = 0, /* Filled in by tegra_enterprise_panel_init() */ + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data tegra_enterprise_nvmap_data = { + .carveouts = tegra_enterprise_carveouts, + .nr_carveouts = ARRAY_SIZE(tegra_enterprise_carveouts), +}; + +static struct platform_device tegra_enterprise_nvmap_device = { + .name = "tegra-nvmap", + .id = -1, + .dev = { + .platform_data = &tegra_enterprise_nvmap_data, + }, +}; + +static struct platform_device *tegra_enterprise_gfx_devices[] __initdata = { + &tegra_enterprise_nvmap_device, + &tegra_grhost_device, + &tegra_pwfm0_device, + &tegra_enterprise_backlight_device, +}; + +int __init tegra_enterprise_panel_init(void) +{ + int err; + struct resource *res; + + tegra_enterprise_carveouts[1].base = tegra_carveout_start; + tegra_enterprise_carveouts[1].size = tegra_carveout_size; + + tegra_gpio_enable(tegra_enterprise_hdmi_hpd); + gpio_request(tegra_enterprise_hdmi_hpd, "hdmi_hpd"); + gpio_direction_input(tegra_enterprise_hdmi_hpd); + + err = platform_add_devices(tegra_enterprise_gfx_devices, + ARRAY_SIZE(tegra_enterprise_gfx_devices)); + + res = nvhost_get_resource_byname(&tegra_enterprise_disp1_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + + if (!err) + err = nvhost_device_register(&tegra_enterprise_disp1_device); + + res = nvhost_get_resource_byname(&tegra_enterprise_disp2_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; + if (!err) + err = nvhost_device_register(&tegra_enterprise_disp2_device); + return err; +} diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c new file mode 100755 index 000000000000..6a0d1996346b --- /dev/null +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -0,0 +1,374 @@ +/* + * arch/arm/mach-tegra/board-enterprise-pinmux.c + * + * Copyright (C) 2011 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <mach/pinmux.h> +#include "board.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } +/* Setting the drive strength of pins + * hsm: Enable High speed mode (ENABLE/DISABLE) + * Schimit: Enable/disable schimit (ENABLE/DISABLE) + * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8) + * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive + * strength code. Value from 0 to 31. + * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive + * strength code. Value from 0 to 31. + * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + * pullup_slew - Driver Output Pull-Down slew control code - + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + */ +#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_##_hsm, \ + .schmitt = TEGRA_SCHMITT_##_schmitt, \ + .drive = TEGRA_DRIVE_##_drive, \ + .pull_down = TEGRA_PULL_##_pulldn_drive, \ + .pull_up = TEGRA_PULL_##_pullup_drive, \ + .slew_rising = TEGRA_SLEW_##_pulldn_slew, \ + .slew_falling = TEGRA_SLEW_##_pullup_slew, \ + } + +/* !!!FIXME!!!! POPULATE THIS TABLE */ +static __initdata struct tegra_drive_pingroup_config tegra_enterprise_drive_pinmux[] = { + /* DEFAULT_DRIVE(<pin_group>), */ + /* SET_DRIVE(ATA, DISABLE, DISABLE, DIV_1, 31, 31, FAST, FAST) */ + SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* All I2C pins are driven to maximum drive strength */ + /* GEN1 I2C */ + SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* GEN2 I2C */ + SET_DRIVE(AT5, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* CAM I2C */ + SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* DDC I2C */ + SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* PWR_I2C */ + SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), +}; + +#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_DEFAULT, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_##_od, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + +static __initdata struct tegra_pingroup_config tegra_enterprise_pinmux[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PV3, CLK12, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_MCLK, VI, PULL_UP, NORMAL, INPUT), + + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_RST_N, RSVD3, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ + DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ + DEFAULT_PINMUX(GMI_A16, SPI4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, SPI4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, SPI4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, SPI4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW0, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), +#ifdef CONFIG_SND_HDA_CODEC_REALTEK + DEFAULT_PINMUX(SPDIF_IN, DAP2, PULL_DOWN, NORMAL, INPUT), +#else + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), +#endif + DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), +#ifdef CONFIG_SND_HDA_CODEC_REALTEK + DEFAULT_PINMUX(DAP2_FS, HDA, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, HDA, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, HDA, PULL_DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, HDA, PULL_DOWN, NORMAL, INPUT), +#else + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), +#endif + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT), + + /* Gpios */ + /* SDMMC1 CD gpio */ + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT), + /* SDMMC1 WP gpio */ + DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT), + + /* Touch panel GPIO */ + /* Touch IRQ */ + DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT), + + /* Touch RESET */ + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT), + + /* Power rails GPIO */ + DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, PULL_UP, NORMAL, INPUT), + VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_PCLK, RSVD1, PULL_UP, TRISTATE, INPUT, DISABLE, ENABLE), + VI_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), +}; + +int __init tegra_enterprise_pinmux_init(void) +{ + tegra_pinmux_config_table(tegra_enterprise_pinmux, ARRAY_SIZE(tegra_enterprise_pinmux)); + tegra_drive_pinmux_config_table(tegra_enterprise_drive_pinmux, + ARRAY_SIZE(tegra_enterprise_drive_pinmux)); + return 0; +} diff --git a/arch/arm/mach-tegra/board-enterprise-sdhci.c b/arch/arm/mach-tegra/board-enterprise-sdhci.c new file mode 100644 index 000000000000..5596dbe91086 --- /dev/null +++ b/arch/arm/mach-tegra/board-enterprise-sdhci.c @@ -0,0 +1,174 @@ +/* + * arch/arm/mach-tegra/board-enterprise-sdhci.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/resource.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/mmc/host.h> + +#include <asm/mach-types.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/sdhci.h> + +#include "gpio-names.h" +#include "board.h" + + +#define TEGRA_ENTERPRISE_SD_CD TEGRA_GPIO_PI5 +#define TEGRA_ENTERPRISE_SD_WP TEGRA_GPIO_PT3 + +static struct resource sdhci_resource0[] = { + [0] = { + .start = INT_SDMMC1, + .end = INT_SDMMC1, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC1_BASE, + .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource3[] = { + [0] = { + .start = INT_SDMMC4, + .end = INT_SDMMC4, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC4_BASE, + .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = { + .clk_id = NULL, + .force_hs = 1, + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .tap_delay = 6, + .is_voltage_switch_supported = true, + .vsd_name = "vddio_sdmmc1", + .vsd_slot_name = "vddio_sd_slot", + .max_clk = 208000000, + .is_8bit_supported = false, +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { + .clk_id = NULL, + .force_hs = 0, + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .tap_delay = 6, + .is_voltage_switch_supported = false, + .vsd_name = NULL, + .vsd_slot_name = NULL, + .max_clk = 48000000, + .is_8bit_supported = true, +}; + +static struct platform_device tegra_sdhci_device0 = { + .name = "sdhci-tegra", + .id = 0, + .resource = sdhci_resource0, + .num_resources = ARRAY_SIZE(sdhci_resource0), + .dev = { + .platform_data = &tegra_sdhci_platform_data0, + }, +}; + +static struct platform_device tegra_sdhci_device3 = { + .name = "sdhci-tegra", + .id = 3, + .resource = sdhci_resource3, + .num_resources = ARRAY_SIZE(sdhci_resource3), + .dev = { + .platform_data = &tegra_sdhci_platform_data3, + }, +}; + +static int tegra_enterprise_sd_cd_gpio_init(void) +{ + unsigned int rc = 0; + + rc = gpio_request(TEGRA_ENTERPRISE_SD_CD, "card_detect"); + if (rc) { + pr_err("Card detect gpio request failed:%d\n", rc); + return rc; + } + + tegra_gpio_enable(TEGRA_ENTERPRISE_SD_CD); + + rc = gpio_direction_input(TEGRA_ENTERPRISE_SD_CD); + if (rc) { + pr_err("Unable to configure direction for card detect gpio:%d\n", rc); + return rc; + } + + return 0; +} + +static int tegra_enterprise_sd_wp_gpio_init(void) +{ + unsigned int rc = 0; + + rc = gpio_request(TEGRA_ENTERPRISE_SD_WP, "write_protect"); + if (rc) { + pr_err("Write protect gpio request failed:%d\n", rc); + return rc; + } + + tegra_gpio_enable(TEGRA_ENTERPRISE_SD_WP); + + rc = gpio_direction_input(TEGRA_ENTERPRISE_SD_WP); + if (rc) { + pr_err("Unable to configure direction for write protect gpio:%d\n", rc); + return rc; + } + + return 0; +} + +int __init tegra_enterprise_sdhci_init(void) +{ + unsigned int rc = 0; + platform_device_register(&tegra_sdhci_device3); + + /* Fix ME: The gpios have to enabled for hot plug support */ + rc = tegra_enterprise_sd_cd_gpio_init(); + if (!rc) { + tegra_sdhci_platform_data0.cd_gpio = TEGRA_ENTERPRISE_SD_CD; + tegra_sdhci_platform_data0.cd_gpio_polarity = 0; + } + rc = tegra_enterprise_sd_wp_gpio_init(); + if (!rc) { + tegra_sdhci_platform_data0.wp_gpio = TEGRA_ENTERPRISE_SD_WP; + tegra_sdhci_platform_data0.wp_gpio_polarity = 1; + } + + platform_device_register(&tegra_sdhci_device0); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c new file mode 100644 index 000000000000..c99e753e5f21 --- /dev/null +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -0,0 +1,399 @@ +/* + * arch/arm/mach-tegra/board-enterprise.c + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/ctype.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/dma-mapping.h> +#include <linux/delay.h> +#include <linux/i2c-tegra.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/platform_data/tegra_usb.h> +#include <linux/spi/spi.h> +#include <mach/clk.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/pinmux.h> +#include <mach/iomap.h> +#include <mach/io.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/usb_phy.h> + +#include "board.h" +#include "clock.h" +#include "board-enterprise.h" +#include "devices.h" +#include "gpio-names.h" +#include "fuse.h" + + +static struct plat_serial8250_port debug_uart_platform_data[] = { + { + .membase = IO_ADDRESS(TEGRA_UARTA_BASE), + .mapbase = TEGRA_UARTA_BASE, + .irq = INT_UARTA, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .type = PORT_TEGRA, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, { + .flags = 0, + } +}; + +static struct platform_device debug_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = debug_uart_platform_data, + }, +}; + +/* !!!TODO: Change for tegra_enterprise (Taken from Cardhu) */ +static struct tegra_utmip_config utmi_phy_config[] = { + [0] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 15, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, + [1] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 15, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, + [2] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 8, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, +}; + +#ifdef CONFIG_BCM4329_RFKILL +static struct resource tegra_enterprise_bcm4329_rfkill_resources[] = { + { + .name = "bcm4329_nshutdown_gpio", + .start = TEGRA_GPIO_PU0, + .end = TEGRA_GPIO_PU0, + .flags = IORESOURCE_IO, + }, +}; + +static struct platform_device tegra_enterprise_bcm4329_rfkill_device = { + .name = "bcm4329_rfkill", + .id = -1, + .num_resources = ARRAY_SIZE(tegra_enterprise_bcm4329_rfkill_resources), + .resource = tegra_enterprise_bcm4329_rfkill_resources, +}; + +static noinline void __init tegra_enterprise_bt_rfkill(void) +{ + platform_device_register(&tegra_enterprise_bcm4329_rfkill_device); + + return; +} +#else +static inline void tegra_enterprise_bt_rfkill(void) { } +#endif + +static __initdata struct tegra_clk_init_table tegra_enterprise_clk_init_table[] = { + /* name parent rate enabled */ + { "uarta", "pll_p", 216000000, true}, + { "uartb", "pll_p", 216000000, false}, + { "uartc", "pll_p", 216000000, false}, + { "uartd", "pll_p", 216000000, false}, + { "uarte", "pll_p", 216000000, false}, + { "pll_m", NULL, 0, true}, + { "hda", "pll_p", 108000000, false}, + { "hda2codec_2x","pll_p", 48000000, false}, + { "pll_p_out4", "pll_p", 24000000, true }, + { "pwm", "clk_32k", 32768, false}, + { "blink", "clk_32k", 32768, true}, + { "pll_a", NULL, 56448000, true}, + { "pll_a_out0", NULL, 11289600, true}, + { NULL, NULL, 0, 0}, +}; + +static struct i2c_board_info __initdata tegra_enterprise_i2c_bus1_board_info[] = { + { + I2C_BOARD_INFO("wm8903", 0x1a), + }, +}; + +static struct tegra_i2c_platform_data tegra_enterprise_i2c1_platform_data = { + .adapter_nr = 0, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data tegra_enterprise_i2c2_platform_data = { + .adapter_nr = 1, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, + .is_clkon_always = true, +}; + +static struct tegra_i2c_platform_data tegra_enterprise_i2c3_platform_data = { + .adapter_nr = 2, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data tegra_enterprise_i2c4_platform_data = { + .adapter_nr = 3, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data tegra_enterprise_i2c5_platform_data = { + .adapter_nr = 4, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static void tegra_enterprise_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &tegra_enterprise_i2c1_platform_data; + tegra_i2c_device2.dev.platform_data = &tegra_enterprise_i2c2_platform_data; + tegra_i2c_device3.dev.platform_data = &tegra_enterprise_i2c3_platform_data; + tegra_i2c_device4.dev.platform_data = &tegra_enterprise_i2c4_platform_data; + tegra_i2c_device5.dev.platform_data = &tegra_enterprise_i2c5_platform_data; + + platform_device_register(&tegra_i2c_device5); + platform_device_register(&tegra_i2c_device4); + platform_device_register(&tegra_i2c_device3); + platform_device_register(&tegra_i2c_device2); + platform_device_register(&tegra_i2c_device1); +} + +static struct resource tegra_rtc_resources[] = { + [0] = { + .start = TEGRA_RTC_BASE, + .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_RTC, + .end = INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tegra_rtc_device = { + .name = "tegra_rtc", + .id = -1, + .resource = tegra_rtc_resources, + .num_resources = ARRAY_SIZE(tegra_rtc_resources), +}; + +static struct platform_device tegra_camera = { + .name = "tegra_camera", + .id = -1, +}; + +static struct platform_device *tegra_enterprise_devices[] __initdata = { + &debug_uart, + &tegra_uartb_device, + &tegra_uartc_device, + &tegra_uartd_device, + &tegra_uarte_device, + &pmu_device, + &tegra_rtc_device, + &tegra_udc_device, +#if defined(CONFIG_SND_HDA_TEGRA) + &tegra_hda_device, +#endif +#if defined(CONFIG_TEGRA_IOVMM_SMMU) + &tegra_smmu_device, +#endif + &tegra_wdt_device, + &tegra_avp_device, + &tegra_camera, + &tegra_spi_device4, +}; + +static struct usb_phy_plat_data tegra_usb_phy_pdata[] = { + [0] = { + .instance = 0, + .vbus_gpio = -1, + .vbus_reg_supply = "vdd_vbus_micro_usb", + }, + [1] = { + .instance = 1, + .vbus_gpio = -1, + }, + [2] = { + .instance = 2, + .vbus_gpio = -1, + .vbus_reg_supply = "vdd_vbus_typea_usb", + }, +}; + + +static struct tegra_ehci_platform_data tegra_ehci_pdata[] = { + [0] = { + .phy_config = &utmi_phy_config[0], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + .usb_phy_type = TEGRA_USB_PHY_TYPE_UTMIP, + }, + [1] = { + .phy_config = &utmi_phy_config[1], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + .usb_phy_type = TEGRA_USB_PHY_TYPE_UTMIP, + }, + [2] = { + .phy_config = &utmi_phy_config[2], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + .usb_phy_type = TEGRA_USB_PHY_TYPE_UTMIP, + }, +}; + +struct platform_device *tegra_usb_otg_host_register(void) +{ + struct platform_device *pdev; + void *platform_data; + int val; + + pdev = platform_device_alloc(tegra_ehci1_device.name, + tegra_ehci1_device.id); + if (!pdev) + return NULL; + + val = platform_device_add_resources(pdev, tegra_ehci1_device.resource, + tegra_ehci1_device.num_resources); + if (val) + goto error; + + pdev->dev.dma_mask = tegra_ehci1_device.dev.dma_mask; + pdev->dev.coherent_dma_mask = tegra_ehci1_device.dev.coherent_dma_mask; + + platform_data = kmalloc(sizeof(struct tegra_ehci_platform_data), + GFP_KERNEL); + if (!platform_data) + goto error; + + memcpy(platform_data, &tegra_ehci_pdata[0], + sizeof(struct tegra_ehci_platform_data)); + pdev->dev.platform_data = platform_data; + + val = platform_device_add(pdev); + if (val) + goto error_add; + + return pdev; + +error_add: + kfree(platform_data); +error: + pr_err("%s: failed to add the host contoller device\n", __func__); + platform_device_put(pdev); + return NULL; +} + +void tegra_usb_otg_host_unregister(struct platform_device *pdev) +{ + platform_device_unregister(pdev); +} + +static struct tegra_otg_platform_data tegra_otg_pdata = { + .host_register = &tegra_usb_otg_host_register, + .host_unregister = &tegra_usb_otg_host_unregister, +}; + +static void tegra_enterprise_usb_init(void) +{ + tegra_usb_phy_init(tegra_usb_phy_pdata, ARRAY_SIZE(tegra_usb_phy_pdata)); + + tegra_otg_device.dev.platform_data = &tegra_otg_pdata; + platform_device_register(&tegra_otg_device); + + tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1]; + platform_device_register(&tegra_ehci2_device); + + + tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2]; + platform_device_register(&tegra_ehci3_device); + +} + +static void tegra_enterprise_gps_init(void) +{ + tegra_gpio_enable(TEGRA_GPIO_PU2); + tegra_gpio_enable(TEGRA_GPIO_PU3); +} + +static void tegra_enterprise_modem_init(void) +{ + tegra_gpio_enable(TEGRA_GPIO_PH5); +} + +static void __init tegra_tegra_enterprise_init(void) +{ + tegra_common_init(); + tegra_clk_init_from_table(tegra_enterprise_clk_init_table); + tegra_enterprise_pinmux_init(); + tegra_enterprise_i2c_init(); + platform_add_devices(tegra_enterprise_devices, ARRAY_SIZE(tegra_enterprise_devices)); + tegra_enterprise_sdhci_init(); + tegra_enterprise_usb_init(); + tegra_enterprise_gps_init(); + tegra_enterprise_modem_init(); + tegra_enterprise_panel_init(); + tegra_enterprise_bt_rfkill(); + tegra_enterprise_emc_init(); +} + +static void __init tegra_tegra_enterprise_reserve(void) +{ + tegra_reserve(SZ_128M, SZ_4M, SZ_8M); +} + +MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise") + .boot_params = 0x80000100, + .phys_io = IO_APB_PHYS, + .io_pg_offst = ((IO_APB_VIRT) >> 18) & 0xfffc, + .init_irq = tegra_init_irq, + .init_machine = tegra_tegra_enterprise_init, + .map_io = tegra_map_common_io, + .reserve = tegra_tegra_enterprise_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-enterprise.h b/arch/arm/mach-tegra/board-enterprise.h new file mode 100644 index 000000000000..f4c1bf8fbad1 --- /dev/null +++ b/arch/arm/mach-tegra/board-enterprise.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-tegra/board-enterprise.h + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _MACH_TEGRA_BOARD_ENTERPRISE_H +#define _MACH_TEGRA_BOARD_ENTERPRISE_H + +#include <mach/gpio.h> +#include <mach/irqs.h> + +int tegra_enterprise_charge_init(void); +int tegra_enterprise_sdhci_init(void); +int tegra_enterprise_pinmux_init(void); +int tegra_enterprise_panel_init(void); +int touch_init(void); +int tegra_enterprise_emc_init(void); + +/* Touchscreen GPIO addresses */ +#ifdef CONFIG_TOUCHSCREEN_ATMEL_MT_T9 +#define TOUCH_GPIO_IRQ_ATMEL_T9 TEGRA_GPIO_PH4 +#define TOUCH_GPIO_RST_ATMEL_T9 TEGRA_GPIO_PH6 +#endif + +#endif diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 1a044e2117a5..10d33f4ad4b0 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1114,3 +1114,4 @@ thales_adc MACH_THALES_ADC THALES_ADC 3492 ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 atdgp318 MACH_ATDGP318 ATDGP318 3494 # Enterprise +tegra_enterprise MACH_TEGRA_ENTERPRISE TEGRA_ENTERPRISE 3435 |