diff options
193 files changed, 31943 insertions, 1593 deletions
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/stmpe-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/stmpe-adc.txt new file mode 100644 index 000000000000..b73a1069ed8e --- /dev/null +++ b/Documentation/devicetree/bindings/staging/iio/adc/stmpe-adc.txt @@ -0,0 +1,30 @@ +STMPE ADC driver +---------------- + +Required properties: + - compatible: "st,stmpe-adc" + +Optional properties: +Note that the ADC is shared with the STMPE touchscreen, so if using both the +settings should be the same. +If they are not, the last one to be initialized will win. +- st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 -> + 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6 + -> 144 clocks), recommended is 4. +- st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) +- st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external + reference) +- st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) + +Node name must be stmpe_adc and should be child node of stmpe node to +which it belongs. + +Example: + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + }; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c5f9a1956e55..fb94e06491de 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -113,6 +113,11 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx53-mba53.dtb \ imx53-qsb.dtb \ imx53-smd.dtb \ + imx6dl-colibri-eval-v3.dtb \ + imx6dl-nit6xlite.dtb \ + imx6dl-nitrogen6x.dtb \ + imx6dl-nitrogen6_max.dtb \ + imx6dl-nitrogen6_mtp.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabreauto-ecspi.dtb \ imx6dl-sabreauto-flexcan1.dtb \ @@ -122,7 +127,12 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-sabresd-ldo.dtb \ imx6dl-sabresd-pf200.dtb \ imx6dl-wandboard.dtb \ + imx6q-apalis-eval.dtb \ + imx6q-apalis-eval_v1_0.dtb \ imx6q-arm2.dtb \ + imx6q-nitrogen6x.dtb \ + imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_mtp.dtb \ imx6q-sabreauto.dtb \ imx6q-sabreauto-ecspi.dtb \ imx6q-sabreauto-flexcan1.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts new file mode 100644 index 000000000000..ad284b74c07b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -0,0 +1,252 @@ +/* + * Copyright 2014 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-eval", "toradex,colibri_imx6dl", "fsl,imx6dl"; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = "/soc/aips-bus@02000000/snvs@020cc000/snvs-rtc-lp@34"; + }; + + aliases { + /* the following, together with kernel patches, forces a fixed assignment + between device id and usdhc controller */ + /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */ + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4bit slot */ + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wakeup"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + ledpwm2 { + label = "PWM<B>"; + pwms = <&pwm1 0 50000>; + max-brightness = <255>; + }; + + ledpwm3 { + label = "PWM<C>"; + pwms = <&pwm4 0 50000>; + max-brightness = <255>; + }; + + ledpwm4 { + label = "PWM<D>"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; + + regulators { + reg_usb_host_vbus: usb_host_vbus { + status = "okay"; + }; + }; +}; + +&backlight { +#if 0 + /* PWM polarity: 1 is brightest */ + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; +#else + /* PWM plarity: 0 is brightest */ + brightness-levels = <0 74 128 164 192 210 255>; + default-brightness-level = <1>; +#endif + status = "okay"; +}; + +/* Colibri SPI */ +&ecspi4 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + status = "okay"; +}; + +&hdmi_video { + status = "okay"; +}; + +/* + * I2C: I2C3_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ +&i2c3 { + status = "okay"; +#if 0 /* not standard pinout, disable PWM<B>, PWM<C> + pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + gpios = <&gpio1 9 0 /* SODIMM-28, Pen down interrupt */ + &gpio2 10 0 /* SODIMM-30, Reset */ + >; + }; +#endif + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 pin 205/207 + */ +&i2cddc { + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&iomuxc { + /* + * Mux all pins which are unused to be GPIOs + * so they are ready for export to user space + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 + &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 + &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 + &pinctrl_csi_gpio_1 + &pinctrl_gpio_1 + &pinctrl_gpio_2 + &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 + &pinctrl_usbc_det_1>; +}; + +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&sound_hdmi { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +#if 0 + linux,rs485-enabled-at-boot-time; +#endif +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* MMC */ +&usdhc1 { + status = "okay"; +}; + +&weim { + status = "okay"; + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */ + ranges = <0 0 0x08000000 0x02000000 + 1 0 0x0a000000 0x02000000 + 2 0 0x0c000000 0x02000000>; + /* SRAM on CS0 */ + sram@0,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <0 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; + /* SRAM on CS1 */ + sram@1,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <1 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/imx6dl-nit6xlite.dts new file mode 100644 index 000000000000..08a76c056e05 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nit6xlite.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-nit6xlite.dtsi" + +/ { + model = "Freescale i.MX6 Solo Nit6x-Lite Board"; + compatible = "fsl,imx6dl-nit6xlite", "fsl,imx6q"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_max.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_max.dts new file mode 100644 index 000000000000..2d25c2d4b60c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_max.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6 Max Board"; + compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&ov5640 { + ipu_id = <0>; +}; + +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6_mtp.dts b/arch/arm/boot/dts/imx6dl-nitrogen6_mtp.dts new file mode 100644 index 000000000000..e5ad39c8b5ac --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6_mtp.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6_mtp.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6 MTP Board"; + compatible = "fsl,imx6dl-nitrogen6_mtp", "fsl,imx6dl"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&ov5640 { + ipu_id = <0>; +}; + +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts new file mode 100644 index 000000000000..9620f2949b42 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6x Board"; + compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&ov5640 { + ipu_id = <0>; +}; + +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0xb0b1 + >; +}; diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h index b81a7a4ebab6..1578dea533c9 100644 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h @@ -950,6 +950,7 @@ #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts new file mode 100644 index 000000000000..6ce793289114 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -0,0 +1,24 @@ +/* + * Copyright 2014 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" +#include "imx6qdl-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX6Q on Apalis Evaluation Board"; + compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval_v1_0.dts b/arch/arm/boot/dts/imx6q-apalis-eval_v1_0.dts new file mode 100644 index 000000000000..277b8847f837 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-apalis-eval_v1_0.dts @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +/* on HW V1.0 all RxD/TxD lines are routed in a DCE way, all control lines (RTS/...) + are then not routed as given in the module specification and thus unusable. + The following define configures the UARTs to RxD/TxD correctly */ +#define USE_UART_IN_DCE_MODE +#include "imx6qdl-apalis.dtsi" +#include "imx6qdl-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX6Q on Apalis Evaluation Board"; + compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts new file mode 100644 index 000000000000..ee5eca0006b7 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6 Max Board"; + compatible = "fsl,imx6q-nitrogen6_max", "fsl,imx6q"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <1>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_mtp.dts b/arch/arm/boot/dts/imx6q-nitrogen6_mtp.dts new file mode 100644 index 000000000000..01417d2f6f77 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6_mtp.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6_mtp.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6 MTP Board"; + compatible = "fsl,imx6q-nitrogen6_mtp", "fsl,imx6q"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <1>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts new file mode 100644 index 000000000000..a500ddf3f485 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 Quad Nitrogen6x Board"; + compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&ov5640 { + ipu_id = <1>; +}; + +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; +}; + +&sata { + status = "okay"; +}; + +&v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <1>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index 97ed0816a6e0..c68c21d67304 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -1024,6 +1024,7 @@ #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index bdcabc9f5b41..d53b7a4a34f9 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -11,164 +11,61 @@ */ /dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> #include "imx6q.dtsi" +#include "imx6qdl-sabrelite.dtsi" / { model = "Freescale i.MX6 Quad SABRE Lite Board"; compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; - - regulators { - compatible = "simple-bus"; - - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: usb_otg_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - - sound { - compatible = "fsl,imx6q-sabrelite-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx6q-sabrelite-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&codec>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <4>; - }; }; -&audmux { +&mxcfb1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; }; -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; +&mxcfb2 { status = "okay"; - - flash: m25p80@0 { - compatible = "sst,sst25vf016b"; - spi-max-frequency = <20000000>; - reg = <0>; - }; }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; +&mxcfb3 { status = "okay"; }; -&i2c1 { +&mxcfb4 { status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 201>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 - MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 - >; - }; - }; +&ov5640 { + ipu_id = <1>; }; -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; - disable-over-current; - status = "okay"; +&pinctrl_ov5640 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0xb0b1 + MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0xb0b1 + MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0xb0b1 + MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0xb0b1 + MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0xb0b1 + MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0xb0b1 + MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0xb0b1 + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0xb0b1 + MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0xb0b1 + MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0xb0b1 + MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0xb0b1 + MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0xb0b1 + >; }; &sata { status = "okay"; }; -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; - cd-gpios = <&gpio7 0 0>; - wp-gpios = <&gpio7 1 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&usdhc4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_2>; - cd-gpios = <&gpio2 6 0>; - wp-gpios = <&gpio2 7 0>; - vmmc-supply = <®_3p3v>; +&v4l2_cap_2 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <1>; + csi_id = <1>; + mclk_source = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi new file mode 100644 index 000000000000..6b5fee51c1d5 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi @@ -0,0 +1,290 @@ +/* + * Copyright 2014 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = "/soc/aips-bus@02000000/snvs@020cc000/snvs-rtc-lp@34"; + }; + + aliases { + /* the following, together with kernel patches, forces a fixed assignment + between device id and usdhc controller */ + /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */ + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc1; /* MMC1 8bit slot */ + mmc2 = &usdhc2; /* SD1 4bit slot */ + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "wakeup"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + ledpwm1 { + label = "PWM1"; + pwms = <&pwm1 0 50000>; + max-brightness = <255>; + }; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + + ledpwm3 { + label = "PWM3"; + pwms = <&pwm3 0 50000>; + max-brightness = <255>; + }; + }; + + regulators { + reg_usb_otg_vbus: usb_otg_vbus { + status = "okay"; + }; + + reg_usb_host_vbus: usb_host_vbus { + status = "okay"; + }; + }; +}; + +&backlight { +#if 0 + /* PWM polarity: 1 is brightest */ + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; +#else + /* PWM plarity: 0 is brightest */ + brightness-levels = <0 74 128 164 192 210 255>; + default-brightness-level = <1>; +#endif + status = "okay"; +}; + +/* Apalis SPI1 */ +&ecspi1 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +/* Apalis SPI2 */ +&ecspi2 { + status = "okay"; + + spidev1: spidev@2 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + status = "okay"; +}; + +&hdmi_core { + status = "okay"; +}; + +&hdmi_video { + status = "okay"; +}; + +/* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ +&i2c1 { + status = "okay"; + + pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + gpios = <&gpio6 10 0 /* MXM-11, Pen down interrupt */ + &gpio6 9 0 /* MXM-13, Reset */ + >; + }; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +/* + * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 pin 201/203 (unused) + */ +&i2c3 { + status = "okay"; +}; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 pin 205/207 + */ +&i2cddc { + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&iomuxc { + /* + * Mux the Apalis GPIOs, GPIO7 used for PCIe reset, + * GPIO5, 6 used by optional fusion_F0710A kernel module + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 + &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 + &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 + &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>; +}; + +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio1 2 0>; + reset-ep-gpio = <&gpio1 28 0>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_hdmi { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +#if 0 + linux,rs485-enabled-at-boot-time; +#endif +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + status = "okay"; +}; + +/* SD1 */ +&usdhc2 { + status = "okay"; +}; + +&vdac { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi new file mode 100644 index 000000000000..384bc7553b6a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -0,0 +1,868 @@ +/* + * Copyright 2014 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/input/input.h> + +/ { + model = "Toradex Apalis iMX6Q Module"; + compatible = "toradex,apalis_imx6q", "fsl,imx6q"; + + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + status = "disabled"; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 pin 205/207 + */ + i2cddc: i2c@0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_ddc>; + gpios = <&gpio3 16 0 /* sda */ + &gpio2 30 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <1>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_t1>; + status = "disabled"; + }; + + memory { + /* This node is rewritten by U-Boot with the actual memory size */ + reg = <0x10000000 0x80000000>; + }; + +#if 0 + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "mipi_dsi"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#else + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "LVDS666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#endif + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; +/* default_bpp = <16>;*/ + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + +#if 0 + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; +#else + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "vdac"; + interface_pix_fmt = "RGB565"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; +#endif + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + status = "disabled"; + }; + + /* on module usb hub */ + reg_usb_host_vbus_hub: usb_host_vbus_hub { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; + regulator-name = "usb_host_vbus_hub"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 28 0>; + startup-delay-us = <2000>; + enable-active-high; + status = "okay"; + }; + + reg_usb_host_vbus: usb_host_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + enable-active-high; + vin-supply = <®_usb_host_vbus_hub>; + status = "disabled"; + }; + }; + + sound { + compatible = "fsl,imx6q-apalis-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-apalis-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + + sound_hdmi: sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + status = "disabled"; + }; + + sound_spdif: sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + spdif-in; + status = "disabled"; + }; + + vdac: vdac@0 { + compatible = "fsl,vdac"; + ipu_id = <1>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_t1>; + status = "disabled"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_t1 &pinctrl_audmux_mclk_1>; + status = "okay"; +}; + +/* Apalis SPI1 */ +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio5 25 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_t1 &pinctrl_spi_cs1>; + status = "disabled"; +}; + +/* Apalis SPI2 */ +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio2 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_t1 &pinctrl_spi_cs2>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_4 &pinctrl_enet_ctrl_1>; + phy-mode = "rgmii"; + /*phy-reset-gpios = <&gpio1 25 0>;*/ + status = "okay"; + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_t1>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + status = "disabled"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec_2>; + status = "disabled"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "disabled"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "disabled"; +}; + +/* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_2>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int_1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + reg = <0>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + }; + }; +}; + +/* + * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 pin 201/203 (unused) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_1>; + status = "disabled"; +}; + +/* PAD Ctrl Values for Common Settings */ +#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/ +#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/ +#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/ +#define PAD_CTRL_NO 0x80000000 + +&iomuxc { + audmux { + + pinctrl_audmux_t1: audmux-t1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi1 { + + pinctrl_ecspi1_t1: ecspi1grp-t1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 + >; + }; + }; + + ecspi2 { + pinctrl_ecspi2_t1: ecspi2grp-t1 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + >; + }; + }; + + flexcan1 { + + pinctrl_flexcan1_t1: flexcan1grp-t1 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 + >; + }; + }; + + imx6q-apalis { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci &pinctrl_emmc_reset_1>; + pinctrl_apalis_gpio1: apalis_gpio1-1 { + fsl,pins = < + /* Apalis GPIO */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 PAD_CTRL_HYS_PD /* Apalis GPIO1 */ + >; + }; + pinctrl_apalis_gpio2: apalis_gpio2-1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 PAD_CTRL_HYS_PD /* Apalis GPIO2 */ + >; + }; + pinctrl_apalis_gpio3: apalis_gpio3-1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 PAD_CTRL_HYS_PD /* Apalis GPIO3 */ + >; + }; + pinctrl_apalis_gpio4: apalis_gpio4-1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 PAD_CTRL_HYS_PD /* Apalis GPIO4 */ + >; + }; + pinctrl_apalis_gpio5: apalis_gpio5-1 { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 PAD_CTRL_HYS_PD /* Apalis GPIO5 */ + >; + }; + pinctrl_apalis_gpio6: apalis_gpio6-1 { + fsl,pins = < + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 PAD_CTRL_HYS_PD /* Apalis GPIO6 */ + >; + }; + pinctrl_apalis_gpio7: apalis_gpio7-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 PAD_CTRL_HYS_PD /* Apalis GPIO7 */ + >; + }; + pinctrl_apalis_gpio8: apalis_gpio8-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 PAD_CTRL_HYS_PD /* Apalis GPIO8 */ + >; + }; + pinctrl_audmux_mclk_1: audmux_mclk-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + >; + }; + pinctrl_emmc_reset_1: emmc_reset-1 { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 PAD_CTRL_PU_22k /* eMMC reset, leave it alone */ + >; + }; + pinctrl_enet_ctrl_1: enet_ctrl-1 { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 PAD_CTRL_NO /* ENET phy reset */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 PAD_CTRL_HYS_PU /* ENET phy interrupt */ + >; + }; + pinctrl_gpio_keys: gpio_keys { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 PAD_CTRL_HYS_PU /* Power Button */ + >; + }; + pinctrl_i2c_ddc: i2c_ddc { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 PAD_CTRL_HYS_PU /* DDC bitbang */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 PAD_CTRL_HYS_PU /* DDC bitbang */ + >; + }; + pinctrl_mmc_cd: gpio_mmc_cd { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 PAD_CTRL_NO /* MMC1 CD */ + >; + }; + pinctrl_regulator_usbh_pwr: gpio_regulator_usbh_pwr { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 PAD_CTRL_PU_22k /* USBH_EN */ + >; + }; + pinctrl_regulator_usbhub_pwr: gpio_regulator_usbhub_pwr { + fsl,pins = < + MX6QDL_PAD_EIM_D28__GPIO3_IO28 PAD_CTRL_PU_22k /* USBH_HUB_EN */ + >; + }; + pinctrl_regulator_usbotg_pwr: gpio_regulator_usbotg_pwr { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 PAD_CTRL_PU_22k /* USBO power en */ + >; + }; + pinctrl_reset_moci: gpio_reset_moci { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 PAD_CTRL_PU_22k /* RESET_MOCI control */ + >; + }; + pinctrl_sd_cd: gpio_sd_cd { + fsl,pins = < + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 PAD_CTRL_NO /* SD1 CD */ + >; + }; + pinctrl_spi_cs1: spi_cs1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 PAD_CTRL_NO /* SPI1 cs */ + >; + }; + pinctrl_spi_cs2: spi_cs2 { + fsl,pins = < + MX6QDL_PAD_EIM_RW__GPIO2_IO26 PAD_CTRL_NO /* SPI2 cs */ + >; + }; + pinctrl_touch_int_1: touch_int-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 PAD_CTRL_HYS_PU /* STMPE811 interrupt */ + >; + }; + }; + + ipu1 { + + pinctrl_ipu1_t1: ipu1grp-t1 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 /* DE */ + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 /* HSync */ + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 /* VSync */ + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 + >; + }; + }; + + ipu2 { + + pinctrl_ipu2_t1: ipu2grp-t1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xD1 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xD1 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xD1 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xF9 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xF9 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xF9 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xF9 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xF9 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xF9 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xF9 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xF9 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xF9 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xF9 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xF9 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xF9 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xF9 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xF9 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xF9 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xF9 + >; + }; + }; + + uart1 { + + pinctrl_uart1_t1: uart1grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart1_t2: uart1grp-t2 { /* Additional DTR, DSR, DCD */ + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + }; + + uart2 { + + pinctrl_uart2_t1: uart2grp-t1 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_t2: uart2grp-t2 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + }; + + uart4 { + pinctrl_uart4_t1: uart4grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_t1: uart5grp-t1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + pinctrl_uart5_t2: uart5grp-t2 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + >; + }; + }; + + usdhc1 { + + pinctrl_usdhc1_t1: usdhc1grp-t1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 + >; + }; + }; +}; + +&ldb { + ipu_id = <1>; + disp_id = <1>; + ext_ref = <1>; + mode = "spl1"; + sec_ipu_id = <1>; + sec_disp_id = <1>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_3>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2_2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_1>; + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_2>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; +#ifndef USE_UART_IN_DCE_MODE + pinctrl-0 = <&pinctrl_uart1_t1 &pinctrl_uart1_t2>; + fsl,dte-mode; + fsl,uart-has-rtscts; +#else + pinctrl-0 = <&pinctrl_uart1_1>; +#endif + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; +#ifndef USE_UART_IN_DCE_MODE + pinctrl-0 = <&pinctrl_uart2_t2>; + fsl,dte-mode; + fsl,uart-has-rtscts; +#else + pinctrl-0 = <&pinctrl_uart2_t1>; +#endif + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; +#ifndef USE_UART_IN_DCE_MODE + pinctrl-0 = <&pinctrl_uart4_t1>; + fsl,dte-mode; +#else + pinctrl-0 = <&pinctrl_uart4_1>; +#endif + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default"; +#ifndef USE_UART_IN_DCE_MODE + pinctrl-0 = <&pinctrl_uart5_t2>; + fsl,dte-mode; +#else + pinctrl-0 = <&pinctrl_uart5_t1>; +#endif + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_2>; + disable-over-current; + status = "disabled"; +}; + +/* MMC1 */ +&usdhc1 { + label = "MMC1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_t1 &pinctrl_mmc_cd>; + cd-gpios = <&gpio4 20 0>; + vmmc-supply = <®_3p3v>; + bus-width = <8>; + no-1-8-v; + status = "disabled"; +}; + +/* SD1 */ +&usdhc2 { + label = "SD1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2 &pinctrl_sd_cd>; + cd-gpios = <&gpio6 14 0>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + no-1-8-v; + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + vmmc-supply = <®_3p3v>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi new file mode 100644 index 000000000000..09f18cf54613 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -0,0 +1,801 @@ +/* + * Copyright 2014 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/input/input.h> + +/ { + model = "Toradex Colibri iMX6DL/S Module"; + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; + + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + status = "disabled"; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 pin 205/207 + */ + i2cddc: i2c@0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_ddc>; + gpios = <&gpio4 13 0 /* sda */ + &gpio4 12 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_t1>; + status = "disabled"; + }; + + memory { + /* This node is rewritten by U-Boot with the actual memory size */ + reg = <0x10000000 0x10000000>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + mode_str ="640x480M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="640x480M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_host_vbus: usb_host_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 0>; + status = "disabled"; + }; + }; + + sound { + compatible = "fsl,imx6-colibri-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-colibri-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <5>; + }; + + sound_hdmi: sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + status = "disabled"; + }; + + sound_spdif: sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + /* spdif-in; */ + status = "disabled"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_t1 &pinctrl_audmux_mclk_2 &pinctrl_mic_gnd>; + status = "okay"; +}; + +/* Colibri SPI */ +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio5 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_t1 &pinctrl_spi_cs1>; + status = "disabled"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_t1>; + phy-mode = "rmii"; + status = "okay"; +}; + +/* Colibri SDDIMM 55/63 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_t1>; + status = "disabled"; +}; + +/* Colibri SODOMM 178/188 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + status = "disabled"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "disabled"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int_1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + reg = <0>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + }; + }; +}; + +/* + * I2C: I2C3_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_2>; + status = "disabled"; +}; + +/* PAD Ctrl Values for Common Settings */ +#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/ +#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/ +#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/ +#define PAD_CTRL_IN 0x0040 /*( PAD_CTL_SPEED_LOW )*/ +#define PAD_CTRL_NO 0x80000000 + +&iomuxc { + audmux { + + pinctrl_audmux_t1: audmux-t1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 + >; + }; + }; + + csi { + /* CSI pins used as GPIO */ + pinctrl_csi_gpio_1: csi_gpio-1 { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 PAD_CTRL_HYS_PU + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_D18__GPIO3_IO18 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_A19__GPIO2_IO19 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_D29__GPIO3_IO29 PAD_CTRL_HYS_PD + MX6QDL_PAD_EIM_A23__GPIO6_IO06 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_A20__GPIO2_IO18 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_A17__GPIO2_IO21 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_A18__GPIO2_IO20 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_D17__GPIO3_IO17 PAD_CTRL_HYS_PU + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 PAD_CTRL_HYS_PU + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_t1: ecspi4grp-t1 { + fsl,pins = < + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + enet { + + pinctrl_enet_t1: enetgrp-t1 { /* RMII */ + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + >; + }; + }; + + flexcan1 { + + pinctrl_flexcan1_t1: flexcan1grp-t1 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 + >; + }; + }; + + gpio { + pinctrl_gpio_1: gpio-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_D27__GPIO3_IO27 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 PAD_CTRL_HYS_PU + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 PAD_CTRL_HYS_PU + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 PAD_CTRL_HYS_PU + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 PAD_CTRL_HYS_PU + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 PAD_CTRL_HYS_PU + >; + }; + pinctrl_gpio_2: gpio-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 PAD_CTRL_HYS_PU + MX6QDL_PAD_GPIO_8__GPIO1_IO08 PAD_CTRL_HYS_PU + >; + }; + }; + + imx6dl-colibri { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_reset_1>; + pinctrl_audmux_mclk_2: audmux_mclk-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + >; + }; + pinctrl_emmc_reset_1: emmc_reset-1 { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 PAD_CTRL_PU_22k /* eMMC reset, leave it alone */ + >; + }; + pinctrl_gpio_keys: gpio_keys { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 PAD_CTRL_HYS_PD /* Power Button */ + >; + }; + pinctrl_i2c_ddc: i2c_ddc { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 PAD_CTRL_HYS_PU /* DDC bitbang */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 PAD_CTRL_HYS_PU /* DDC bitbang */ + >; + }; + pinctrl_mic_gnd: gpio_mic_gnd { + fsl,pins = < + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 PAD_CTRL_HYS_PU /* Controlls Mic GND, PU or '1' pull Mic GND to GND */ + >; + }; + pinctrl_mmc_cd: gpio_mmc_cd { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 PAD_CTRL_NO /* MMC1 CD */ + >; + }; + pinctrl_pwm_a_cif_d7: pwm_d_cif_d7 { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 PAD_CTRL_IN /* disable, muxed with PWM<A> */ + >; + }; + pinctrl_pwm_d_cif_d6: pwm_d_cif_d6 { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 PAD_CTRL_IN /* disable, muxed with PWM<D> */ + >; + }; + pinctrl_regulator_usbh_pwr: gpio_regulator_usbh_pwr { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 PAD_CTRL_PU_22k /* USBH_EN */ + >; + }; +#if 0 //TODO + pinctrl_regulator_usbotg_pwr: gpio_regulator_usbotg_pwr { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 PAD_CTRL_PU_22k /* USBO power en */ + >; + }; +#endif + pinctrl_spi_cs1: spi_cs1 { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 PAD_CTRL_NO /* SPI cs */ + >; + }; + pinctrl_touch_int_1: touch_int-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 PAD_CTRL_HYS_PU /* STMPE811 interrupt */ + >; + }; + pinctrl_usbh_oc_1: usbh_oc-1 { + fsl,pins = < + /* USBH_OC */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 PAD_CTRL_HYS_PU + >; + }; + pinctrl_usbc_id_1: usbc_id-1 { + fsl,pins = < + /* USBC_ID */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 PAD_CTRL_HYS_PU + >; + }; + pinctrl_usbc_det_1: usbc_det-1 { + fsl,pins = < + /* USBC_DET */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 PAD_CTRL_HYS_PU + >; + }; + }; + + ipu1 { + + pinctrl_ipu1_t1: ipu1grp-t1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + >; + }; + }; + + spdif { + + pinctrl_spdif_t1: spdifgrp-t1 { + fsl,pins = < + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + + pinctrl_uart1_t1: uart1grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart1_t2: uart1grp-t2 { /* Additional DTR, DSR, DCD */ + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + }; + + uart2 { + + pinctrl_uart2_t1: uart2grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + }; + + uart3 { + + pinctrl_uart3_t1: uart3grp-t1 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + >; + }; + }; + + weim { + pinctrl_weim_cs1_1: weim_cs1grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 /* nEXT_CS1 */ + >; + }; + pinctrl_weim_cs2_1: weim_cs2grp-1 { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 /* nEXT_CS2 */ + >; + }; + pinctrl_weim_sram_1: weim_sramgrp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + /* data */ + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + /* address */ + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + pinctrl_weim_rdnwr_1: weim_rdnwr-1 { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 PAD_CTRL_IN + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 PAD_CTRL_HYS_PD + >; + }; + pinctrl_weim_npwe_1: weim_npwe-1 { + fsl,pins = < + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 PAD_CTRL_IN + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 PAD_CTRL_HYS_PD + >; + }; + + /* ADDRESS[17:18] [25] used as GPIO */ + pinctrl_weim_gpio_1: weim_gpio-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 PAD_CTRL_HYS_PU + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 PAD_CTRL_HYS_PU + >; + }; + /* ADDRESS[19:24] used as GPIO */ + pinctrl_weim_gpio_2: weim_gpio-2 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 PAD_CTRL_HYS_PU + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 PAD_CTRL_HYS_PU + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 PAD_CTRL_HYS_PU + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 PAD_CTRL_HYS_PU + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 PAD_CTRL_HYS_PU + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 PAD_CTRL_HYS_PU + >; + }; + /* DATA[16:29] [31] used as GPIO */ + pinctrl_weim_gpio_3: weim_gpio-3 { + fsl,pins = < + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 PAD_CTRL_HYS_PU + MX6QDL_PAD_GPIO_19__GPIO4_IO05 PAD_CTRL_HYS_PU + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 PAD_CTRL_HYS_PU + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 PAD_CTRL_HYS_PU + MX6QDL_PAD_GPIO_4__GPIO1_IO04 PAD_CTRL_HYS_PU + MX6QDL_PAD_GPIO_5__GPIO1_IO05 PAD_CTRL_HYS_PU + MX6QDL_PAD_GPIO_2__GPIO1_IO02 PAD_CTRL_HYS_PU + >; + }; + /* DQM[0:3] used as GPIO */ + pinctrl_weim_gpio_4: weim_gpio-4 { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 PAD_CTRL_HYS_PU + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 PAD_CTRL_HYS_PU + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 PAD_CTRL_HYS_PU + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 PAD_CTRL_HYS_PU + >; + }; + /* RDY used as GPIO */ + pinctrl_weim_gpio_5: weim_gpio-5 { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 PAD_CTRL_HYS_PU + >; + }; + /* ADDRESS[16] DATA[30] used as GPIO */ + pinctrl_weim_gpio_6: weim_gpio-6 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 PAD_CTRL_HYS_PU + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 PAD_CTRL_HYS_PU + >; + }; + }; +}; + +/* PWM B */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_3>; + status = "disabled"; +}; +/* PWM D */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2_2 &pinctrl_pwm_d_cif_d6>; + status = "disabled"; +}; +/* PWM A */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_1 &pinctrl_pwm_a_cif_d7>; + status = "disabled"; +}; +/* PWM C */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_1>; + status = "disabled"; +}; + +/* S/PDIF out on SODIMM137 */ +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_t1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +/* UART A */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_t1 &pinctrl_uart1_t1>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "disabled"; +}; + +/* UART B */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_t1>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "disabled"; +}; + +/* UART_C */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_t1>; + fsl,dte-mode; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; +// pinctrl-0 = <&pinctrl_usbotg_2>; + disable-over-current; +// dr_mode = "host"; //working when connected at boot + dr_mode = "otg"; //working as peripheral + status = "disabled"; +}; + +/* MMC */ +&usdhc1 { + label = "MMC1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_1 &pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 0>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + no-1-8-v; + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + vmmc-supply = <®_3p3v>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_sram_1 &pinctrl_weim_cs0_1 + &pinctrl_weim_cs1_1 &pinctrl_weim_cs2_1 + &pinctrl_weim_rdnwr_1 &pinctrl_weim_npwe_1>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi new file mode 100644 index 000000000000..88ec8783dd66 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -0,0 +1,448 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + brm_wifi_en: brm_wlan { + compatible = "regulator-fixed"; + regulator-name = "brm_wifi_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 7 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + home { + label = "Home"; + gpios = <&gpio7 13 0>; + linux,code = <102>; /* KEY_HOME */ + }; + + back { + label = "Back"; + gpios = <&gpio4 5 0>; + linux,code = <158>; /* KEY_BACK */ + }; + }; + + sound { + compatible = "fsl,imx6dl-nit6xlite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6dl-nit6xlite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + sound-hdmi { + compatible = "fsl,imx6dl-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_4>; + status = "okay"; + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wlan_bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "wlan_bt_rfkill"; + type = <2>; /* bluetooth */ + gpios = <&gpio6 15 0>, <&gpio6 8 0>; + }; + +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_4>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = <&gpio1 27 0>; +#endif + status = "okay"; + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec_2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_3>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + ft5x06_ts@38 { + compatible = "ft5x06-ts,ft5x06-ts"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + interrupt-parent = <&gpio2>; + interrupts = <27 2>; + wakeup-gpios = <&gpio2 27 0>; + }; + isl1208@6f { + compatible = "isl,isl1208"; + reg = <0x6f>; + interrupt-parent = <&gpio2>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* spi-nor CS */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* otg power en */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0 /* J14 pin 1 - GLED */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0 /* J14 pin 3 - RLED */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* J28 pin 7 - barcode scanner gpio */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0 /* J46 pin 2 - gp(inverted) */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 /* J46 pin 3 - gp(inverted) */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* J7 pin 4 - I2C3 irq */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* Broadcom slow clock */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0b0b0 /* ethernet phy reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 /* J10 pin 14 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* J10 pin 15 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 /* J10 pin 16 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* J10 pin 17 - Reserved(Broadcom) */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /* J10 pin 18 - Reserved(Broadcom) */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b0 /* RTC_IRQ - falling edge */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* tsc2004(I2C3) irq */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0b0b0 /* J14 pin 8/9(dry contact) */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0b0b0 /* J14 pin 7 - back button */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0 /* tsc2004(I2C3) *reset */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0b0b0 /* 12v Supply Enable, high active */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* SGTL5000 amp enable, high active */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 /* Wifi reg en(Broadcom) */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b0 /* BT reset(Broadcom) */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* Clk req irq(Broadcom) */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* wake output(Broadcom) */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0 /* BT reg en(Broadcom) */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b0 /* BT host wake irq(Broadcom) */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* USDHC3 CD */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* J6 pin 19 - LVDS gp */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 /* J14 pin 5 - home button */ + >; + }; + }; +}; + +&ldb { + ipu_id = <0>; + disp_id = <1>; + ext_ref = <1>; + mode = "sin0"; + sec_ipu_id = <1>; + sec_disp_id = <1>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&brm_wifi_en>; + ocr-limit = <0x180>; /* 1.65v - 2.1v */ + power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi new file mode 100644 index 000000000000..42aa3ce9d620 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -0,0 +1,734 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/input/input.h> + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + wilink_wl_en: tiwi_wlan { + compatible = "regulator-fixed"; + regulator-name = "wilink_wl_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 15 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + power { + label = "Power Button"; + gpios = <&gpio2 3 0>; + linux,code = <KEY_POWER>; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 0>; + linux,code = <KEY_MENU>; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 0>; + linux,code = <KEY_HOME>; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 0>; + linux,code = <KEY_BACK>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 0>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio7 1 0>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6_max-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_4>; +#if 0 + status = "okay"; +#endif + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + backlight_lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + backlight_lvds1 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wlan { + compatible = "ti,wilink6"; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclock>; + clock-names = "refclock"; + + refclock: refclock { + compatible = "ti,wilink-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + }; + + wlan_bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "wlan_bt_rfkill"; + type = <2>; /* bluetooth */ + gpios = <&gpio6 16 0>; + }; + + i2cmux@2 { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio3 20 0>, <&gpio4 15 0>; + i2c-parent = <&i2c2>; + idle-state = <0>; + + i2c2@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2a: i2c2@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2b: i2c2@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2cmux@3 { + compatible = "i2c-mux-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3mux>; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio2 25 0>; + i2c-parent = <&i2c3>; + idle-state = <0>; + + i2c3@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3a: i2c3@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3b: i2c3@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_4>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = <&gpio1 27 0>; + status = "okay"; +#endif + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-stby-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec_2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + rv4162@68 { + compatible = "mcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&i2c2a { + ov5642: ov5642@3d { + compatible = "ovti,ov5642"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio3 29 1>; + rst-gpios = <&gpio1 4 0>; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; +}; + +&i2c2b { + ov5640_mipi: ov5640_mipi@3e { + compatible = "ovti,ov5640_mipi"; + reg = <0x3e>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio6 9 1>; + rst-gpios = <&gpio2 5 0>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_3>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts,ft5x06-ts"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640 &pinctrl_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio3 13 1>; + rst-gpios = <&gpio3 14 0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; + + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = <20 2>; + wakeup-gpios = <&gpio4 20 0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx6q-nitrogen6_max { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* spi-nor CS */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* otg power en */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 /* ethernet phy reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* USDHC3 CD */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN standby */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* I2C3 touch screen interrupt */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* ov5640 mipi powerdown */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 /* ov5640 mipi reset */ + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* ov5642 mclk */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0 /* ov5642 Power Down */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x000b0 /* ov5642 Reset */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 /* wl12xx_wl_irq */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 /* wl12xx_wl_en */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 /* wl12xx_bt_en */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* rv4162 rtc interrupt */ + >; + }; + + pinctrl_ov5640: pinctrl_ov5640 { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_ov5640_gpios: pinctrl_ov5640_gpios { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 /* Power */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* Reset */ + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x030b0 /* RS485 RX Enable */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0 /* RS485 TX Enable */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b0 /* RS485/RS232 Select 2.5V */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b0 /* ON - meaning depends on others */ + >; + }; + + pinctrl_i2c2mux: i2c2muxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 /* ov5642 camera i2c enable */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 /* ov5640_mipi camera i2c enable */ + >; + }; + pinctrl_i2c3mux: i2c3muxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 /* pcie i2c enable */ + >; + }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 /* pcie reset */ + >; + }; + }; +}; + +&ldb { + ipu_id = <0>; + disp_id = <1>; + ext_ref = <1>; + mode = "sin0"; + sec_ipu_id = <1>; + sec_disp_id = <1>; + status = "okay"; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2_3>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&wilink_wl_en>; + vqmmc-1-8-v; + ocr-limit = <0x80>; /* 1.65v - 1.95v */ + power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + bus-width = <4>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_3p3v>; + ocr-limit = <0x80>; /* 1.65v - 1.95v */ + keep-power-in-suspend; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_mtp.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_mtp.dtsi new file mode 100644 index 000000000000..abfb5060d71f --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_mtp.dtsi @@ -0,0 +1,634 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/input/input.h> + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + wilink_wl_en: tiwi_wlan { + compatible = "regulator-fixed"; + regulator-name = "wilink_wl_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 15 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + power { + label = "Power Button"; + gpios = <&gpio2 3 0>; + linux,code = <KEY_POWER>; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 0>; + linux,code = <KEY_MENU>; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 0>; + linux,code = <KEY_HOME>; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 0>; + linux,code = <KEY_BACK>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 0>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 0>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6_mtp-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6_mtp-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_4>; +#if 0 + status = "okay"; +#endif + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wlan { + compatible = "ti,wilink6"; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclock>; + clock-names = "refclock"; + + refclock: refclock { + compatible = "ti,wilink-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + }; + + wlan_bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "wlan_bt_rfkill"; + type = <2>; /* bluetooth */ + gpios = <&gpio6 16 0>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_4>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = <&gpio1 27 0>; +#endif + status = "okay"; + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec_2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + isl1208@6f { + compatible = "isl,isl1208"; + reg = <0x6f>; + interrupt-parent = <&gpio6>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio6 9 1>; + rst-gpios = <&gpio2 5 0>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_3>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts,ft5x06-ts"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640 &pinctrl_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio3 13 1>; + rst-gpios = <&gpio3 14 0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; + + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = <20 2>; + wakeup-gpios = <&gpio4 20 0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx6q-nitrogen6_mtp { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* spi-nor CS */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* otg power en */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 /* ethernet phy reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* USDHC3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* Spare */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* uSDHC4 CD */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* Spare */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN standby */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* Spare */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* I2C3 touch screen interrupt */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* ov5640 mipi powerdown */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 /* ov5640 mipi reset */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 /* ov5642 Power Down */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 /* ov5642 Reset */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 /* wl12xx_wl_irq */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 /* wl12xx_wl_en */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 /* wl12xx_bt_en */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* ISL1208 interrupt */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + >; + }; + + pinctrl_ov5640: pinctrl_ov5640 { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_ov5640_gpios: pinctrl_ov5640_gpios { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 /* Power */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* Reset */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x030b1 + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x130b1 + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x030b1 + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x130b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x030b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x130b1 + MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x030b1 + MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x130b1 + >; + }; + }; +}; + +&ldb { + ipu_id = <0>; + disp_id = <1>; + ext_ref = <1>; + mode = "sin0"; + sec_ipu_id = <1>; + sec_disp_id = <1>; + status = "okay"; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&wilink_wl_en>; + ocr-limit = <0x80>; /* 1.65v - 1.95v */ + power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_2>; + cd-gpios = <&gpio2 6 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi new file mode 100644 index 000000000000..3262b521a869 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -0,0 +1,667 @@ +/* + * Copyright 2013 Boundary Devices + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/input/input.h> + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + wilink_wl_en: tiwi_wlan { + compatible = "regulator-fixed"; + regulator-name = "wilink_wl_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 15 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + power { + label = "Power Button"; + gpios = <&gpio2 3 0>; + linux,code = <KEY_POWER>; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 0>; + linux,code = <KEY_MENU>; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 0>; + linux,code = <KEY_HOME>; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 0>; + linux,code = <KEY_BACK>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 0>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 0>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + sound { + compatible = "fsl,imx6q-nitrogen6x-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-nitrogen6x-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; +#if 0 + disp_dev = "mipi_dsi"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#else + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#endif + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_4>; +#if 0 + status = "okay"; +#endif + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + + wlan { + compatible = "ti,wilink6"; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&refclock>; + clock-names = "refclock"; + + refclock: refclock { + compatible = "ti,wilink-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + }; + + wlan_bt_rfkill { + compatible = "net,rfkill-gpio"; + name = "wlan_bt_rfkill"; + type = <2>; /* bluetooth */ + gpios = <&gpio6 16 0>; + }; + +#if 0 + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + #reset-cells = <0>; + }; +#endif +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_4>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = <&gpio1 27 0>; +#endif + status = "okay"; + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-stby-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec_2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + isl1208@6f { + compatible = "isl,isl1208"; + reg = <0x6f>; + interrupt-parent = <&gpio6>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5642: ov5642@3d { + compatible = "ovti,ov5642"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio1 6 1>; + rst-gpios = <&gpio1 8 0>; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; + + ov5640_mipi: ov5640_mipi@3e { + compatible = "ovti,ov5640_mipi"; + reg = <0x3e>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio6 9 1>; + rst-gpios = <&gpio2 5 0>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45>; + }; + + tc358743_mipi: tc358743_mipi@0f { + compatible = "tc358743_mipi"; + reg = <0x0f>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + rst-gpios = <&gpio6 9 1>; + interrupt-parent = <&gpio2>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + ipu_id = <0>; + csi_id = <0>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_3>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts,ft5x06-ts"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640 &pinctrl_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio3 13 1>; + rst-gpios = <&gpio3 14 0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; + + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = <20 2>; + wakeup-gpios = <&gpio4 20 0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx6q-nitrogen6x { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* spi-nor CS */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* otg power en */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 /* ethernet phy reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* USDHC3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* Spare */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* uSDHC4 CD */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* Spare */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN standby */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* Spare */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* I2C3 touch screen interrupt */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* ov5640 mipi powerdown */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 /* ov5640 mipi reset */ + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* ov5642 mclk */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 /* ov5642 Power Down */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 /* ov5642 Reset */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x100b0 /* wl12xx_wl_irq */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 /* wl12xx_wl_en */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 /* wl12xx_bt_en */ + MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 /* TiWi slow clock */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 /* ISL1208 interrupt */ + >; + }; + + pinctrl_ov5640: pinctrl_ov5640 { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_ov5640_gpios: pinctrl_ov5640_gpios { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 /* Power */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* Reset */ + >; + }; + }; +}; + +&ldb { + ipu_id = <0>; + disp_id = <1>; + ext_ref = <1>; + mode = "sin0"; + sec_ipu_id = <1>; + sec_disp_id = <1>; + status = "okay"; +}; + +#if 0 +&mipi_dsi { + dev_id = <0>; + disp_id = <0>; + lcd_panel = "hitachi-1080p"; + disp-power-on-supply = <®_3p3v>; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; +#endif + +&mipi_csi { + ipu_id = <0>; + csi_id = <0>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { /* uSDHC2, TiWi wl1271 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&wilink_wl_en>; + ocr-limit = <0x80>; /* 1.65v - 1.95v */ + power-off-card; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + cd-gpios = <&gpio7 0 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_2>; + cd-gpios = <&gpio2 6 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi new file mode 100644 index 000000000000..4f83104ba1f4 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -0,0 +1,587 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/input/input.h> + +/ { + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + memory { + reg = <0x10000000 0x40000000>; + }; + + clocks { + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_1p8v: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + power { + label = "Power Button"; + gpios = <&gpio2 3 0>; + linux,code = <KEY_POWER>; /* or KEY_SEARCH */ + gpio-key,wakeup; + }; + + menu { + label = "Menu"; + gpios = <&gpio2 1 0>; + linux,code = <KEY_MENU>; + }; + + home { + label = "Home"; + gpios = <&gpio2 4 0>; + linux,code = <KEY_HOME>; + }; + + back { + label = "Back"; + gpios = <&gpio2 2 0>; + linux,code = <KEY_BACK>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio7 13 0>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio4 5 0>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + sound { + compatible = "fsl,imx6q-sabrelite-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6q-sabrelite-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; +#if 0 + disp_dev = "mipi_dsi"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#else + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; +#endif + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_4>; +#if 0 + status = "okay"; +#endif + }; + + backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2: v4l2_cap_2 { + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; + +#if 0 + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + #reset-cells = <0>; + }; +#endif +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "sst,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0xC0000>; + read-only; + }; + partition@C0000 { + label = "env"; + reg = <0xC0000 0x2000>; + read-only; + }; + partition@C2000 { + label = "Kernel"; + reg = <0xC2000 0x13e000>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_4>; + phy-mode = "rgmii"; +#if 0 + phy-reset-gpios = <&gpio3 23 0>; +#endif + status = "okay"; + + #address-cells = <0>; + #size-cells = <1>; + phy_int { + reg = <0x6>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-stby-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec_2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + hdmi: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov5642: ov5642@3d { + compatible = "ovti,ov5642"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio1 6 1>; + rst-gpios = <&gpio1 8 0>; + ipu_id = <0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; + + ov5640_mipi: ov5640_mipi@3e { + compatible = "ovti,ov5640_mipi"; + reg = <0x3e>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio6 9 1>; + rst-gpios = <&gpio2 5 0>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_3>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ft5x06_ts@38 { + compatible = "ft5x06-ts,ft5x06-ts"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <9 2>; + wakeup-gpios = <&gpio1 9 0>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640 &pinctrl_ov5640_gpios>; + clocks = <&clk24m 0>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio3 13 1>; + rst-gpios = <&gpio3 14 0>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; + + tsc2004@48 { + compatible = "tsc2004,tsc2004"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = <20 2>; + wakeup-gpios = <&gpio4 20 0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx6q-sabrelite { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* Power Button */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + /* Menu Button */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + /* Home Button */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + /* Back Button */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + /* Volume Up Button */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* Volume Down Button */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* spi-nor CS */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* otg power en */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* ethernet phy reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* ethernet phy interrupt */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* USDHC3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* USDHC3 WP */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* uSDHC4 CD */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* Spare */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN standby */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* CAN enable */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* I2C3 touch screen interrupt */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* tsc2004 interrupt */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0 /* ov5640 mipi powerdown */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0 /* ov5640 mipi reset */ + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 /* ov5642 mclk */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x000b0 /* ov5642 Power Down */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x000b0 /* ov5642 Reset */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 /* USB Hub Reset */ + >; + }; + + pinctrl_ov5640: pinctrl_ov5640 { + /* parallel camera on CSI1, pins differ for iMX6Q/iMX6DL */ + }; + + pinctrl_ov5640_gpios: pinctrl_ov5640_gpios { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x0b0b0 /* Power */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x030b0 /* Reset */ + >; + }; + }; +}; + +&ldb { + ipu_id = <0>; + disp_id = <1>; + ext_ref = <1>; + mode = "sin0"; + sec_ipu_id = <1>; + sec_disp_id = <1>; + status = "okay"; +}; + +#if 0 +&mipi_dsi { + dev_id = <0>; + disp_id = <0>; + lcd_panel = "hitachi-1080p"; + disp-power-on-supply = <®_3p3v>; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; +#endif + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_2>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_2>; + cd-gpios = <&gpio2 6 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2cb5ae0294e6..2e9879f2b65f 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1168,6 +1168,27 @@ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 >; }; + + pinctrl_enet_4: enetgrp-4 { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + }; esai { @@ -1431,6 +1452,40 @@ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 >; }; + + pinctrl_ipu1_4: ipu1grp-4 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + }; mlb { @@ -1457,6 +1512,34 @@ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 >; }; + pinctrl_pwm1_2: pwm1grp-2 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + pinctrl_pwm1_3: pwm1grp-3 { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + }; + + pwm2 { + pinctrl_pwm2_1: pwm2grp-1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + pinctrl_pwm2_2: pwm2grp-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + pinctrl_pwm2_3: pwm2grp-3 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; }; pwm3 { @@ -1465,6 +1548,24 @@ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 >; }; + pinctrl_pwm3_2: pwm3grp-2 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_1: pwm4grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_pwm4_2: pwm4grp-2 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; }; spdif { @@ -1489,6 +1590,13 @@ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 >; }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; }; uart2 { @@ -1518,6 +1626,14 @@ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 >; }; + pinctrl_uart3_2: uart3grp-2 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; }; uart4 { diff --git a/arch/arm/configs/apalis_imx6_android_defconfig b/arch/arm/configs/apalis_imx6_android_defconfig new file mode 100644 index 000000000000..a0769007aed2 --- /dev/null +++ b/arch/arm/configs/apalis_imx6_android_defconfig @@ -0,0 +1,4264 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.10.17 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +CONFIG_KERNEL_LZO=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_FHANDLE=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +CONFIG_UIDGID_CONVERTED=y +CONFIG_UIDGID_STRICT_TYPE_CHECKS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_MM_OWNER=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_HOTPLUG=y +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_THROTTLING is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_CFQ_GROUP_IOSCHED is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +CONFIG_ARCH_MXC=y + +# +# Freescale i.MX support +# +# CONFIG_MXC_IRQ_PRIOR is not set +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_HAVE_IMX_RNG=y +CONFIG_HAVE_IMX_ANATOP=y +CONFIG_HAVE_IMX_GPC=y +CONFIG_HAVE_IMX_MMDC=y +CONFIG_HAVE_IMX_SRC=y + +# +# i.MX51 machines: +# +# CONFIG_MACH_IMX51_DT is not set +# CONFIG_MACH_MX51_BABBAGE is not set +# CONFIG_MACH_EUKREA_CPUIMX51SD is not set + +# +# Device tree only +# +# CONFIG_SOC_IMX53 is not set +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +# CONFIG_SOC_VF610 is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +CONFIG_PL310_ERRATA_727915=y +CONFIG_ARM_ERRATA_794072=y +CONFIG_ARM_ERRATA_761320=y +# CONFIG_PL310_ERRATA_753970 is not set +CONFIG_ARM_ERRATA_754322=y +# CONFIG_ARM_ERRATA_754327 is not set +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +CONFIG_PCIE_DW=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_FORCE_GEN1=y +# CONFIG_EP_MODE_IN_EP_RC_SYS is not set +CONFIG_RC_MODE_IN_EP_RC_SYS=y +CONFIG_PCI_IMX_EP_DRV=y +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_SECCOMP=y +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +# CONFIG_GENERIC_CPUFREQ_CPU0 is not set + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set +# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set +# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set +# CONFIG_ARM_EXYNOS5440_CPUFREQ is not set +CONFIG_ARM_IMX6_CPUFREQ=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_PM_TEST_SUSPEND=y +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_UDP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_GRE=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_NETLINK_ACCT=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_BROADCAST=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_QUEUE_CT=y +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_PROTO_DCCP=y +CONFIG_NF_NAT_PROTO_UDPLITE=y +CONFIG_NF_NAT_PROTO_SCTP=y +CONFIG_NF_NAT_AMANDA=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=y +CONFIG_NF_NAT_SIP=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_SET=y + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set +CONFIG_NETFILTER_XT_TARGET_CT=y +CONFIG_NETFILTER_XT_TARGET_DSCP=y +CONFIG_NETFILTER_XT_TARGET_HL=y +CONFIG_NETFILTER_XT_TARGET_HMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NETMAP=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_RATEEST=y +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_BPF=y +CONFIG_NETFILTER_XT_MATCH_CLUSTER=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_CPU=y +CONFIG_NETFILTER_XT_MATCH_DCCP=y +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ECN=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_HL=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_NFACCT=y +CONFIG_NETFILTER_XT_MATCH_OSF=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_RATEEST=y +CONFIG_NETFILTER_XT_MATCH_REALM=y +CONFIG_NETFILTER_XT_MATCH_RECENT=y +CONFIG_NETFILTER_XT_MATCH_SCTP=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_SET=y +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=y +CONFIG_IP_SET_BITMAP_IPMAC=y +CONFIG_IP_SET_BITMAP_PORT=y +CONFIG_IP_SET_HASH_IP=y +CONFIG_IP_SET_HASH_IPPORT=y +CONFIG_IP_SET_HASH_IPPORTIP=y +CONFIG_IP_SET_HASH_IPPORTNET=y +CONFIG_IP_SET_HASH_NET=y +CONFIG_IP_SET_HASH_NETPORT=y +CONFIG_IP_SET_HASH_NETIFACE=y +CONFIG_IP_SET_LIST_SET=y +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT_IPV4=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_NF_NAT_SNMP_BASIC=y +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_CLUSTERIP=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_EUI64=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_TARGET_HL=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_NF_NAT_IPV6=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_TARGET_NPT=y +CONFIG_IP_DCCP=y +CONFIG_INET_DCCP_DIAG=y + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=y +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_HFSC=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_RED=y +CONFIG_NET_SCH_SFB=y +CONFIG_NET_SCH_SFQ=y +CONFIG_NET_SCH_TEQL=y +CONFIG_NET_SCH_TBF=y +CONFIG_NET_SCH_GRED=y +CONFIG_NET_SCH_DSMARK=y +CONFIG_NET_SCH_NETEM=y +CONFIG_NET_SCH_DRR=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_SCH_CHOKE=y +CONFIG_NET_SCH_QFQ=y +CONFIG_NET_SCH_CODEL=y +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_INGRESS is not set +CONFIG_NET_SCH_PLUG=y + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_NET_CLS_ROUTE4=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=y +CONFIG_NET_CLS_RSVP6=y +CONFIG_NET_CLS_FLOW=y +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_EMATCH_CANID=y +CONFIG_NET_EMATCH_IPSET=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_IPT=y +CONFIG_NET_ACT_NAT=y +CONFIG_NET_ACT_PEDIT=y +CONFIG_NET_ACT_SIMP=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_CSUM=y +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NETPRIO_CGROUP=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y +CONFIG_CAN_GW=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +# CONFIG_CAN_SLCAN is not set +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_LEDS is not set +# CONFIG_CAN_AT91 is not set +# CONFIG_CAN_MCP251X is not set +CONFIG_HAVE_CAN_FLEXCAN=y +CONFIG_CAN_FLEXCAN=y +# CONFIG_PCH_CAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_C_CAN is not set +# CONFIG_CAN_CC770 is not set + +# +# CAN USB interfaces +# +# CONFIG_CAN_EMS_USB is not set +# CONFIG_CAN_ESD_USB2 is not set +# CONFIG_CAN_KVASER_USB is not set +# CONFIG_CAN_PEAK_USB is not set +# CONFIG_CAN_8DEV_USB is not set +# CONFIG_CAN_SOFTING is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=m +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +# CONFIG_CFG80211_WEXT is not set +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +CONFIG_RFKILL_GPIO=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 + +# +# Bus devices +# +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI is not set +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_SX4 is not set +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_HIGHBANK is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARASAN_CF is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CS5536 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +CONFIG_PATA_IMX=y +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +CONFIG_MII=y +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_3COM=y +# CONFIG_VORTEX is not set +# CONFIG_TYPHOON is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +# CONFIG_PCNET32 is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +# CONFIG_NET_TULIP is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EXAR=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_FEC=y +CONFIG_NET_VENDOR_HP=y +# CONFIG_HP100 is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_NET_VENDOR_NVIDIA=y +# CONFIG_FORCEDETH is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_PCH_GBE is not set +# CONFIG_ETHOC is not set +CONFIG_NET_PACKET_ENGINE=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_NETXEN_NIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R8169 is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +CONFIG_MICREL_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPPOE is not set +# CONFIG_PPTP is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=y +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=y +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET=y +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=y +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +# CONFIG_ATH_CARDS is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +# CONFIG_LIBERTAS is not set +# CONFIG_P54_COMMON is not set +CONFIG_RT2X00=m +# CONFIG_RT2400PCI is not set +# CONFIG_RT2500PCI is not set +# CONFIG_RT61PCI is not set +# CONFIG_RT2800PCI is not set +# CONFIG_RT2500USB is not set +# CONFIG_RT73USB is not set +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +# CONFIG_RT2800USB_RT53XX is not set +# CONFIG_RT2800USB_RT55XX is not set +# CONFIG_RT2800USB_UNKNOWN is not set +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +# CONFIG_RTLWIFI is not set +# CONFIG_WL_TI is not set +# CONFIG_ZD1211RW is not set +# CONFIG_MWIFIEX is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set +CONFIG_INPUT_MATRIXKMAP=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +CONFIG_KEYBOARD_IMX=y +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_STMPE is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AR1020_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_FT5X06 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_ISL29023 is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_FSL_OTP is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_IMX_RNG is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_MXS_VIIM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_IMX=y +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set + +# +# Qualcomm MSM SSBI bus support +# +# CONFIG_SSBI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# CONFIG_PTP_1588_CLOCK_PCH is not set +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_IMX=y +CONFIG_PINCTRL_IMX6Q=y +CONFIG_PINCTRL_IMX6SL=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_EXYNOS is not set +# CONFIG_PINCTRL_EXYNOS5440 is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +CONFIG_GPIO_MXC=y +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_STMPE is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_IMX6_USB_CHARGER is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX17135 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_MAG3110=y +CONFIG_MXC_MMA8451=y +CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_CPU_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MPCORE_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_IMX2_WDT=y +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +CONFIG_MFD_MXC_HDMI=y +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX17135 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +CONFIG_MFD_STMPE=y + +# +# STMicroelectronics STMPE Interface Drivers +# +CONFIG_STMPE_I2C=y +# CONFIG_STMPE_SPI is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_FAN53555 is not set +CONFIG_REGULATOR_ANATOP=y +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEO_V4L2_INT_DEVICE=m +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_USB_SN9C102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_TIMBERDALE is not set +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +# CONFIG_MXC_HDMI_CSI2_TC358743 is not set +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_MXC_IPU_PRP_ENC=m +CONFIG_MXC_IPU_CSI_ENC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +CONFIG_SOC_CAMERA=y +# CONFIG_SOC_CAMERA_PLATFORM is not set +# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SR030PC30 is not set + +# +# Flash devices +# + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set + +# +# Sensors used on soc_camera driver +# + +# +# soc_camera sensor drivers +# +# CONFIG_SOC_CAMERA_IMX074 is not set +# CONFIG_SOC_CAMERA_MT9M001 is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9T112 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_OV2640 is not set +# CONFIG_SOC_CAMERA_OV5642 is not set +# CONFIG_SOC_CAMERA_OV6650 is not set +# CONFIG_SOC_CAMERA_OV772X is not set +# CONFIG_SOC_CAMERA_OV9640 is not set +# CONFIG_SOC_CAMERA_OV9740 is not set +# CONFIG_SOC_CAMERA_RJ54N1 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set + +# +# Customise DVB Frontends +# +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +CONFIG_DRM_VIVANTE=y +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_TILCDC is not set +# CONFIG_DRM_QXL is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +CONFIG_FB_MXS=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXC_EDID=y +CONFIG_FB_MXC_EINK_PANEL=y +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set +CONFIG_FB_MXS_SII902X=y +CONFIG_HANNSTAR_CABC=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_FB_SSD1307 is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_DMAENGINE_PCM=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_SOC_FSL_SSI=y +CONFIG_SND_SOC_FSL_ASRC=y +CONFIG_SND_SOC_FSL_SPDIF=y +CONFIG_SND_SOC_FSL_HDMI=y +CONFIG_SND_SOC_FSL_UTILS=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_PCM_DMA=y +CONFIG_SND_SOC_IMX_HDMI_DMA=y +CONFIG_SND_SOC_IMX_AUDMUX=y +# CONFIG_SND_SOC_IMX_CS42888 is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +# CONFIG_SND_SOC_IMX_SI476X is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_OMAP_HDMI_CODEC=y +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SOC_SPDIF=y +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SOUND_PRIME is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PS3REMOTE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_MXC is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_IMX21_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +# CONFIG_USB_CHIPIDEA_DEBUG is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=y +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +CONFIG_USB_SERIAL_QUALCOMM=y +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_ZTE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_SAMSUNG_USBPHY is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_USB_MXS_PHY=y +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_ULPI is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +# CONFIG_USB_FSL_USB2 is not set +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_MASS_STORAGE=m +# CONFIG_FSL_UTP is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y + +# +# MXC Vivante GPU support +# +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_IPU_V3=y + +# +# MXC Asynchronous Sample Rate Converter support +# +CONFIG_MXC_ASRC=y + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set +# CONFIG_MX6_VPU_352M is not set + +# +# MXC HDMI CEC (Consumer Electronics Control) support +# +# CONFIG_MXC_HDMI_CEC is not set + +# +# MXC MIPI Support +# +CONFIG_MXC_MIPI_CSI2=y + +# +# MXC Media Local Bus Driver +# +CONFIG_MXC_MLB=y +CONFIG_MXC_MLB150=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=y +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_BLINKM is not set + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RV4162 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +CONFIG_RTC_DRV_SNVS=y + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_DW_DMAC is not set +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +# CONFIG_TIMB_DMA is not set +CONFIG_IMX_SDMA=y +# CONFIG_IMX_DMA is not set +# CONFIG_MXS_DMA is not set +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_ET131X is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_W35UND is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_R8187SE is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_DX_SEP is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_LIS3L02DQ is not set + +# +# Analog to digital converters +# +# CONFIG_AD7291 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD799X is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set +CONFIG_STMPE_ADC=y + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD5930 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16260 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Light sensors +# +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_HMC5843 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set + +# +# Triggers - standalone +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_FB_XGI is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_TIMED_OUTPUT=y +# CONFIG_ANDROID_TIMED_GPIO is not set +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_INTF_ALARM_DEV=y +CONFIG_SYNC=y +CONFIG_SW_SYNC=y +CONFIG_SW_SYNC_USER=y +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_WIMAX_GDM72XX is not set +CONFIG_NET_VENDOR_SILICOM=y +# CONFIG_SBYPASS is not set +# CONFIG_BPCTL is not set +# CONFIG_CED1401 is not set +# CONFIG_DRM_IMX is not set +# CONFIG_DGRP is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_COMMON_CLK_SI5351 is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +CONFIG_IIO=y +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set + +# +# Accelerometers +# +# CONFIG_KXSD9 is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set + +# +# Analog to digital converters +# +# CONFIG_AD7266 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7887 is not set +# CONFIG_EXYNOS_ADC is not set +# CONFIG_MAX1363 is not set +# CONFIG_TI_ADC081C is not set + +# +# Amplifiers +# +# CONFIG_AD8366 is not set + +# +# Hid Sensor IIO Common +# + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5686 is not set +# CONFIG_MAX517 is not set +# CONFIG_MCP4725 is not set + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_INV_MPU6050_IIO is not set + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_VCNL4000 is not set + +# +# Magnetometer sensors +# +# CONFIG_AK8975 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_CPU_STALL_VERBOSE=y +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_IMX_UART_PORT=1 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA1_ARM is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_BLOWFISH_COMMON=y +CONFIG_CRYPTO_CAMELLIA=y +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_STMP_DEVICE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=y +CONFIG_TEXTSEARCH_BM=y +CONFIG_TEXTSEARCH_FSM=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_OID_REGISTRY=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/apalis_imx6_defconfig b/arch/arm/configs/apalis_imx6_defconfig new file mode 100644 index 000000000000..de535c174f32 --- /dev/null +++ b/arch/arm/configs/apalis_imx6_defconfig @@ -0,0 +1,363 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_FORCE_GEN1=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_CAN=y +CONFIG_CAN_VCAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_UBI=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_USB_USBNET=y +CONFIG_RT2X00=m +CONFIG_RT2800USB=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_V4L2_INT_DEVICE=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_HIDRAW=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_ASRC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_MLB150=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +CONFIG_STMPE_ADC=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/colibri_imx6_defconfig b/arch/arm/configs/colibri_imx6_defconfig new file mode 100644 index 000000000000..d9410354be36 --- /dev/null +++ b/arch/arm/configs/colibri_imx6_defconfig @@ -0,0 +1,354 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_CAN=y +CONFIG_CAN_VCAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_PERCENTAGE=50 +CONFIG_CMA_SIZE_SEL_MIN=y +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_UBI=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_USB_USBNET=y +CONFIG_RT2X00=m +CONFIG_RT2800USB=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_V4L2_INT_DEVICE=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_HIDRAW=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_QUALCOMM=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_ASRC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_MLB150=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +CONFIG_STMPE_ADC=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/nit6xlite_defconfig b/arch/arm/configs/nit6xlite_defconfig new file mode 100644 index 000000000000..72f64aab7f62 --- /dev/null +++ b/arch/arm/configs/nit6xlite_defconfig @@ -0,0 +1,302 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_BRCMFMAC=m +CONFIG_IWLWIFI=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_V4L2_INT_DEVICE=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_ASRC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/nitrogen6x_defconfig b/arch/arm/configs/nitrogen6x_defconfig new file mode 100644 index 000000000000..5f611ca241e4 --- /dev/null +++ b/arch/arm/configs/nitrogen6x_defconfig @@ -0,0 +1,315 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_IWLWIFI=m +CONFIG_WL_TI=y +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_V4L2_INT_DEVICE=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_ASRC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/configs/nitrogen6x_ub_defconfig b/arch/arm/configs/nitrogen6x_ub_defconfig new file mode 100644 index 000000000000..cad8a2c238d6 --- /dev/null +++ b/arch/arm/configs/nitrogen6x_ub_defconfig @@ -0,0 +1,328 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_SECCOMP=y +CONFIG_CC_STACKPROTECTOR=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_IWLWIFI=m +CONFIG_WL_TI=y +CONFIG_WL12XX=m +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_V4L2_INT_DEVICE=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_ASRC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_SECURITY=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 25e987cd2337..d8b9dd14d0b3 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -432,7 +432,7 @@ static struct regulator_desc pu_dummy_desc = { static int pu_dummy_probe(struct platform_device *pdev) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int ret; config.dev = &pdev->dev; diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 5fb11af5643d..013129eb137c 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -198,7 +198,7 @@ static void __init imx6q_1588_init(void) IMX6Q_GPR1_ENET_CLK_SEL_MASK, IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); else - pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); } @@ -357,17 +357,23 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) */ val = readl_relaxed(base + OCOTP_CFG3); val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 3; if (cpu_is_imx6q()) { - if ((val & 0x3) < OCOTP_CFG3_SPEED_1P2GHZ) + if (!val) { + /* fuses not set for IMX_CHIP_REVISION_1_0 */ + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) + val = OCOTP_CFG3_SPEED_1GHZ; + } + if (val < OCOTP_CFG3_SPEED_1P2GHZ) if (opp_disable(cpu_dev, 1200000000)) pr_warn("failed to disable 1.2 GHz OPP\n"); } - if ((val & 0x3) < OCOTP_CFG3_SPEED_1GHZ) + if (val < OCOTP_CFG3_SPEED_1GHZ) if (opp_disable(cpu_dev, 996000000)) pr_warn("failed to disable 1 GHz OPP\n"); if (cpu_is_imx6q()) { - if ((val & 0x3) < OCOTP_CFG3_SPEED_850MHZ || - (val & 0x3) == OCOTP_CFG3_SPEED_1GHZ) + if (val < OCOTP_CFG3_SPEED_850MHZ || + val == OCOTP_CFG3_SPEED_1GHZ) if (opp_disable(cpu_dev, 852000000)) pr_warn("failed to disable 850 MHz OPP\n"); } @@ -424,6 +430,8 @@ static struct platform_device imx6q_cpufreq_pdev = { .name = "imx6-cpufreq", }; +extern unsigned int system_rev; + static void __init imx6q_init_late(void) { struct regmap *gpr; @@ -438,6 +446,15 @@ static void __init imx6q_init_late(void) IMX6Q_GPR1_GINT_MASK, IMX6Q_GPR1_GINT_ASSERT); + if (!system_rev) { + if (cpu_is_imx6q()) + system_rev = 0x63000; + else if (cpu_is_imx6dl()) + system_rev = 0x61000; + else if (cpu_is_imx6sl()) + system_rev = 0x60000; + system_rev |= imx_get_soc_revision(); + } /* * WAIT mode is broken on TO 1.0 and 1.1, so there is no point * to run cpuidle on them. diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index ef3e0f3aac96..a66b81cf9a4d 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -298,7 +298,11 @@ static void __dma_free_remap(void *cpu_addr, size_t size) vunmap(cpu_addr); } +#if IS_ENABLED(CONFIG_VIDEO_TW68) +#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_32M +#else #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K +#endif struct dma_pool { size_t size; diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index a10297da122b..2cc0c6dffb7f 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1007,3 +1007,4 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572 eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573 domotab MACH_DOMOTAB DOMOTAB 4574 pfla03 MACH_PFLA03 PFLA03 4575 +apalis_imx6 MACH_APALIS_IMX6 APALIS_IMX6 4886 diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 349f14e886b7..426f3e130b03 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -10,7 +10,10 @@ #include <linux/module.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of_device.h> +#include <linux/regmap.h> struct imx_weim { void __iomem *base; @@ -25,6 +28,8 @@ MODULE_DEVICE_TABLE(of, weim_id_table); #define CS_TIMING_LEN 6 #define CS_REG_RANGE 0x18 +#define CS_MAX_NUM_CS 4 +#define CS_MEM_RANGES_LEN 4 /* Parse and set the timing for this device. */ static int @@ -59,7 +64,11 @@ weim_timing_setup(struct platform_device *pdev, struct device_node *np) static int weim_parse_dt(struct platform_device *pdev) { struct device_node *child; + unsigned gpr_val, i; + struct regmap *gpr; int ret; + unsigned int start_addr = 0x08000000; /* StartAddr of next CS range */ + u32 value[CS_MAX_NUM_CS * CS_MEM_RANGES_LEN]; for_each_child_of_node(pdev->dev.of_node, child) { if (!child->name) @@ -73,6 +82,120 @@ static int weim_parse_dt(struct platform_device *pdev) } } + /* set the CS mem ranges, IOMUXC_GPR1 to 32M,32M,32M,32M */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (IS_ERR(gpr)) { + dev_err(&pdev->dev, + "failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + return ret; + } + i = 0; + do { + ret = of_property_read_u32_index(pdev->dev.of_node, + "ranges", i, &value[i]); + if (ret) + break; + i++; + } while (i < (CS_MAX_NUM_CS * CS_MEM_RANGES_LEN)); + + if (i && (i % CS_MEM_RANGES_LEN)) { + dev_err(&pdev->dev, "ranges property must be a multiple " + "of 4 32bit values but is %d\n", + i); + return -EINVAL; + } + gpr_val = 0; + /* CS 0, 128M, 64M 32M) */ + if ((value[0] != 0) || (value[2] != start_addr)) { + dev_err(&pdev->dev, "physical start addr for CS0 must be %x\n", + start_addr); + return -EINVAL; + } else { + switch (value[3]) { + case (128 * 1024 * 1024): + gpr_val = 0x5 << 0; + start_addr = 0xffffffff; + break; + case (64 * 1024 * 1024): + gpr_val = 0x3 << 0; + start_addr += 64 * 1024 * 1024; + break; + case (32 * 1024 * 1024): + gpr_val = 0x1 << 0; + start_addr += 32 * 1024 * 1024; + break; + default: + dev_err(&pdev->dev, + "size for CS0 must be 128M|64M|32M\n"); + return -EINVAL; + } + } + if (i > 4) { + /* CS 1, 64M 32M) */ + if ((value[4] != 1) || (value[4+2] != start_addr)) { + dev_err(&pdev->dev, + "physical start addr for CS1 must be %x\n", + start_addr); + return -EINVAL; + } else { + switch (value[4+3]) { + case (64 * 1024 * 1024): + gpr_val |= 0x003 << 3; + start_addr += 0xffffffff; + break; + case (32 * 1024 * 1024): + gpr_val |= 0x001 << 3; + start_addr += 32 * 1024 * 1024; + break; + default: + dev_err(&pdev->dev, + "size for CS1 must be 64M|32M\n"); + return -EINVAL; + } + } + } + if (i > 8) { + /* CS 2, 32M) */ + if ((value[8] != 2) || (value[8+2] != start_addr)) { + dev_err(&pdev->dev, + "physical start addr for CS2 must be %x\n", + start_addr); + return -EINVAL; + } else { + switch (value[8+3]) { + case (32 * 1024 * 1024): + gpr_val |= 0x001 << 6; + start_addr += 32 * 1024 * 1024; + break; + default: + dev_err(&pdev->dev, + "size for CS2 must be 32M\n"); + return -EINVAL; + } + } + } + if (i > 12) { + /* CS 3, 32M) */ + if ((value[12] != 3) || (value[12+2] != start_addr)) { + dev_err(&pdev->dev, + "physical start addr for CS3 must be %x\n", + start_addr); + return -EINVAL; + } else { + switch (value[12+3]) { + case (32 * 1024 * 1024): + gpr_val |= 0x001 << 9; + break; + default: + dev_err(&pdev->dev, + "size for CS3 must be 32M\n"); + return -EINVAL; + } + } + } + dev_dbg(&pdev->dev, "weim CS setup in IOMUXC_GPR1 %x\n", gpr_val); + regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gpr_val); + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); if (ret) dev_err(&pdev->dev, "%s fail to create devices.\n", diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c index e893f6e1937d..589d28931e8c 100644 --- a/drivers/gpu/vga/vgaarb.c +++ b/drivers/gpu/vga/vgaarb.c @@ -1099,7 +1099,7 @@ static ssize_t vga_arb_write(struct file *file, const char __user * buf, vgadev = vgadev_find(pdev); pr_debug("vgaarb: vgadev %p\n", vgadev); if (vgadev == NULL) { - pr_err("vgaarb: this pci device is not a vga device\n"); + pr_debug("vgaarb: this pci device is not a vga device\n"); pci_dev_put(pdev); ret_val = -ENODEV; goto done; diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 041a3dad16cb..9c9dc68e5e10 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -86,6 +86,16 @@ config TOUCHSCREEN_AD7879_SPI To compile this driver as a module, choose M here: the module will be called ad7879-spi. +config TOUCHSCREEN_AR1020_I2C + tristate "Microchip AR1020 I2C touchscreen" + depends on I2C + help + Say Y here if you have a Microchip AR1020 I2C Controller and + want to enable support for the built-in touchscreen. + + To compile this driver as a module, choose M here: the + module will be called ar1020-i2c. + config TOUCHSCREEN_ATMEL_MXT tristate "Atmel mXT I2C Touchscreen" depends on I2C @@ -256,6 +266,22 @@ config TOUCHSCREEN_ELAN To compile this driver as a module, choose M here: the module will be called elan-touch. +config TOUCHSCREEN_FT5X06 + tristate "Focaltech FT5X06 5 point touchscreen" + select I2C + help + If you say yes here you get touchscreen support through + FocalTech's FT5X06 controller. + +config TOUCHSCREEN_FT5X06_SINGLE_TOUCH + bool "FT5X06 touchscreen as single-touch" + default N + depends on TOUCHSCREEN_FT5X06 + help + If you say yes here you get single-touch touchscreen support + on the FT5X06 I2C controller. + If you say "no", you'll get the normal 5-finger goodness. + config TOUCHSCREEN_FUJITSU tristate "Fujitsu serial touchscreen" select SERIO @@ -834,6 +860,17 @@ config TOUCHSCREEN_TSC_SERIO To compile this driver as a module, choose M here: the module will be called tsc40. +config TOUCHSCREEN_TSC2004 + tristate "TSC2004 based touchscreens" + depends on I2C + help + Say Y here if you have a TSC2004 based touchscreen. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called tsc2004. + config TOUCHSCREEN_TSC2005 tristate "TSC2005 based touchscreens" depends on SPI_MASTER && GENERIC_HARDIRQS @@ -897,6 +934,13 @@ config TOUCHSCREEN_STMPE To compile this driver as a module, choose M here: the module will be called stmpe-ts. +config TOUCHSCREEN_FUSION_F0710A + tristate "TouchRevolution Fusion F0710A Touchscreens" + depends on I2C + help + Say Y here if you want to support the multi-touch input driver for + the TouchRevolution Fusion 7 and 10 panels. + config TOUCHSCREEN_TPS6507X tristate "TPS6507x based touchscreens" depends on I2C diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index a5dde290ada6..44869b420b78 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_TOUCHSCREEN_AD7879) += ad7879.o obj-$(CONFIG_TOUCHSCREEN_AD7879_I2C) += ad7879-i2c.o obj-$(CONFIG_TOUCHSCREEN_AD7879_SPI) += ad7879-spi.o obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o +obj-$(CONFIG_TOUCHSCREEN_AR1020_I2C) += ar1020-i2c.o obj-$(CONFIG_TOUCHSCREEN_ATMEL_MXT) += atmel_mxt_ts.o obj-$(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) += atmel_tsadcc.o obj-$(CONFIG_TOUCHSCREEN_AUO_PIXCIR) += auo-pixcir-ts.o @@ -30,6 +31,7 @@ obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o obj-$(CONFIG_TOUCHSCREEN_ELAN) += elan_ts.o obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o +obj-$(CONFIG_TOUCHSCREEN_FT5X06) += ft5x06_ts.o obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o @@ -58,6 +60,7 @@ obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213) += touchit213.o obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o obj-$(CONFIG_TOUCHSCREEN_TSC_SERIO) += tsc40.o +obj-$(CONFIG_TOUCHSCREEN_TSC2004) += tsc2004.o obj-$(CONFIG_TOUCHSCREEN_TSC2005) += tsc2005.o obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o @@ -73,3 +76,4 @@ obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o obj-$(CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE) += zylonite-wm97xx.o obj-$(CONFIG_TOUCHSCREEN_W90X900) += w90p910_ts.o obj-$(CONFIG_TOUCHSCREEN_TPS6507X) += tps6507x-ts.o +obj-$(CONFIG_TOUCHSCREEN_FUSION_F0710A) += fusion_F0710A.o diff --git a/drivers/input/touchscreen/ar1020-i2c.c b/drivers/input/touchscreen/ar1020-i2c.c new file mode 100644 index 000000000000..1ecfbecf460d --- /dev/null +++ b/drivers/input/touchscreen/ar1020-i2c.c @@ -0,0 +1,500 @@ +/* + * Microchip I2C Touchscreen Driver + * + * Copyright (c) 2011 Microchip Technology, Inc. + * + * http://www.microchip.com/mtouch + */ + +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/kobject.h> +#include <linux/string.h> +#include <linux/sysfs.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/slab.h> + +/* The private data structure that is referenced within the I2C bus driver */ +struct ar1020_i2c_priv { + struct i2c_client *client; + struct input_dev *input; + int irq; + int testCount; + int command_pending; + int use_count; + int button; + struct delayed_work reenable_work; +}; + +/* + * These are all the sysfs variables used to store and retrieve information + * from a user-level application + */ +static char sendBuffer[100]; +static char receiveBuffer[100]; +static int commandDataPending; + +/* + * These variables allows the IRQ to be specified via a module parameter + * or kernel parameter. To configuration of these value, please see + * driver documentation. + */ +static int touchIRQ; + +module_param(touchIRQ, int, S_IRUGO); + + +/* + * Since the reference to private data is stored within the I2C + * bus driver, we will store another reference within this driver + * so the sysfs related function may also access this data + */ +struct ar1020_i2c_priv *g_priv; + +/* + * Display value of "commandDataPending" variable to application that is + * requesting it's value. + */ +static ssize_t commandDataPending_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d", commandDataPending); +} + +/* + * Save value to "commandDataPending" variable from application that is + * requesting this. + */ +static ssize_t commandDataPending_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + sscanf(buf, "%d", &commandDataPending); + return count; +} + +static struct kobj_attribute commandDataPending_attribute = + __ATTR(commandDataPending, 0666, commandDataPending_show, + commandDataPending_store); + + +/* + * Display value of "receiveBuffer" variable to application that is + * requesting it's value. + */ +static ssize_t receiveBuffer_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + /* receive data is no longer pending */ + commandDataPending = 0; + return sprintf(buf, "%s", receiveBuffer); +} + +/* + * Save value to "receiveBuffer" variable from application that is + * requesting this. + */ +static ssize_t receiveBuffer_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + return snprintf(receiveBuffer, sizeof(receiveBuffer), "%s", buf); +} + +static struct kobj_attribute receiveBuffer_attribute = + __ATTR(receiveBuffer, 0666, receiveBuffer_show, receiveBuffer_store); + +/* + * Display value of "sendBuffer" variable to application that is + * requesting it's value. + */ +static ssize_t sendBuffer_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%s", sendBuffer); +} + +/* + * Save value to "sendBuffer" variable from application that is + * requesting this. + */ +static ssize_t sendBuffer_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + int data[8]; + char buff[8]; + int cnt; + int i; + struct ar1020_i2c_priv *priv = g_priv; + + commandDataPending = 0; + + cnt = sscanf(buf, "%x %x %x %x %x %x %x %x", &data[0], &data[1], + &data[2], &data[3], &data[4], &data[5], &data[6], &data[7]); + + pr_debug("AR1020 I2C: Processed %d bytes.\n", cnt); + + /* Verify command string to send to controller is valid */ + if (cnt < 3) + pr_info("AR1020 I2C: Insufficient command bytes to process.\n"); + else if (data[0] != 0x0) + pr_info("AR1020 I2C: Leading zero required when sending I2C commands.\n"); + else if (data[1] != 0x55) + pr_info("AR1020 I2C: Invalid header byte (0x55 expected).\n"); + else if (data[2] != (cnt - 3)) + pr_info("AR1020 I2C: Number of command bytes specified not " + "valid for current string.\n"); + + strcpy(sendBuffer, ""); + pr_debug("AR1020 I2C: sending command bytes: "); + for (i = 0; i < cnt; i++) { + buff[i] = (char)data[i]; + pr_debug("0x%02x ", data[i]); + } + pr_debug("\n"); + + if (priv) { + priv->command_pending = 1; + i2c_master_send(priv->client, buff, cnt); + } + + return snprintf(sendBuffer, sizeof(sendBuffer), "%s", buf); +} + +static struct kobj_attribute sendBuffer_attribute = + __ATTR(sendBuffer, 0666, sendBuffer_show, sendBuffer_store); + +/* + * Create a group of calibration attributes so we may work with them + * as a set. + */ +static struct attribute *attrs[] = { + &commandDataPending_attribute.attr, + &receiveBuffer_attribute.attr, + &sendBuffer_attribute.attr, + NULL, +}; + +static struct attribute_group attr_group = { + .attrs = attrs, +}; + +static struct kobject *ar1020_kobj; + +static void irq_reenable_work(struct work_struct *work) +{ + struct ar1020_i2c_priv *priv = container_of(work, + struct ar1020_i2c_priv, reenable_work.work); + + enable_irq(priv->irq); +} + +/* + * When the controller interrupt is asserted, this function is scheduled + * to be called to read the controller data. + */ +static irqreturn_t touch_irq_handler_func(int irq, void *dev_id) +{ + struct ar1020_i2c_priv *priv = (struct ar1020_i2c_priv *)dev_id; + int i; + int cnt; + unsigned char packet[9]; + int x; + int y; + int button; + + for (i = 0; i < 5; i++) + packet[i] = 0; + + /* + * We want to ensure we only read packets when we are not in the middle + * of command communication. Disable command mode after receiving + * command response to resume receiving packets. + */ + cnt = i2c_master_recv(priv->client, packet, + (priv->command_pending) ? 9 : 5); + + if (cnt <= 0) + goto error; + + if (packet[0] == 0x55) { + unsigned char *p = receiveBuffer; + unsigned char *pend = p + sizeof(receiveBuffer) - 2; + /* process up to 9 bytes */ + strcpy(receiveBuffer, ""); + + priv->command_pending = 0; + + if (packet[1] > 6) + pr_info("AR1020 I2C: invalid byte count\n"); + else if (cnt > packet[1] + 2) + cnt = packet[1] + 2; + + for (i = 0; i < cnt; i++) { + int ret = snprintf(p, pend - p, " 0x%02x", packet[i]); + if (ret <= 0) + break; + p += ret; + if (p >= pend) + break; + } + *p++ = '\n'; + *p++ = 0; + pr_info("AR1020 I2C: command response: %s", receiveBuffer); + commandDataPending = 1; + return IRQ_HANDLED; + } + + /* + * Decode packets of data from a device path using AR1XXX protocol. + * Data format, 5 bytes: SYNC, DATA1, DATA2, DATA3, DATA4 + * SYNC [7:0]: 1,0,0,0,0,TOUCHSTATUS[0:0] + * DATA1[7:0]: 0,X-LOW[6:0] + * DATA2[7:0]: 0,X-HIGH[4:0] + * DATA3[7:0]: 0,Y-LOW[6:0] + * DATA4[7:0]: 0,Y-HIGH[4:0] + * + * TOUCHSTATUS: 0 = Touch up, 1 = Touch down + */ + if ((packet[0] & 0xfe) != 0x80) { + pr_err("AR1020 I2C: 1st Touch byte not valid. Value: 0x%02x\n", + packet[0]); + goto error; /* irq line may be shorted high, let's delay */ + } + for (i = 1; i < 5; i++) { + /* verify byte is valid for current index */ + if (0x80 & packet[i]) { + pr_err("AR1020 I2C: Touch byte not valid. Value: " + "0x%02x Index: 0x%02x\n", packet[i], i); + goto error; + } + } + x = ((packet[2] & 0x1f) << 7) | (packet[1] & 0x7f); + y = ((packet[4] & 0x1f) << 7) | (packet[3] & 0x7f); + button = (packet[0] & 1); + + if (!button && !priv->button) + return IRQ_HANDLED; + + priv->button = button; + input_report_abs(priv->input, ABS_X, x); + input_report_abs(priv->input, ABS_Y, y); + input_report_key(priv->input, BTN_TOUCH, button); + input_sync(priv->input); + return IRQ_HANDLED; +error: + disable_irq_nosync(priv->irq); + schedule_delayed_work(&priv->reenable_work, 100); + return IRQ_HANDLED; +} + +static int ar1020_i2c_open(struct input_dev *idev) +{ + struct ar1020_i2c_priv *priv = input_get_drvdata(idev); + + if (priv->use_count++ == 0) + enable_irq(priv->irq); + return 0; +} + +static void ar1020_i2c_close(struct input_dev *idev) +{ + struct ar1020_i2c_priv *priv = input_get_drvdata(idev); + + if (--priv->use_count == 0) + disable_irq(priv->irq); +} + +/* + * After the kernel's platform specific source files have been modified to + * reference the "ar1020_i2c" driver, this function will then be called. + * This function needs to be called to finish registering the driver. + */ +static int ar1020_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ar1020_i2c_priv *priv = NULL; + struct input_dev *input_dev = NULL; + int err = 0; + int irq; + + pr_info("%s: begin\n", __func__); + + if (!client) { + pr_err("AR1020 I2C: client pointer is NULL\n"); + err = -EINVAL; + goto error; + } + + irq = client->irq; + if (touchIRQ) + irq = touchIRQ; + + if (!irq) { + pr_err("AR1020 I2C: no IRQ set for touch controller\n"); + err = -EINVAL; + goto error; + } + + priv = kzalloc(sizeof(struct ar1020_i2c_priv), GFP_KERNEL); + input_dev = input_allocate_device(); + if (!priv) { + pr_err("AR1020 I2C: kzalloc error\n"); + err = -ENOMEM; + goto error; + } + + if (!input_dev) { + pr_err("AR1020 I2C: input allocate error\n"); + err = -ENOMEM; + goto error; + } + + priv->client = client; + priv->irq = irq; + priv->input = input_dev; + INIT_DELAYED_WORK(&priv->reenable_work, irq_reenable_work); + + input_dev->name = "AR1020 Touchscreen"; + input_dev->id.bustype = BUS_I2C; + + input_dev->open = ar1020_i2c_open; + input_dev->close = ar1020_i2c_close; + + input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + + input_set_abs_params(input_dev, ABS_X, 0, 4095, 0, 0); + input_set_abs_params(input_dev, ABS_Y, 0, 4095, 0, 0); + input_set_drvdata(input_dev, priv); + err = input_register_device(input_dev); + if (err) { + pr_err("AR1020 I2C: error registering input device\n"); + goto error; + } + + /* set type and register gpio pin as our interrupt */ + err = request_threaded_irq(priv->irq, NULL, touch_irq_handler_func, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "AR1020 I2C IRQ", + priv); + if (err < 0) + goto error1; + disable_irq(priv->irq); /* wait for open */ + i2c_set_clientdata(client, priv); + /* + * save pointer so sysfs helper functions may also have access + * to private data + */ + g_priv = priv; + return 0; + +error1: + input_unregister_device(input_dev); +error: + if (input_dev) + input_free_device(input_dev); + + kfree(priv); + return err; + +} + +/* + * Unregister/remove the kernel driver from memory. + */ +static int ar1020_i2c_remove(struct i2c_client *client) +{ + struct ar1020_i2c_priv *priv = + (struct ar1020_i2c_priv *)i2c_get_clientdata(client); + + free_irq(priv->irq, priv); + input_unregister_device(priv->input); + kfree(priv); + g_priv = NULL; + return 0; +} + +/* This structure describe a list of supported slave chips */ +static const struct i2c_device_id ar1020_i2c_id[] = { + { "ar1020_i2c", 0 }, + { } +}; + +/* + * This is the initial set of information the kernel has + * before probing drivers on the system + */ +static struct i2c_driver ar1020_i2c_driver = { + .driver = { + .name = "ar1020_i2c", + }, + .probe = ar1020_i2c_probe, + .remove = ar1020_i2c_remove, + /* + * suspend/resume functions not needed since controller automatically + * put's itself to sleep mode after configurable short period of time + */ + .suspend = NULL, + .resume = NULL, + .id_table = ar1020_i2c_id, +}; + +/* + * This function is called during startup even if the platform specific + * files have not been setup yet. + */ +static int __init ar1020_i2c_init(void) +{ + int retval; + + pr_debug("AR1020 I2C: ar1020_i2c_init: begin\n"); + strcpy(receiveBuffer, ""); + strcpy(sendBuffer, ""); + + /* + * Creates a kobject "ar1020" that appears as a sub-directory + * under "/sys/kernel". + */ + ar1020_kobj = kobject_create_and_add("ar1020", kernel_kobj); + if (!ar1020_kobj) { + pr_err("AR1020 I2C: cannot create kobject\n"); + return -ENOMEM; + } + + /* Create the files associated with this kobject */ + retval = sysfs_create_group(ar1020_kobj, &attr_group); + if (retval) { + pr_err("AR1020 I2C: error registering ar1020-i2c driver's sysfs interface\n"); + kobject_put(ar1020_kobj); + } + + return i2c_add_driver(&ar1020_i2c_driver); +} + +/* + * This function is called after ar1020_i2c_remove() immediately before + * being removed from the kernel. + */ +static void __exit ar1020_i2c_exit(void) +{ + pr_debug("AR1020 I2C: ar1020_i2c_exit begin\n"); + kobject_put(ar1020_kobj); + i2c_del_driver(&ar1020_i2c_driver); +} + +MODULE_AUTHOR("Steve Grahovac <steve.grahovac@microchip.com>"); +MODULE_DESCRIPTION("AR1020 touchscreen I2C bus driver"); +MODULE_LICENSE("GPL"); + +module_init(ar1020_i2c_init); +module_exit(ar1020_i2c_exit); diff --git a/drivers/input/touchscreen/ft5x06_ts.c b/drivers/input/touchscreen/ft5x06_ts.c new file mode 100644 index 000000000000..1b8a7695188d --- /dev/null +++ b/drivers/input/touchscreen/ft5x06_ts.c @@ -0,0 +1,633 @@ +/* + * Boundary Devices FTx06 touch screen controller. + * + * Copyright (c) by Boundary Devices <info@boundarydevices.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/wait.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/of_gpio.h> +#include <linux/proc_fs.h> +#include <linux/delay.h> +#include <linux/input.h> + +#ifdef CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH +#else +#define USE_ABS_MT +#endif + +static int calibration[7] = { + 65536,0,0, + 0,65536,0, + 65536 +}; +module_param_array(calibration, int, NULL, S_IRUGO | S_IWUSR); + +static int screenres[2] = {1024, 600}; +module_param_array(screenres, int, NULL, S_IRUGO | S_IWUSR); + +static void translate(int *px, int *py) +{ + int x, y, x1, y1; + if (calibration[6]) { + x1 = *px; + y1 = *py; + + x = calibration[0] * x1 + + calibration[1] * y1 + + calibration[2]; + x /= calibration[6]; + if (x < 0) + x = 0; + y = calibration[3] * x1 + + calibration[4] * y1 + + calibration[5]; + y /= calibration[6]; + if (y < 0) + y = 0; + *px = x ; + *py = y ; + } +} + +struct point { + int x; + int y; +}; + +struct ft5x06_ts { + struct i2c_client *client; + struct input_dev *idev; + struct workqueue_struct *wq; + struct work_struct work; + struct delayed_work reenable_work; + int int_disabled; + struct semaphore sem; + int use_count; + int bReady; + int irq; + unsigned gp; + int buttons; + struct proc_dir_entry *procentry; +}; +static const char *client_name = "ft5x06"; + +struct ft5x06_ts *gts; + +static char const procentryname[] = { + "ft5x06" +}; + +static int ts_startup(struct ft5x06_ts *ts); +static void ts_shutdown(struct ft5x06_ts *ts); + +/*-----------------------------------------------------------------------*/ +static inline void ts_evt_add(struct ft5x06_ts *ts, + unsigned buttons, struct point *p) +{ + struct input_dev *idev = ts->idev; + int i; + if (!buttons) { + /* send release to user space. */ +#ifdef USE_ABS_MT + input_event(idev, EV_ABS, ABS_MT_TOUCH_MAJOR, 0); + input_event(idev, EV_KEY, BTN_TOUCH, 0); + input_mt_sync(idev); +#else + input_report_abs(idev, ABS_PRESSURE, 0); + input_report_key(idev, BTN_TOUCH, 0); + input_sync(idev); +#endif + } else { + for (i = 0; i < buttons; i++) { + translate(&p[i].x, &p[i].y); +#ifdef USE_ABS_MT + input_event(idev, EV_ABS, ABS_MT_POSITION_X, p[i].x); + input_event(idev, EV_ABS, ABS_MT_POSITION_Y, p[i].y); + input_event(idev, EV_ABS, ABS_MT_TOUCH_MAJOR, 1); + input_mt_sync(idev); +#else + input_report_abs(idev, ABS_X, p[i].x); + input_report_abs(idev, ABS_Y, p[i].y); + input_report_abs(idev, ABS_PRESSURE, 1); + input_report_key(idev, BTN_TOUCH, 1); + input_sync(idev); +#endif + } + input_event(idev, EV_KEY, BTN_TOUCH, 1); + } +#ifdef USE_ABS_MT + input_sync(idev); +#endif +} + +static int ts_open(struct input_dev *idev) +{ + struct ft5x06_ts *ts = input_get_drvdata(idev); + return ts_startup(ts); +} + +static void ts_close(struct input_dev *idev) +{ + struct ft5x06_ts *ts = input_get_drvdata(idev); + ts_shutdown(ts); +} + +static inline int ts_register(struct ft5x06_ts *ts) +{ + struct input_dev *idev; + idev = input_allocate_device(); + if (idev == NULL) + return -ENOMEM; + + ts->idev = idev; + idev->name = procentryname ; + idev->id.product = ts->client->addr; + idev->open = ts_open; + idev->close = ts_close; + + __set_bit(EV_ABS, idev->evbit); + __set_bit(EV_KEY, idev->evbit); + __set_bit(BTN_TOUCH, idev->keybit); + +#ifdef USE_ABS_MT + input_set_abs_params(idev, ABS_MT_POSITION_X, 0, screenres[0]-1, 0, 0); + input_set_abs_params(idev, ABS_MT_POSITION_Y, 0, screenres[1]-1, 0, 0); + input_set_abs_params(idev, ABS_X, 0, screenres[0]-1, 0, 0); + input_set_abs_params(idev, ABS_Y, 0, screenres[1]-1, 0, 0); + input_set_abs_params(idev, ABS_MT_TOUCH_MAJOR, 0, 1, 0, 0); +#else + __set_bit(EV_SYN, idev->evbit); + input_set_abs_params(idev, ABS_X, 0, screenres[0]-1, 0, 0); + input_set_abs_params(idev, ABS_Y, 0, screenres[1]-1, 0, 0); + input_set_abs_params(idev, ABS_PRESSURE, 0, 1, 0, 0); +#endif + + input_set_drvdata(idev, ts); + return input_register_device(idev); +} + +static inline void ts_deregister(struct ft5x06_ts *ts) +{ + if (ts->idev) { + input_unregister_device(ts->idev); + input_free_device(ts->idev); + ts->idev = NULL; + } +} + +#ifdef DEBUG +static void printHex(u8 const *buf, unsigned len) +{ + char hex[512]; + char *next = hex ; + char *end = hex+sizeof(hex); + + while (len--) { + next += snprintf(next, end-next, "%02x", *buf++); + if (next >= end) { + hex[sizeof(hex)-1] = '\0' ; + break; + } + } + printk(KERN_ERR "%s\n", hex); +} +#endif + +static void write_reg(struct ft5x06_ts *ts, int regnum, int value) +{ + u8 regnval[] = { + regnum, + value + }; + struct i2c_msg pkt = { + ts->client->addr, 0, sizeof(regnval), regnval + }; + int ret = i2c_transfer(ts->client->adapter, &pkt, 1); + if (ret != 1) + printk(KERN_WARNING "%s: i2c_transfer failed\n", __func__); + else + printk(KERN_DEBUG "%s: set register 0x%02x to 0x%02x\n", + __func__, regnum, value); +} + +static void set_mode(struct ft5x06_ts *ts, int mode) +{ + write_reg(ts, 0, (mode&7)<<4); + printk(KERN_DEBUG "%s: changed mode to 0x%02x\n", __func__, mode); +} + +#define WORK_MODE 0 +#define FACTORY_MODE 4 + +static int proc_regnum = 0; +static int ft5x06_proc_read + (struct file *f, + char __user *ubuf, + size_t count, + loff_t *off) +{ + int ret; + unsigned char startch[1] = { (u8)proc_regnum }; + unsigned char buf[1]; + struct i2c_msg readpkt[2] = { + {gts->client->addr, 0, 1, startch}, + {gts->client->addr, I2C_M_RD, sizeof(buf), buf} + }; + ret = i2c_transfer(gts->client->adapter, readpkt, + ARRAY_SIZE(readpkt)); + if (ret != ARRAY_SIZE(readpkt)) { + printk(KERN_WARNING "%s: i2c_transfer failed\n", + client_name); + } else { + printk (KERN_ERR "ft5x06[0x%02x] == 0x%02x\n", (u8)proc_regnum, buf[0]); + } + return 0 ; +} + +static int +ft5x06_proc_write + (struct file *file, + const char __user *buffer, + size_t count, + loff_t *data) +{ + proc_regnum = simple_strtoul(buffer,0,0); + return count ; +} + +struct file_operations proc_fops = { + .read = ft5x06_proc_read, + .write = ft5x06_proc_write, +}; + +/*-----------------------------------------------------------------------*/ +static void irq_reenable_work(struct work_struct *work) +{ + struct ft5x06_ts *ts = container_of(work, struct ft5x06_ts, + reenable_work.work); + + if (ts->int_disabled) { + ts->int_disabled = 0; + enable_irq(ts->irq); + } +} + + +static void ts_work_func(struct work_struct *work) +{ + struct ft5x06_ts *ts = container_of(work, + struct ft5x06_ts, work); + int ret; + struct point points[5]; + unsigned char buf[33]; + unsigned char startch[1] = { 0 }; + struct i2c_msg readpkt[2] = { + {ts->client->addr, 0, 1, startch}, + {ts->client->addr, I2C_M_RD, sizeof(buf), buf} + }; + int loop_max = 10; + int buttons = 0 ; + + while (0 == gpio_get_value(ts->gp)) { + ts->bReady = 0; + ret = i2c_transfer(ts->client->adapter, readpkt, + ARRAY_SIZE(readpkt)); + if (ret != ARRAY_SIZE(readpkt)) { + printk(KERN_WARNING "%s: i2c_transfer failed\n", + client_name); + msleep(1000); + } else { + int i; + unsigned char *p = buf+3; +#ifdef DEBUG + printHex(buf, sizeof(buf)); +#endif + buttons = buf[2]; + if (buttons > 5) { + printk(KERN_ERR + "%s: invalid button count %02x\n", + __func__, buttons); + buttons = 0 ; + } else { + for (i = 0; i < buttons; i++) { + points[i].x = ((p[0] << 8) + | p[1]) & 0x7ff; + points[i].y = ((p[2] << 8) + | p[3]) & 0x7ff; + p += 6; + } + } + } + +#ifdef DEBUG + printk(KERN_ERR "%s: buttons = %d, " + "points[0].x = %d, " + "points[0].y = %d\n", + client_name, buttons, points[0].x, points[0].y); +#endif + ts_evt_add(ts, buttons, points); + if (--loop_max == 0) + goto error; + } + ts->int_disabled = 0; + ts->buttons = buttons; + enable_irq(ts->irq); + return; +error: + schedule_delayed_work(&ts->reenable_work, 100); + return; +} + +/* + * We only detect samples ready with this interrupt + * handler, and even then we just schedule our task. + */ +static irqreturn_t ts_interrupt(int irq, void *id) +{ + struct ft5x06_ts *ts = id; + + disable_irq_nosync(ts->client->irq); + ts->int_disabled = 1; + queue_work(ts->wq, &ts->work); + return IRQ_HANDLED; +} + +#define ID_G_THGROUP 0x80 +#define ID_G_PERIODMONITOR 0x89 +#define FT5X0X_REG_HEIGHT_B 0x8a +#define FT5X0X_REG_MAX_FRAME 0x8b +#define FT5X0X_REG_FEG_FRAME 0x8e +#define FT5X0X_REG_LEFT_RIGHT_OFFSET 0x92 +#define FT5X0X_REG_UP_DOWN_OFFSET 0x93 +#define FT5X0X_REG_DISTANCE_LEFT_RIGHT 0x94 +#define FT5X0X_REG_DISTANCE_UP_DOWN 0x95 +#define FT5X0X_REG_MAX_X_HIGH 0x98 +#define FT5X0X_REG_MAX_X_LOW 0x99 +#define FT5X0X_REG_MAX_Y_HIGH 0x9a +#define FT5X0X_REG_MAX_Y_LOW 0x9b +#define FT5X0X_REG_K_X_HIGH 0x9c +#define FT5X0X_REG_K_X_LOW 0x9d +#define FT5X0X_REG_K_Y_HIGH 0x9e +#define FT5X0X_REG_K_Y_LOW 0x9f + +#define ID_G_AUTO_CLB 0xa0 +#define ID_G_B_AREA_TH 0xae + +#ifdef DEBUG +static void dumpRegs(struct ft5x06_ts *ts, unsigned start, unsigned end) +{ + u8 regbuf[512]; + unsigned char startch[1] = { start }; + int ret ; + struct i2c_msg readpkt[2] = { + {ts->client->addr, 0, 1, startch}, + {ts->client->addr, I2C_M_RD, end-start+1, regbuf} + }; + ret = i2c_transfer(ts->client->adapter, readpkt, ARRAY_SIZE(readpkt)); + if (ret != ARRAY_SIZE(readpkt)) { + printk(KERN_WARNING "%s: i2c_transfer failed\n", client_name); + } else { + printk(KERN_ERR "registers %02x..%02x\n", start, end); + printHex(regbuf, end-start+1); + } +} +#endif + +static int ts_startup(struct ft5x06_ts *ts) +{ + int ret = 0; + if (ts == NULL) + return -EIO; + + if (down_interruptible(&ts->sem)) + return -EINTR; + + if (ts->use_count++ != 0) + goto out; + + ret = request_irq(ts->irq, &ts_interrupt, IRQF_TRIGGER_FALLING, + client_name, ts); + if (ret) { + printk(KERN_ERR "%s: request_irq failed, irq:%i\n", + client_name, ts->irq); + goto out; + } + +#ifdef DEBUG + set_mode(ts, FACTORY_MODE); + dumpRegs(ts, 0x4c, 0x4C); + write_reg(ts, 0x4C, 0x05); + dumpRegs(ts, 0, 0x4C); +#endif + set_mode(ts, WORK_MODE); +#ifdef DEBUG + dumpRegs(ts, 0x3b, 0x3b); + dumpRegs(ts, 0x6a, 0x6a); + dumpRegs(ts, ID_G_THGROUP, ID_G_PERIODMONITOR); + dumpRegs(ts, FT5X0X_REG_HEIGHT_B, FT5X0X_REG_K_Y_LOW); + dumpRegs(ts, ID_G_AUTO_CLB, ID_G_B_AREA_TH); +#endif + set_mode(ts, WORK_MODE); + + out: + if (ret) + ts->use_count--; + up(&ts->sem); + return ret; +} + +/* + * Release touchscreen resources. Disable IRQs. + */ +static void ts_shutdown(struct ft5x06_ts *ts) +{ + if (ts) { + down(&ts->sem); + if (--ts->use_count == 0) { + cancel_work_sync(&ts->work); + cancel_delayed_work_sync(&ts->reenable_work); + free_irq(ts->irq, ts); + } + up(&ts->sem); + } +} +/*-----------------------------------------------------------------------*/ + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int detect_ft5x06(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + char buffer; + struct i2c_msg pkt = { + client->addr, + I2C_M_RD, + sizeof(buffer), + &buffer + }; + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + if (i2c_transfer(adapter, &pkt, 1) != 1) + return -ENODEV; + return 0; +} + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int ts_detect(struct i2c_client *client, + struct i2c_board_info *info) +{ + int err = detect_ft5x06(client); + if (!err) + strlcpy(info->type, "ft5x06-ts", I2C_NAME_SIZE); + return err; +} + +static int ts_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + int err = 0; + struct ft5x06_ts *ts; + struct device *dev = &client->dev; + struct device_node *np = client->dev.of_node; + if (gts) { + printk(KERN_ERR "%s: Error gts is already allocated\n", + client_name); + return -ENOMEM; + } + if (detect_ft5x06(client) != 0) { + dev_err(dev, "%s: Could not detect touch screen.\n", + client_name); + return -ENODEV; + } + ts = kzalloc(sizeof(struct ft5x06_ts), GFP_KERNEL); + if (!ts) { + dev_err(dev, "Couldn't allocate memory for %s\n", client_name); + return -ENOMEM; + } + sema_init(&ts->sem, 1); + ts->client = client; + ts->irq = client->irq ; + ts->gp = of_get_named_gpio(np, "wakeup-gpios", 0); + if (!gpio_is_valid(ts->gp)) + return -ENODEV; + + err = gpio_request(ts->gp, "ft5x06_irq"); + if (err < 0) { + dev_err(&client->dev, + "request gpio failed, cannot wake up controller: %d\n", + err); + return err; + } + + ts->wq = create_singlethread_workqueue("ft5x06_wq"); + if (!ts->wq) { + pr_err("%s: create workqueue failed\n", __func__); + err = -ENOMEM; + goto err_create_wq_failed; + } + INIT_WORK(&ts->work, ts_work_func); + INIT_DELAYED_WORK(&ts->reenable_work, irq_reenable_work); + + printk(KERN_INFO "%s: %s touchscreen irq=%i, gp=%i\n", __func__, + client_name, ts->irq, ts->gp); + i2c_set_clientdata(client, ts); + err = ts_register(ts); + if (err == 0) { + gts = ts; + ts->procentry = proc_create(procentryname, 0x660, NULL, + &proc_fops); + return 0; + } +err_create_wq_failed: + printk(KERN_WARNING "%s: ts_register failed\n", client_name); + ts_deregister(ts); + kfree(ts); + return err; +} + +static int ts_remove(struct i2c_client *client) +{ + struct ft5x06_ts *ts = i2c_get_clientdata(client); + remove_proc_entry(procentryname, 0); + if (ts == gts) { + gts = NULL; + ts_deregister(ts); + } else { + printk(KERN_ERR "%s: Error ts!=gts\n", client_name); + } + if (ts->wq) + destroy_workqueue(ts->wq); + kfree(ts); + return 0; +} + + +/*-----------------------------------------------------------------------*/ + +static const struct i2c_device_id ts_idtable[] = { + { "ft5x06-ts", 0 }, + { } +}; + +static const struct of_device_id ft5x06_dt_ids[] = { + { + .compatible = "ft5x06,ft5x06-touch", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, ft5x06_dt_ids); + +static struct i2c_driver ts_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ft5x06-ts", + .of_match_table = ft5x06_dt_ids, + }, + .id_table = ts_idtable, + .probe = ts_probe, + .remove = ts_remove, + .detect = ts_detect, +}; + +static int __init ts_init(void) +{ + int res = i2c_add_driver(&ts_driver); + if (res) { + printk(KERN_WARNING "%s: i2c_add_driver failed\n", client_name); + return res; + } + printk(KERN_INFO "%s: " __DATE__ "\n", client_name); + return 0; +} + +static void __exit ts_exit(void) +{ + i2c_del_driver(&ts_driver); +} + +MODULE_AUTHOR("Boundary Devices <info@boundarydevices.com>"); +MODULE_DESCRIPTION("I2C interface for FocalTech ft5x06 touch screen controller."); +MODULE_LICENSE("GPL"); + +module_init(ts_init) +module_exit(ts_exit) diff --git a/drivers/input/touchscreen/fusion_F0710A.c b/drivers/input/touchscreen/fusion_F0710A.c new file mode 100644 index 000000000000..0c7598b3da6e --- /dev/null +++ b/drivers/input/touchscreen/fusion_F0710A.c @@ -0,0 +1,569 @@ +/* + * "fusion_F0710A" touchscreen driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/workqueue.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <asm/irq.h> +#include <linux/gpio.h> +#include <linux/input/fusion_F0710A.h> +#include <linux/slab.h> +#include <linux/of_gpio.h> + + +#include "fusion_F0710A.h" + +#define DRV_NAME "fusion_F0710A" + + +static struct fusion_F0710A_data fusion_F0710A; + +static unsigned short normal_i2c[] = { fusion_F0710A_I2C_SLAVE_ADDR, I2C_CLIENT_END }; + +//I2C_CLIENT_INSMOD; + +static int fusion_F0710A_write_u8(u8 addr, u8 data) +{ + return i2c_smbus_write_byte_data(fusion_F0710A.client, addr, data); +} + +static int fusion_F0710A_read_u8(u8 addr) +{ + return i2c_smbus_read_byte_data(fusion_F0710A.client, addr); +} + +static int fusion_F0710A_read_block(u8 addr, u8 len, u8 *data) +{ +#if 0 + /* When i2c_smbus_read_i2c_block_data() takes a block length parameter, we can do + * this. lm-sensors lists hints this has been fixed, but I can't tell whether it + * was or will be merged upstream. */ + + return i2c_smbus_read_i2c_block_data(&fusion_F0710A.client, addr, data); +#else + u8 msgbuf0[1] = { addr }; + u16 slave = fusion_F0710A.client->addr; + u16 flags = fusion_F0710A.client->flags; + struct i2c_msg msg[2] = { { slave, flags, 1, msgbuf0 }, + { slave, flags | I2C_M_RD, len, data } + }; + + return i2c_transfer(fusion_F0710A.client->adapter, msg, ARRAY_SIZE(msg)); +#endif +} + + +static int fusion_F0710A_register_input(void) +{ + int ret; + struct input_dev *dev; + + dev = fusion_F0710A.input = input_allocate_device(); + if (dev == NULL) + return -ENOMEM; + + dev->name = "fusion_F0710A"; + + set_bit(EV_KEY, dev->evbit); + set_bit(EV_ABS, dev->evbit); + + input_set_abs_params(dev, ABS_MT_POSITION_X, 0, fusion_F0710A.info.xres-1, 0, 0); + input_set_abs_params(dev, ABS_MT_POSITION_Y, 0, fusion_F0710A.info.yres-1, 0, 0); +#ifdef CONFIG_ANDROID + input_set_abs_params(dev, ABS_MT_TRACKING_ID, 0, 15, 0, 0); +#else + input_set_abs_params(dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); + input_set_abs_params(dev, ABS_MT_WIDTH_MAJOR, 0, 15, 0, 0); +#endif + + input_set_abs_params(dev, ABS_X, 0, fusion_F0710A.info.xres-1, 0, 0); + input_set_abs_params(dev, ABS_Y, 0, fusion_F0710A.info.yres-1, 0, 0); + input_set_abs_params(dev, ABS_PRESSURE, 0, 255, 0, 0); + + ret = input_register_device(dev); + if (ret < 0) + goto bail1; + + return 0; + +bail1: + input_free_device(dev); + return ret; +} + +#define WC_RETRY_COUNT 3 +static int fusion_F0710A_write_complete(void) +{ + int ret, i; + + for(i=0; i<WC_RETRY_COUNT; i++) + { + ret = fusion_F0710A_write_u8(fusion_F0710A_SCAN_COMPLETE, 0); + if(ret == 0) + break; + else + dev_err(&fusion_F0710A.client->dev, "Write complete failed(%d): %d\n", i, ret); + } + + return ret; +} + +#define DATA_START fusion_F0710A_DATA_INFO +#define DATA_END fusion_F0710A_SEC_TIDTS +#define DATA_LEN (DATA_END - DATA_START + 1) +#define DATA_OFF(x) ((x) - DATA_START) + +static int fusion_F0710A_read_sensor(void) +{ + int ret; + u8 data[DATA_LEN]; + +#define DATA(x) (data[DATA_OFF(x)]) + /* To ensure data coherency, read the sensor with a single transaction. */ + ret = fusion_F0710A_read_block(DATA_START, DATA_LEN, data); + if (ret < 0) { + dev_err(&fusion_F0710A.client->dev, + "Read block failed: %d\n", ret); + + return ret; + } + + fusion_F0710A.f_num = DATA(fusion_F0710A_DATA_INFO)&0x03; + + fusion_F0710A.y1 = DATA(fusion_F0710A_POS_X1_HI) << 8; + fusion_F0710A.y1 |= DATA(fusion_F0710A_POS_X1_LO); + fusion_F0710A.x1 = DATA(fusion_F0710A_POS_Y1_HI) << 8; + fusion_F0710A.x1 |= DATA(fusion_F0710A_POS_Y1_LO); + fusion_F0710A.z1 = DATA(fusion_F0710A_FIR_PRESS); + fusion_F0710A.tip1 = DATA(fusion_F0710A_FIR_TIDTS)&0x0f; + fusion_F0710A.tid1 = (DATA(fusion_F0710A_FIR_TIDTS)&0xf0)>>4; + + + fusion_F0710A.y2 = DATA(fusion_F0710A_POS_X2_HI) << 8; + fusion_F0710A.y2 |= DATA(fusion_F0710A_POS_X2_LO); + fusion_F0710A.x2 = DATA(fusion_F0710A_POS_Y2_HI) << 8; + fusion_F0710A.x2 |= DATA(fusion_F0710A_POS_Y2_LO); + fusion_F0710A.z2 = DATA(fusion_F0710A_SEC_PRESS); + fusion_F0710A.tip2 = DATA(fusion_F0710A_SEC_TIDTS)&0x0f; + fusion_F0710A.tid2 =(DATA(fusion_F0710A_SEC_TIDTS)&0xf0)>>4; +#undef DATA + + return 0; +} + +#define val_cut_max(x, max, reverse) \ +do \ +{ \ + if(x > max) \ + x = max; \ + if(reverse) \ + x = (max) - (x); \ +} \ +while(0) + +static void fusion_F0710A_wq(struct work_struct *work) +{ + struct input_dev *dev = fusion_F0710A.input; + int save_points = 0; + int x1 = 0, y1 = 0, z1 = 0, x2 = 0, y2 = 0, z2 = 0; + + if (fusion_F0710A_read_sensor() < 0) + goto restore_irq; + +#ifdef DEBUG + printk(KERN_DEBUG "tip1, tid1, x1, y1, z1 (%x,%x,%d,%d,%d); tip2, tid2, x2, y2, z2 (%x,%x,%d,%d,%d)\n", + fusion_F0710A.tip1, fusion_F0710A.tid1, fusion_F0710A.x1, fusion_F0710A.y1, fusion_F0710A.z1, + fusion_F0710A.tip2, fusion_F0710A.tid2, fusion_F0710A.x2, fusion_F0710A.y2, fusion_F0710A.z2); +#endif /* DEBUG */ + + val_cut_max(fusion_F0710A.x1, fusion_F0710A.info.xres-1, fusion_F0710A.info.xy_reverse); + val_cut_max(fusion_F0710A.y1, fusion_F0710A.info.yres-1, fusion_F0710A.info.xy_reverse); + val_cut_max(fusion_F0710A.x2, fusion_F0710A.info.xres-1, fusion_F0710A.info.xy_reverse); + val_cut_max(fusion_F0710A.y2, fusion_F0710A.info.yres-1, fusion_F0710A.info.xy_reverse); + + if(fusion_F0710A.tip1 == 1) + { + if(fusion_F0710A.tid1 == 1) + { + /* first point */ + x1 = fusion_F0710A.x1; + y1 = fusion_F0710A.y1; + z1 = fusion_F0710A.z1; + save_points |= fusion_F0710A_SAVE_PT1; + } + else if(fusion_F0710A.tid1 == 2) + { + /* second point ABS_DISTANCE second point pressure, BTN_2 second point touch */ + x2 = fusion_F0710A.x1; + y2 = fusion_F0710A.y1; + z2 = fusion_F0710A.z1; + save_points |= fusion_F0710A_SAVE_PT2; + } + } + + if(fusion_F0710A.tip2 == 1) + { + if(fusion_F0710A.tid2 == 2) + { + /* second point ABS_DISTANCE second point pressure, BTN_2 second point touch */ + x2 = fusion_F0710A.x2; + y2 = fusion_F0710A.y2; + z2 = fusion_F0710A.z2; + save_points |= fusion_F0710A_SAVE_PT2; + } + else if(fusion_F0710A.tid2 == 1)/* maybe this will never happen */ + { + /* first point */ + x1 = fusion_F0710A.x2; + y1 = fusion_F0710A.y2; + z1 = fusion_F0710A.z2; + save_points |= fusion_F0710A_SAVE_PT1; + } + } + +#ifdef CONFIG_ANDROID + if(z1) + { + input_report_abs(dev, ABS_MT_TRACKING_ID, 1); + input_report_abs(dev, ABS_MT_POSITION_X, x1); + input_report_abs(dev, ABS_MT_POSITION_Y, y1); + } + input_mt_sync(dev); + + if(z2) + { + input_report_abs(dev, ABS_MT_TRACKING_ID, 2); + input_report_abs(dev, ABS_MT_POSITION_X, x2); + input_report_abs(dev, ABS_MT_POSITION_Y, y2); + } + input_mt_sync(dev); +#else /* CONFIG_ANDROID */ + input_report_abs(dev, ABS_MT_TOUCH_MAJOR, z1); + input_report_abs(dev, ABS_MT_WIDTH_MAJOR, 1); + input_report_abs(dev, ABS_MT_POSITION_X, x1); + input_report_abs(dev, ABS_MT_POSITION_Y, y1); + input_mt_sync(dev); + input_report_abs(dev, ABS_MT_TOUCH_MAJOR, z2); + input_report_abs(dev, ABS_MT_WIDTH_MAJOR, 2); + input_report_abs(dev, ABS_MT_POSITION_X, x2); + input_report_abs(dev, ABS_MT_POSITION_Y, y2); + input_mt_sync(dev); +#endif /* CONFIG_ANDROID */ + + input_report_abs(dev, ABS_X, x1); + input_report_abs(dev, ABS_Y, y1); + input_report_abs(dev, ABS_PRESSURE, z1); + input_report_key(dev, BTN_TOUCH, fusion_F0710A.tip1); + + input_sync(dev); + +restore_irq: + enable_irq(fusion_F0710A.client->irq); + + /* Clear fusion_F0710A interrupt */ + fusion_F0710A_write_complete(); +} +static DECLARE_WORK(fusion_F0710A_work, fusion_F0710A_wq); + +static irqreturn_t fusion_F0710A_interrupt(int irq, void *dev_id) +{ + disable_irq_nosync(fusion_F0710A.client->irq); + + queue_work(fusion_F0710A.workq, &fusion_F0710A_work); + + return IRQ_HANDLED; +} + +const static u8* g_ver_product[4] = { + "10Z8", "70Z7", "43Z6", "" +}; + +static int of_fusion_F0710A_get_pins(struct device_node *np, + unsigned int *int_pin, unsigned int *reset_pin) +{ + if (of_gpio_count(np) < 2) + return -ENODEV; + + *int_pin = of_get_gpio(np, 0); + *reset_pin = of_get_gpio(np, 1); + + if (!gpio_is_valid(*int_pin) || !gpio_is_valid(*reset_pin)) { + pr_err("%s: invalid GPIO pins, int=%d/reset=%d\n", + np->full_name, *int_pin, *reset_pin); + return -ENODEV; + } + + return 0; +} + +static int fusion_F0710A_probe(struct i2c_client *i2c, const struct i2c_device_id *id) +{ + struct device_node *np = i2c->dev.of_node; + struct fusion_f0710a_init_data *pdata = i2c->dev.platform_data; + int ret; + u8 ver_product, ver_id; + u32 version; + + if (np != NULL) { + pdata = i2c->dev.platform_data = + devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL); + if (pdata == NULL) { + dev_err(&i2c->dev, "No platform data for Fusion driver\n"); + return -ENODEV; + } + /* the dtb did the pinmuxing for us */ + pdata->pinmux_fusion_pins = NULL; + ret = of_fusion_F0710A_get_pins(i2c->dev.of_node, + &pdata->gpio_int, &pdata->gpio_reset); + if (ret) + return ret; + } + else if (pdata == NULL) { + dev_err(&i2c->dev, "No platform data for Fusion driver\n"); + return -ENODEV; + } + + /* Request pinmuxing, if necessary */ + if (pdata->pinmux_fusion_pins != NULL) { + ret = pdata->pinmux_fusion_pins(); + if (ret < 0) { + dev_err(&i2c->dev, "muxing GPIOs failed\n"); + return -ENODEV; + } + } + + if ((gpio_request(pdata->gpio_int, "Fusion pen down interrupt") == 0) && + (gpio_direction_input(pdata->gpio_int) == 0)) { + gpio_export(pdata->gpio_int, 0); + } else { + dev_warn(&i2c->dev, "Could not obtain GPIO for Fusion pen down\n"); + return -ENODEV; + } + + if ((gpio_request(pdata->gpio_reset, "Fusion reset") == 0) && + (gpio_direction_output(pdata->gpio_reset, 1) == 0)) { + + /* Generate a 0 => 1 edge explicitly, and wait for startup... */ + gpio_set_value(pdata->gpio_reset, 0); + msleep(10); + gpio_set_value(pdata->gpio_reset, 1); + /* Wait for startup (up to 125ms according to datasheet) */ + msleep(125); + + gpio_export(pdata->gpio_reset, 0); + } else { + dev_warn(&i2c->dev, "Could not obtain GPIO for Fusion reset\n"); + ret = -ENODEV; + goto bail0; + } + + /* Use Pen Down GPIO as sampling interrupt */ + i2c->irq = gpio_to_irq(pdata->gpio_int); + + if(!i2c->irq) + { + dev_err(&i2c->dev, "fusion_F0710A irq < 0 \n"); + ret = -ENOMEM; + goto bail1; + } + + /* Attach the I2C client */ + fusion_F0710A.client = i2c; + i2c_set_clientdata(i2c, &fusion_F0710A); + + dev_info(&i2c->dev, "Touchscreen registered with bus id (%d) with slave address 0x%x\n", + i2c_adapter_id(fusion_F0710A.client->adapter), fusion_F0710A.client->addr); + + /* Read out a lot of registers */ + ret = fusion_F0710A_read_u8(fusion_F0710A_VIESION_INFO_LO); + if (ret < 0) { + dev_err(&i2c->dev, "query failed: %d\n", ret); + goto bail1; + } + ver_product = (((u8)ret) & 0xc0) >> 6; + version = (10 + ((((u32)ret)&0x30) >> 4)) * 100000; + version += (((u32)ret)&0xf) * 1000; + /* Read out a lot of registers */ + ret = fusion_F0710A_read_u8(fusion_F0710A_VIESION_INFO); + if (ret < 0) { + dev_err(&i2c->dev, "query failed: %d\n", ret); + goto bail1; + } + ver_id = ((u8)(ret) & 0x6) >> 1; + version += ((((u32)ret) & 0xf8) >> 3) * 10; + version += (((u32)ret) & 0x1) + 1; /* 0 is build 1, 1 is build 2 */ + dev_info(&i2c->dev, "version product %s(%d)\n", g_ver_product[ver_product] ,ver_product); + dev_info(&i2c->dev, "version id %s(%d)\n", ver_id ? "1.4" : "1.0", ver_id); + dev_info(&i2c->dev, "version series (%d)\n", version); + + switch(ver_product) + { + case fusion_F0710A_VIESION_07: /* 7 inch */ + fusion_F0710A.info.xres = fusion_F0710A07_XMAX; + fusion_F0710A.info.yres = fusion_F0710A07_YMAX; + fusion_F0710A.info.xy_reverse = fusion_F0710A07_REV; + break; + case fusion_F0710A_VIESION_43: /* 4.3 inch */ + fusion_F0710A.info.xres = fusion_F0710A43_XMAX; + fusion_F0710A.info.yres = fusion_F0710A43_YMAX; + fusion_F0710A.info.xy_reverse = fusion_F0710A43_REV; + break; + default: /* fusion_F0710A_VIESION_10 10 inch */ + fusion_F0710A.info.xres = fusion_F0710A10_XMAX; + fusion_F0710A.info.yres = fusion_F0710A10_YMAX; + fusion_F0710A.info.xy_reverse = fusion_F0710A10_REV; + break; + } + + /* Register the input device. */ + ret = fusion_F0710A_register_input(); + if (ret < 0) { + dev_err(&i2c->dev, "can't register input: %d\n", ret); + goto bail1; + } + + /* Create a worker thread */ + fusion_F0710A.workq = create_singlethread_workqueue(DRV_NAME); + if (fusion_F0710A.workq == NULL) { + dev_err(&i2c->dev, "can't create work queue\n"); + ret = -ENOMEM; + goto bail2; + } + + + /* Register for the interrupt and enable it. Our handler will + * start getting invoked after this call. */ + ret = request_irq(i2c->irq, fusion_F0710A_interrupt, IRQF_TRIGGER_RISING, + i2c->name, &fusion_F0710A); + if (ret < 0) { + dev_err(&i2c->dev, "can't get irq %d: %d\n", i2c->irq, ret); + goto bail3; + } + /* clear the irq first */ + ret = fusion_F0710A_write_u8(fusion_F0710A_SCAN_COMPLETE, 0); + if (ret < 0) { + dev_err(&i2c->dev, "Clear irq failed: %d\n", ret); + goto bail4; + } + + return 0; + +bail4: + free_irq(i2c->irq, &fusion_F0710A); + +bail3: + destroy_workqueue(fusion_F0710A.workq); + fusion_F0710A.workq = NULL; + +bail2: + input_unregister_device(fusion_F0710A.input); +bail1: + gpio_free(pdata->gpio_reset); +bail0: + gpio_free(pdata->gpio_int); + + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int fusion_F0710A_suspend(struct device *dev) +{ + struct i2c_client *i2c = to_i2c_client(dev); + disable_irq(i2c->irq); + flush_workqueue(fusion_F0710A.workq); + + return 0; +} + +static int fusion_F0710A_resume(struct device *dev) +{ + struct i2c_client *i2c = to_i2c_client(dev); + enable_irq(i2c->irq); + + return 0; +} +#endif + +static int fusion_F0710A_remove(struct i2c_client *i2c) +{ + struct fusion_f0710a_init_data *pdata = i2c->dev.platform_data; + + gpio_free(pdata->gpio_int); + gpio_free(pdata->gpio_reset); + destroy_workqueue(fusion_F0710A.workq); + free_irq(i2c->irq, &fusion_F0710A); + input_unregister_device(fusion_F0710A.input); + i2c_set_clientdata(i2c, NULL); + + dev_info(&i2c->dev, "driver removed\n"); + + return 0; +} + +static struct i2c_device_id fusion_F0710A_id[] = { + {"fusion_F0710A", 0}, + {}, +}; + + +static const struct of_device_id fusion_F0710A_dt_ids[] = { + { + .compatible = "touchrevolution,fusion-f0710a", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, fusion_F0710A_dt_ids); + +static const struct dev_pm_ops fusion_F0710A_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(fusion_F0710A_suspend, fusion_F0710A_resume) +}; + +static struct i2c_driver fusion_F0710A_i2c_drv = { + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .pm = &fusion_F0710A_pm_ops, + .of_match_table = fusion_F0710A_dt_ids, + }, + .probe = fusion_F0710A_probe, + .remove = fusion_F0710A_remove, + .id_table = fusion_F0710A_id, + .address_list = normal_i2c, +}; + +static int __init fusion_F0710A_init( void ) +{ + int ret; + + memset(&fusion_F0710A, 0, sizeof(fusion_F0710A)); + + /* Probe for fusion_F0710A on I2C. */ + ret = i2c_add_driver(&fusion_F0710A_i2c_drv); + if (ret < 0) { + printk(KERN_WARNING DRV_NAME " can't add i2c driver: %d\n", ret); + } + + return ret; +} + +static void __exit fusion_F0710A_exit( void ) +{ + i2c_del_driver(&fusion_F0710A_i2c_drv); +} +module_init(fusion_F0710A_init); +module_exit(fusion_F0710A_exit); + +MODULE_DESCRIPTION("fusion_F0710A Touchscreen Driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/input/touchscreen/fusion_F0710A.h b/drivers/input/touchscreen/fusion_F0710A.h new file mode 100644 index 000000000000..85f8210345a9 --- /dev/null +++ b/drivers/input/touchscreen/fusion_F0710A.h @@ -0,0 +1,87 @@ +/* + * "fusion_F0710A" touchscreen driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* I2C slave address */ +#define fusion_F0710A_I2C_SLAVE_ADDR 0x10 + +/* I2C registers */ +#define fusion_F0710A_DATA_INFO 0x00 + +/* First Point*/ +#define fusion_F0710A_POS_X1_HI 0x01 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_X1_LO 0x02 /* 16-bit register, LSB */ +#define fusion_F0710A_POS_Y1_HI 0x03 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_Y1_LO 0x04 /* 16-bit register, LSB */ +#define fusion_F0710A_FIR_PRESS 0X05 +#define fusion_F0710A_FIR_TIDTS 0X06 + +/* Second Point */ +#define fusion_F0710A_POS_X2_HI 0x07 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_X2_LO 0x08 /* 16-bit register, LSB */ +#define fusion_F0710A_POS_Y2_HI 0x09 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_Y2_LO 0x0A /* 16-bit register, LSB */ +#define fusion_F0710A_SEC_PRESS 0x0B +#define fusion_F0710A_SEC_TIDTS 0x0C + +#define fusion_F0710A_VIESION_INFO_LO 0X0E +#define fusion_F0710A_VIESION_INFO 0X0F + +#define fusion_F0710A_RESET 0x10 +#define fusion_F0710A_SCAN_COMPLETE 0x11 + + +#define fusion_F0710A_VIESION_10 0 +#define fusion_F0710A_VIESION_07 1 +#define fusion_F0710A_VIESION_43 2 + +/* fusion_F0710A 10 inch panel */ +#define fusion_F0710A10_XMAX 2275 +#define fusion_F0710A10_YMAX 1275 +#define fusion_F0710A10_REV 1 + +/* fusion_F0710A 7 inch panel */ +#define fusion_F0710A07_XMAX 1500 +#define fusion_F0710A07_YMAX 900 +#define fusion_F0710A07_REV 0 + +/* fusion_F0710A 4.3 inch panel */ +#define fusion_F0710A43_XMAX 900 +#define fusion_F0710A43_YMAX 500 +#define fusion_F0710A43_REV 0 + +#define fusion_F0710A_SAVE_PT1 0x1 +#define fusion_F0710A_SAVE_PT2 0x2 + + + +/* fusion_F0710A touch screen information */ +struct fusion_F0710A_info { + int xres; /* x resolution */ + int yres; /* y resolution */ + int xy_reverse; /* if need reverse in the x,y value x=xres-1-x, y=yres-1-y*/ +}; + +struct fusion_F0710A_data { + struct fusion_F0710A_info info; + struct i2c_client *client; + struct workqueue_struct *workq; + struct input_dev *input; + u16 x1; + u16 y1; + u8 z1; + u8 tip1; + u8 tid1; + u16 x2; + u16 y2; + u8 z2; + u8 tip2; + u8 tid2; + u8 f_num; + u8 save_points; +}; + diff --git a/drivers/input/touchscreen/stmpe-ts.c b/drivers/input/touchscreen/stmpe-ts.c index 59e81b00f244..5979aafd43d8 100644 --- a/drivers/input/touchscreen/stmpe-ts.c +++ b/drivers/input/touchscreen/stmpe-ts.c @@ -50,17 +50,6 @@ #define STMPE_IRQ_TOUCH_DET 0 -#define SAMPLE_TIME(x) ((x & 0xf) << 4) -#define MOD_12B(x) ((x & 0x1) << 3) -#define REF_SEL(x) ((x & 0x1) << 1) -#define ADC_FREQ(x) (x & 0x3) -#define AVE_CTRL(x) ((x & 0x3) << 6) -#define DET_DELAY(x) ((x & 0x7) << 3) -#define SETTLING(x) (x & 0x7) -#define FRACTION_Z(x) (x & 0x7) -#define I_DRIVE(x) (x & 0x1) -#define OP_MODE(x) ((x & 0x7) << 1) - #define STMPE_TS_NAME "stmpe-ts" #define XY_MASK 0xfff @@ -165,7 +154,7 @@ static irqreturn_t stmpe_ts_handler(int irq, void *data) STMPE_TSC_CTRL_TSC_EN, STMPE_TSC_CTRL_TSC_EN); /* start polling for touch_det to detect release */ - schedule_delayed_work(&ts->work, HZ / 50); + schedule_delayed_work(&ts->work, HZ / 10); return IRQ_HANDLED; } diff --git a/drivers/input/touchscreen/tsc2004.c b/drivers/input/touchscreen/tsc2004.c new file mode 100644 index 000000000000..0263f849f9f7 --- /dev/null +++ b/drivers/input/touchscreen/tsc2004.c @@ -0,0 +1,554 @@ +/* + * drivers/input/touchscreen/tsc2004.c + * + * Copyright (C) 2009 Texas Instruments Inc + * Author: Vaibhav Hiremath <hvaibhav@ti.com> + * + * Using code from: + * - tsc2007.c + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/of_gpio.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/i2c/tsc2007.h> + +static int calibration[7]; +module_param_array(calibration, int, NULL, S_IRUGO | S_IWUSR); + +static void translate(u16 *px, u16 *py) +{ + int x, y, x1, y1; + if (calibration[6]) { + x1 = *px; + y1 = *py; + + x = calibration[0] * x1 + + calibration[1] * y1 + + calibration[2]; + x /= calibration[6]; + if (x < 0) + x = 0; + y = calibration[3] * x1 + + calibration[4] * y1 + + calibration[5]; + y /= calibration[6]; + if (y < 0) + y = 0; + *px = x ; + *py = y ; + } +} + +#define TS_POLL_DELAY 1 /* ms delay between samples */ +#define TS_POLL_PERIOD 1 /* ms delay between samples */ + +/* Control byte 0 */ +#define TSC2004_CMD0(addr, pnd, rw) ((addr<<3)|(pnd<<1)|rw) +/* Control byte 1 */ +#define TSC2004_CMD1(cmd, mode, rst) ((1<<7)|(cmd<<4)|(mode<<2)|(rst<<1)) + +/* Command Bits */ +#define READ_REG 1 +#define WRITE_REG 0 +#define SWRST_TRUE 1 +#define SWRST_FALSE 0 +#define PND0_TRUE 1 +#define PND0_FALSE 0 + +/* Converter function mapping */ +enum convertor_function { + MEAS_X_Y_Z1_Z2, /* Measure X,Y,z1 and Z2: 0x0 */ + MEAS_X_Y, /* Measure X and Y only: 0x1 */ + MEAS_X, /* Measure X only: 0x2 */ + MEAS_Y, /* Measure Y only: 0x3 */ + MEAS_Z1_Z2, /* Measure Z1 and Z2 only: 0x4 */ + MEAS_AUX, /* Measure Auxillary input: 0x5 */ + MEAS_TEMP1, /* Measure Temparature1: 0x6 */ + MEAS_TEMP2, /* Measure Temparature2: 0x7 */ + MEAS_AUX_CONT, /* Continuously measure Auxillary input: 0x8 */ + X_DRV_TEST, /* X-Axis drivers tested 0x9 */ + Y_DRV_TEST, /* Y-Axis drivers tested 0xA */ + /*Command Reserved*/ + SHORT_CKT_TST = 0xC, /* Short circuit test: 0xC */ + XP_XN_DRV_STAT, /* X+,Y- drivers status: 0xD */ + YP_YN_DRV_STAT, /* X+,Y- drivers status: 0xE */ + YP_XN_DRV_STAT /* Y+,X- drivers status: 0xF */ +}; + +/* Register address mapping */ +enum register_address { + X_REG, /* X register: 0x0 */ + Y_REG, /* Y register: 0x1 */ + Z1_REG, /* Z1 register: 0x2 */ + Z2_REG, /* Z2 register: 0x3 */ + AUX_REG, /* AUX register: 0x4 */ + TEMP1_REG, /* Temp1 register: 0x5 */ + TEMP2_REG, /* Temp2 register: 0x6 */ + STAT_REG, /* Status Register: 0x7 */ + AUX_HGH_TH_REG, /* AUX high threshold register: 0x8 */ + AUX_LOW_TH_REG, /* AUX low threshold register: 0x9 */ + TMP_HGH_TH_REG, /* Temp high threshold register:0xA */ + TMP_LOW_TH_REG, /* Temp low threshold register: 0xB */ + CFR0_REG, /* Configuration register 0: 0xC */ + CFR1_REG, /* Configuration register 1: 0xD */ + CFR2_REG, /* Configuration register 2: 0xE */ + CONV_FN_SEL_STAT /* Convertor function select register: 0xF */ +}; + +/* Supported Resolution modes */ +enum resolution_mode { + MODE_10BIT, /* 10 bit resolution */ + MODE_12BIT /* 12 bit resolution */ +}; + +/* Configuraton register bit fields */ +/* CFR0 */ +#define PEN_STS_CTRL_MODE (1<<15) +#define ADC_STS (1<<14) +#define RES_CTRL (1<<13) +#define ADC_CLK_4MHZ (0<<11) +#define ADC_CLK_2MHZ (1<<11) +#define ADC_CLK_1MHZ (2<<11) +#define PANEL_VLTG_STB_TIME_0US (0<<8) +#define PANEL_VLTG_STB_TIME_100US (1<<8) +#define PANEL_VLTG_STB_TIME_500US (2<<8) +#define PANEL_VLTG_STB_TIME_1MS (3<<8) +#define PANEL_VLTG_STB_TIME_5MS (4<<8) +#define PANEL_VLTG_STB_TIME_10MS (5<<8) +#define PANEL_VLTG_STB_TIME_50MS (6<<8) +#define PANEL_VLTG_STB_TIME_100MS (7<<8) + +/* CFR2 */ +#define PINTS1 (1<<15) +#define PINTS0 (1<<14) +#define MEDIAN_VAL_FLTR_SIZE_1 (0<<12) +#define MEDIAN_VAL_FLTR_SIZE_3 (1<<12) +#define MEDIAN_VAL_FLTR_SIZE_7 (2<<12) +#define MEDIAN_VAL_FLTR_SIZE_15 (3<<12) +#define AVRG_VAL_FLTR_SIZE_1 (0<<10) +#define AVRG_VAL_FLTR_SIZE_3_4 (1<<10) +#define AVRG_VAL_FLTR_SIZE_7_8 (2<<10) +#define AVRG_VAL_FLTR_SIZE_16 (3<<10) +#define MAV_FLTR_EN_X (1<<4) +#define MAV_FLTR_EN_Y (1<<3) +#define MAV_FLTR_EN_Z (1<<2) + +#define MAX_12BIT ((1 << 12) - 1) +#define MEAS_MASK 0xFFF + +struct ts_event { + u16 x; + u16 y; + u16 z1, z2; +}; + +struct tsc2004 { + struct input_dev *input; + char phys[32]; + struct delayed_work work; + + struct i2c_client *client; + + u16 x_plate_ohms; + + bool pendown; + int irq; + + int (*get_pendown_state)(void); + void (*clear_penirq)(void); +}; + +static inline int tsc2004_read_xyz_data(struct tsc2004 *tsc, u8 cmd) +{ + s32 data; + u16 val; + + data = i2c_smbus_read_word_data(tsc->client, cmd); + if (data < 0) { + dev_err(&tsc->client->dev, "i2c io (read) error: %d\n", data); + return data; + } + + /* + * We need to swap byte order for little-endian cpus. + * 12 bit precision, high 4 bits should be zero + */ + val = be16_to_cpu(data) & 0xfff; + + dev_dbg(&tsc->client->dev, "data: 0x%x, val: 0x%x\n", data, val); + + return val; +} + +static inline int tsc2004_write_word_data(struct tsc2004 *tsc, u8 cmd, u16 data) +{ + u16 val; + + val = cpu_to_be16(data); + return i2c_smbus_write_word_data(tsc->client, cmd, val); +} + +static inline int tsc2004_write_cmd(struct tsc2004 *tsc, u8 value) +{ + return i2c_smbus_write_byte(tsc->client, value); +} + +static int tsc2004_prepare_for_reading(struct tsc2004 *ts) +{ + int err; + int cmd, data; + int retries ; + + /* Reset the TSC, configure for 12 bit */ + retries = 0 ; + do { + /* Reset the TSC, configure for 12 bit */ + cmd = TSC2004_CMD1(MEAS_X_Y_Z1_Z2, MODE_12BIT, SWRST_TRUE); + err = tsc2004_write_cmd(ts, cmd); + if (err < 0) + printk (KERN_ERR "%s: write_cmd %d\n", __func__, err ); + } while ( (err < 0) && (3 < retries++) ); + + if (err < 0) + return err ; + + /* Enable interrupt for PENIRQ and DAV */ + cmd = TSC2004_CMD0(CFR2_REG, PND0_FALSE, WRITE_REG); + data = PINTS1 | PINTS0 | MEDIAN_VAL_FLTR_SIZE_15 | + AVRG_VAL_FLTR_SIZE_7_8 | MAV_FLTR_EN_X | MAV_FLTR_EN_Y | + MAV_FLTR_EN_Z; + err = tsc2004_write_word_data(ts, cmd, data); + if (err < 0) + return err; + + /* Configure the TSC in TSMode 1 */ + cmd = TSC2004_CMD0(CFR0_REG, PND0_FALSE, WRITE_REG); + data = PEN_STS_CTRL_MODE | ADC_CLK_2MHZ | PANEL_VLTG_STB_TIME_1MS; + err = tsc2004_write_word_data(ts, cmd, data); + if (err < 0) + return err; + + /* Enable x, y, z1 and z2 conversion functions */ + cmd = TSC2004_CMD1(MEAS_X_Y_Z1_Z2, MODE_12BIT, SWRST_FALSE); + err = tsc2004_write_cmd(ts, cmd); + if (err < 0) + return err; + + return 0; +} + +static void tsc2004_read_values(struct tsc2004 *tsc, struct ts_event *tc) +{ + int cmd; + + /* Read X Measurement */ + cmd = TSC2004_CMD0(X_REG, PND0_FALSE, READ_REG); + tc->x = tsc2004_read_xyz_data(tsc, cmd); + + /* Read Y Measurement */ + cmd = TSC2004_CMD0(Y_REG, PND0_FALSE, READ_REG); + tc->y = tsc2004_read_xyz_data(tsc, cmd); + + /* Read Z1 Measurement */ + cmd = TSC2004_CMD0(Z1_REG, PND0_FALSE, READ_REG); + tc->z1 = tsc2004_read_xyz_data(tsc, cmd); + + /* Read Z2 Measurement */ + cmd = TSC2004_CMD0(Z2_REG, PND0_FALSE, READ_REG); + tc->z2 = tsc2004_read_xyz_data(tsc, cmd); + + + tc->x &= MEAS_MASK; + tc->y &= MEAS_MASK; + tc->z1 &= MEAS_MASK; + tc->z2 &= MEAS_MASK; + + /* Prepare for touch readings */ + if (tsc2004_prepare_for_reading(tsc) < 0) + dev_dbg(&tsc->client->dev, "Failed to prepare TSC for next" + "reading\n"); +} + +static u32 tsc2004_calculate_pressure(struct tsc2004 *tsc, struct ts_event *tc) +{ + u32 rt = 0; + + /* range filtering */ + if (tc->x == MAX_12BIT) + tc->x = 0; + + if (likely(tc->x && tc->z1)) { + /* compute touch pressure resistance using equation #1 */ + rt = tc->z2 - tc->z1; + rt *= tc->x; + rt *= tsc->x_plate_ohms; + rt /= tc->z1; + rt = (rt + 2047) >> 12; + } + + return rt; +} + +static void tsc2004_send_up_event(struct tsc2004 *tsc) +{ + struct input_dev *input = tsc->input; + + dev_dbg(&tsc->client->dev, "UP\n"); + + input_report_key(input, BTN_TOUCH, 0); + input_report_abs(input, ABS_PRESSURE, 0); + input_sync(input); +} + +static void tsc2004_work(struct work_struct *work) +{ + struct tsc2004 *ts = + container_of(to_delayed_work(work), struct tsc2004, work); + struct ts_event tc; + u32 rt; + + /* + * NOTE: We can't rely on the pressure to determine the pen down + * state, even though this controller has a pressure sensor. + * The pressure value can fluctuate for quite a while after + * lifting the pen and in some cases may not even settle at the + * expected value. + * + * The only safe way to check for the pen up condition is in the + * work function by reading the pen signal state (it's a GPIO + * and IRQ). Unfortunately such callback is not always available, + * in that case we have rely on the pressure anyway. + */ + if (ts->get_pendown_state) { + if (unlikely(!ts->get_pendown_state())) { + tsc2004_send_up_event(ts); + ts->pendown = false; + goto out; + } + + dev_dbg(&ts->client->dev, "pen is still down\n"); + } + + tsc2004_read_values(ts, &tc); + + rt = tsc2004_calculate_pressure(ts, &tc); + if (rt > MAX_12BIT) { + /* + * Sample found inconsistent by debouncing or pressure is + * beyond the maximum. Don't report it to user space, + * repeat at least once more the measurement. + */ + dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt); + goto out; + + } + + if (rt) { + struct input_dev *input = ts->input; + + translate(&tc.x, &tc.y); + + if (!ts->pendown) { + dev_dbg(&ts->client->dev, "DOWN\n"); + + input_report_key(input, BTN_TOUCH, 1); + ts->pendown = true; + } + + input_report_abs(input, ABS_X, tc.x); + input_report_abs(input, ABS_Y, tc.y); + input_report_abs(input, ABS_PRESSURE, rt); + + input_sync(input); + + dev_dbg(&ts->client->dev, "point(%4d,%4d), pressure (%4u)\n", + tc.x, tc.y, rt); + + } else if (!ts->get_pendown_state && ts->pendown) { + /* + * We don't have callback to check pendown state, so we + * have to assume that since pressure reported is 0 the + * pen was lifted up. + */ + tsc2004_send_up_event(ts); + ts->pendown = false; + } + + out: + if (ts->pendown) + schedule_delayed_work(&ts->work, + msecs_to_jiffies(TS_POLL_PERIOD)); + else + enable_irq(ts->irq); +} + +static irqreturn_t tsc2004_irq(int irq, void *handle) +{ + struct tsc2004 *ts = handle; + + if (!ts->get_pendown_state || likely(ts->get_pendown_state())) { + disable_irq_nosync(ts->irq); + schedule_delayed_work(&ts->work, + msecs_to_jiffies(TS_POLL_DELAY)); + } + + if (ts->clear_penirq) + ts->clear_penirq(); + + return IRQ_HANDLED; +} + +static void tsc2004_free_irq(struct tsc2004 *ts) +{ + free_irq(ts->irq, ts); + if (cancel_delayed_work_sync(&ts->work)) { + /* + * Work was pending, therefore we need to enable + * IRQ here to balance the disable_irq() done in the + * interrupt handler. + */ + enable_irq(ts->irq); + } +} + +static int tsc2004_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct tsc2004 *ts; + struct input_dev *input_dev; + int err; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_WORD_DATA)) + return -EIO; + + ts = kzalloc(sizeof(struct tsc2004), GFP_KERNEL); + input_dev = input_allocate_device(); + if (!ts || !input_dev) { + err = -ENOMEM; + goto err_free_mem; + } + + ts->client = client; + ts->irq = client->irq; + ts->input = input_dev; + INIT_DELAYED_WORK(&ts->work, tsc2004_work); + + ts->x_plate_ohms = 500; + + snprintf(ts->phys, sizeof(ts->phys), + "%s/input0", dev_name(&client->dev)); + + input_dev->name = "tsc2004"; + input_dev->phys = ts->phys; + input_dev->id.bustype = BUS_I2C; + + input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + + input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, 0, 0); + input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, 0, 0); + input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0); + + err = request_irq(ts->irq, tsc2004_irq, IRQF_TRIGGER_FALLING, + client->dev.driver->name, ts); + if (err < 0) { + dev_err(&client->dev, "irq %d busy(%d)?\n", ts->irq,err); + goto err_free_mem; + } + + /* Prepare for touch readings */ + err = tsc2004_prepare_for_reading(ts); + if (err < 0) + goto err_free_irq; + + err = input_register_device(input_dev); + if (err) + goto err_free_irq; + + i2c_set_clientdata(client, ts); + + return 0; + + err_free_irq: + tsc2004_free_irq(ts); + + err_free_mem: + input_free_device(input_dev); + kfree(ts); + return err; +} + +static int tsc2004_remove(struct i2c_client *client) +{ + struct tsc2004 *ts = i2c_get_clientdata(client); + + tsc2004_free_irq(ts); + + input_unregister_device(ts->input); + kfree(ts); + + return 0; +} + +static struct i2c_device_id tsc2004_idtable[] = { + { "tsc2004", 0 }, + { } +}; + +MODULE_DEVICE_TABLE(i2c, tsc2004_idtable); + +static const struct of_device_id tsc2004_dt_ids[] = { + { + .compatible = "tsc2004,tsc2004-touch", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, tsc2004_dt_ids); + +static struct i2c_driver tsc2004_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "tsc2004", + .of_match_table = tsc2004_dt_ids, + }, + .id_table = tsc2004_idtable, + .probe = tsc2004_probe, + .remove = tsc2004_remove, +}; + +static int __init tsc2004_init(void) +{ + return i2c_add_driver(&tsc2004_driver); +} + +static void __exit tsc2004_exit(void) +{ + i2c_del_driver(&tsc2004_driver); +} + +module_init(tsc2004_init); +module_exit(tsc2004_exit); + +MODULE_AUTHOR("Vaibhav Hiremath <hvaibhav@ti.com>"); +MODULE_DESCRIPTION("TSC2004 TouchScreen Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/pci/Kconfig b/drivers/media/pci/Kconfig index 53196f1366f3..0e75c97b835f 100644 --- a/drivers/media/pci/Kconfig +++ b/drivers/media/pci/Kconfig @@ -19,6 +19,7 @@ if MEDIA_ANALOG_TV_SUPPORT source "drivers/media/pci/ivtv/Kconfig" source "drivers/media/pci/zoran/Kconfig" source "drivers/media/pci/saa7146/Kconfig" +source "drivers/media/pci/TW68/Kconfig" endif if MEDIA_ANALOG_TV_SUPPORT || MEDIA_DIGITAL_TV_SUPPORT diff --git a/drivers/media/pci/Makefile b/drivers/media/pci/Makefile index 35cc57862c01..3734de9f3044 100644 --- a/drivers/media/pci/Makefile +++ b/drivers/media/pci/Makefile @@ -15,6 +15,7 @@ obj-y += ttpci/ \ obj-$(CONFIG_VIDEO_IVTV) += ivtv/ obj-$(CONFIG_VIDEO_ZORAN) += zoran/ +obj-$(CONFIG_VIDEO_TW68) += TW68/ obj-$(CONFIG_VIDEO_CX18) += cx18/ obj-$(CONFIG_VIDEO_CX23885) += cx23885/ obj-$(CONFIG_VIDEO_CX25821) += cx25821/ diff --git a/drivers/media/pci/TW68/Kconfig b/drivers/media/pci/TW68/Kconfig new file mode 100644 index 000000000000..44a6fd0dd66d --- /dev/null +++ b/drivers/media/pci/TW68/Kconfig @@ -0,0 +1,10 @@ +config VIDEO_TW68 + tristate "TW686x cards" + depends on PCI + select VIDEOBUF_DMA_SG + select VIDEOBUF_VMALLOC + help + Support for TW6869 PCIe cards. + + Say Y or M if you own such a device and want to use it. + diff --git a/drivers/media/pci/TW68/Makefile b/drivers/media/pci/TW68/Makefile new file mode 100644 index 000000000000..98f33b156f0f --- /dev/null +++ b/drivers/media/pci/TW68/Makefile @@ -0,0 +1,3 @@ +tw68v-objs := TW68-core.o TW68-video.o TW68-ALSA.o + +obj-$(CONFIG_VIDEO_TW68) += tw68v.o diff --git a/drivers/media/pci/TW68/TW68-ALSA.c b/drivers/media/pci/TW68/TW68-ALSA.c new file mode 100644 index 000000000000..0ddd7f73564b --- /dev/null +++ b/drivers/media/pci/TW68/TW68-ALSA.c @@ -0,0 +1,614 @@ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Thanks to yiliang for variable audio packet length and more audio + * formats support. + */ +#define DEBUG +#include <linux/module.h> +#include <linux/vmalloc.h> +#include <sound/core.h> +#include <sound/control.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> + +#include "TW68.h" +#include "TW68_defines.h" + + +MODULE_DESCRIPTION("alsa driver module for tw68 PCIe capture chip"); +MODULE_AUTHOR("Simon Xu"); +MODULE_LICENSE("GPL"); + +/* + * Main chip structure + */ +struct snd_card_tw68 { + struct snd_card *card; + spinlock_t mixer_lock; + + struct pci_dev *pci; + struct TW68_dev *dev; + + struct snd_pcm *TW68_pcm; + struct snd_pcm_substream *substream[10]; + spinlock_t lock; + u32 audio_dma_size; + u32 audio_rate; + u32 audio_frame_bits; + u32 audio_lock_mask; + u32 last_audio_PB; + u8 period_insert[8]; +}; + + +// static struct snd_card *snd_TW68_cards[SNDRV_CARDS]; + +static long TW68_audio_nPCM = 0; + +/* + * ALSA hardware capabilities definition + */ + +static struct snd_pcm_hardware snd_card_tw68_pcm_hw = +{ + .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID), + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8, + .rates = SNDRV_PCM_RATE_8000_48000, + .rate_min = 8000, + .rate_max = 48000, + .channels_min = 1, + .channels_max = 1, + .buffer_bytes_max = AUDIO_CH_BUF_SIZE, + .period_bytes_min = 64, + .period_bytes_max = 4096, + .periods_min = 4, + .periods_max = 256, +}; + + +/* + * TW68 audio DMA IRQ handler + * + * Called whenever we get an TW68 audio interrupt + * Handles shifting between the 2 buffers, manages the read counters, + * and notifies ALSA when periods elapse + * + */ + +void TW68_alsa_irq(struct TW68_dev *dev, u32 dma_status, u32 pb_status) +{ + u32 dma_base = dev->m_AudioBuffer.dma; + struct snd_card_tw68 *ctw = (struct snd_card_tw68 *)dev->card->private_data; + u32 mask = ((dev->videoDMA_ID & dma_status) & 0xff00) >> 8; + u32 change = pb_status ^ ctw->last_audio_PB; + + // pr_debug("%s: card pcm %p dma_status %x pb_status %x \n", __func__, + // ctw->TW68_pcm, dma_status, pb_status); + while (mask) { + int k = __fls(mask); + u32 dma_ch = dma_base + AUDIO_CH_BUF_SIZE * k; + int period = ctw->period_insert[k]; + u32 reg_addr = DMA_CH8_CONFIG_P + k * 2; + struct snd_pcm_substream *substream = ctw->substream[k]; + u32 buffer_bytes = snd_pcm_lib_buffer_bytes(substream); + u32 smask = (1 << (k + 8)); + u32 offset = ctw->audio_dma_size * period; + + mask &= ~(1 << k); + if (!(ctw->last_audio_PB & smask)) + reg_addr++; + reg_writel(reg_addr, dma_ch + offset); + period++; + offset += ctw->audio_dma_size; + if (offset >= buffer_bytes) { + period = 0; + offset = 0; + } + + if (!(change & smask)) { + reg_addr ^= 1; + reg_writel(reg_addr, dma_ch + offset); + period++; + offset += ctw->audio_dma_size; + if (offset >= buffer_bytes) + period = 0; + pr_debug("%s: 2 periods elapsed\n", __func__); + } + ctw->period_insert[k] = period; + ctw->last_audio_PB ^= change & smask; + snd_pcm_period_elapsed(substream); + } +} + + +/* + * ALSA capture trigger + * + * - One of the ALSA capture callbacks. + * + * Called whenever a capture is started or stopped. Must be defined, + * + * + */ + +static int snd_card_TW68_capture_trigger(struct snd_pcm_substream *substream, int cmd) +{ + // DMA start bit based on ss id + u32 mask = (1 << (substream->number + 8)); + u32 dwReg; + u32 dwRegF; + struct snd_card_tw68 *ctw = snd_pcm_substream_chip(substream); + struct TW68_dev *dev = ctw->dev; + int start; + unsigned long flags; + + if (!ctw) { + pr_err("%s: can't find device struct.\n", __func__); + return -ENODEV; + } + + //pr_debug("%s: cmd=%d ctw 0x%p\n", __func__, cmd, ctw); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + start = 1; + break; + + case SNDRV_PCM_TRIGGER_STOP: + start = 0; + break; + + default: + pr_debug("%s: cmd %d not supported\n", __func__, cmd); + return -EINVAL; + } + spin_lock_irqsave(&dev->slock, flags); + dwReg = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = reg_readl(DMA_CMD); + if (start) { + dev->videoDMA_ID |= mask; + dev->videoCap_ID |= mask; + dwReg |= mask; + dwRegF |= mask | (1<<31); + } else { + dev->videoDMA_ID &= ~mask; + dev->videoCap_ID &= ~mask; + dwReg &= ~mask; + dwRegF &= ~mask; + } + reg_writel(DMA_CHANNEL_ENABLE, dwReg); + reg_writel(DMA_CMD, dwRegF); + spin_unlock_irqrestore(&dev->slock, flags); +// pr_debug("%s: cmd %X DMA_CHANNEL_ENABLE 0x%x 0x%x\n", __func__, cmd, dwReg, dwRegF); + return 0; +} + + + +/* + * ALSA PCM preparation + * + * - One of the ALSA capture callbacks. + * + * Called right after the capture device is opened, this function configures + * the buffer using the previously defined functions, allocates the memory, + * sets up the hardware registers, and then starts the DMA. When this function + * returns, the audio should be flowing. + * Audio sample rate bits setup + */ + +static int snd_card_TW68_capture_prepare(struct snd_pcm_substream * substream) +{ + int k = substream->number; + u32 dma_ch; + u32 pb_status; + u32 mask = (1 << (k + 8)); + u32 sr = substream->runtime->rate; + u32 frame_bits = substream->runtime->frame_bits; + u32 audio_dma_size; + struct snd_card_tw68 *ctw = snd_pcm_substream_chip(substream); + struct TW68_dev *dev; + __u32 __iomem *chbase; + u32 reg_addr = DMA_CH8_CONFIG_P + k * 2; + + if (!ctw) { + pr_err("%s: can't find device struct.\n", __func__); + return -ENODEV; + } + dev = ctw->dev; + chbase = dev->lmmio + ((k & 4) * 0x40); + writel(readl(chbase + POWER_DOWN_CTRL) & ~0x90, chbase + POWER_DOWN_CTRL); + audio_dma_size = snd_pcm_lib_period_bytes(substream); + ctw->audio_lock_mask &= ~mask; + if (((ctw->audio_dma_size == audio_dma_size) && + (ctw->audio_rate == sr) && + (ctw->audio_frame_bits == frame_bits)) || + !ctw->audio_lock_mask) { + u64 q; + u32 ctrl1, ctrl2, ctrl3; + + ctw->audio_dma_size = audio_dma_size; + ctw->audio_rate = sr; + ctw->audio_frame_bits = frame_bits; + ctw->audio_lock_mask |= mask; + + q = (u64)125000000 << 16; + do_div(q, sr); + ctrl2 = (u32)q; + ctrl1 = (ctw->audio_dma_size << 19) | (((ctrl2 >> 16) & 0x3fff) << 5) | (1 << 0); + ctrl3 = reg_readl(AUDIO_CTRL3); + if (frame_bits == 8) + ctrl3 |= 0x100; + else + ctrl3 &= ~0x100; + reg_writel(AUDIO_CTRL1, ctrl1); + reg_writel(AUDIO_CTRL2, ctrl2); + reg_writel(AUDIO_CTRL3, ctrl3); + pr_debug("%s: AUDIO_CTRL1: 0x%x 0x%x\n", __func__, reg_readl(AUDIO_CTRL1), ctrl1); + pr_debug("%s: AUDIO_CTRL2: 0x%x 0x%x\n", __func__, reg_readl(AUDIO_CTRL2), ctrl2); + pr_debug("%s: AUDIO_CTRL3: 0x%x 0x%x\n", __func__, reg_readl(AUDIO_CTRL3), ctrl3); + pr_debug("%s: audio_dma_size=0x%x lock=0x%x\n", + __func__, ctw->audio_dma_size, ctw->audio_lock_mask); + } else { + pr_err("%s: can't change size=%x %x, rate=%d %d frame_bits %d %d lock=%x\n", + __func__, ctw->audio_dma_size, audio_dma_size, + ctw->audio_rate, sr, + ctw->audio_frame_bits, frame_bits, ctw->audio_lock_mask); + return -EINVAL; + } + + dma_ch = dev->m_AudioBuffer.dma + AUDIO_CH_BUF_SIZE * k; + pb_status = reg_readl(DMA_PB_STATUS) & mask; + ctw->last_audio_PB &= ~mask; + ctw->last_audio_PB |= pb_status; + if (!pb_status) + reg_addr++; + reg_writel(reg_addr, dma_ch); + reg_addr ^= 1; + reg_writel(reg_addr, dma_ch + ctw->audio_dma_size); + ctw->period_insert[k] = 2; + + writel(0xc0, chbase + AUDIO_DET_PERIOD); + writel(0, chbase + AUDIO_DET_THRESHOLD1); + writel(0, chbase + AUDIO_DET_THRESHOLD2); + pr_debug("%s: dev %p substream->runtime->rate %d\n", __func__, dev, sr); + return 0; +} + +/* + * ALSA pointer fetching + * + * - One of the ALSA capture callbacks. + * + * Called whenever a period elapses, it must return the current hardware + * position of the buffer. + * Also resets the read counter used to prevent overruns + * + */ + +static snd_pcm_uframes_t snd_card_TW68_capture_pointer( + struct snd_pcm_substream * substream) +{ + struct snd_card_tw68 *ctw = snd_pcm_substream_chip(substream); + int period = ctw->period_insert[substream->number]; + snd_pcm_uframes_t frames; + + period -= 2; + if (period < 0) + period += substream->runtime->periods; + frames = period * ctw->audio_dma_size; + if (ctw->audio_frame_bits != 8) + frames >>= 1; + return frames; +} + +/* + * ALSA hardware params + * + * - One of the ALSA capture callbacks. + * + * Called on initialization, right before the PCM preparation + * + */ + +static int snd_card_TW68_hw_params(struct snd_pcm_substream * substream, + struct snd_pcm_hw_params * hw_params) +{ + pr_debug("%s\n", __func__); + return 0; +} + +/* + * ALSA hardware release + * + * - One of the ALSA capture callbacks. + * + * Called after closing the device, but before snd_card_TW68_capture_close + * It stops the DMA audio and releases the buffers. + * + */ + +static int snd_card_TW68_hw_free(struct snd_pcm_substream * substream) +{ + pr_debug("%s\n", __func__); + return 0; +} + +/* + * ALSA capture finish + * + * - One of the ALSA capture callbacks. + * + * Called after closing the device. + * + */ + +static int snd_card_TW68_capture_close(struct snd_pcm_substream * substream) +{ + int k = substream->number; + u32 mask = (1 << (k + 8)); + struct snd_card_tw68 *ctw = snd_pcm_substream_chip(substream); + + pr_debug("%s\n", __func__); + ctw->audio_lock_mask &= ~mask; + return 0; +} + +/* + * ALSA capture start + * + * - One of the ALSA capture callbacks. + * + * Called when opening the device. It creates and populates the PCM structure + * + */ + +static int snd_card_TW68_capture_open(struct snd_pcm_substream * substream) +{ + int k = substream->number; + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_card_tw68 *ctw = snd_pcm_substream_chip(substream); + struct TW68_dev *dev; + int err; + + if (!ctw) { + pr_err("%s: can't find device struct\n", __func__); + return -ENODEV; + } + dev = ctw->dev; + + runtime->hw = snd_card_tw68_pcm_hw; + runtime->dma_area = (u8 *)dev->m_AudioBuffer.cpu + k * AUDIO_CH_BUF_SIZE; + runtime->dma_bytes = AUDIO_CH_BUF_SIZE; + + err = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) + return err; + + /* Align to 4 bytes */ + err = snd_pcm_hw_constraint_step(runtime, 0, + SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4); + if (err < 0) + return err; + pr_debug("%s: substream %p N:%d %s rate %d \n", __func__, + substream, substream->number, substream->name, runtime->rate ); + + return 0; +} + + +/* + * ALSA capture callbacks definition + */ + +static struct snd_pcm_ops snd_card_TW68_capture_ops = { + .open = snd_card_TW68_capture_open, + .close = snd_card_TW68_capture_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_card_TW68_hw_params, + .hw_free = snd_card_TW68_hw_free, + .prepare = snd_card_TW68_capture_prepare, + .trigger = snd_card_TW68_capture_trigger, + .pointer = snd_card_TW68_capture_pointer, + //.page = snd_card_TW68_page, +}; + +/* 7 bits, 0 : .5, 127 : 2.484375, n : .5 + n/64 */ +static int gain_info(struct snd_kcontrol *ctl, + struct snd_ctl_elem_info *info) +{ + info->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + info->count = 1; + info->value.integer.min = 0; + info->value.integer.max = 127; + return 0; +} + +static int gain_get(struct snd_kcontrol *ctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct TW68_dev *dev = ctl->private_data; + int k = snd_ctl_get_ioffidx(ctl, &ucontrol->id); + __u32 __iomem *chbase = dev->lmmio + ((k & 4) * 0x40); + u32 gain; + + gain = readl(chbase + AUDIO_GAIN_CH0 + (k & 3)); + ucontrol->value.integer.value[0] = gain; + pr_debug("%s: gain[%d]=%d\n", __func__, k, gain); + return 0; +} + +static int gain_put(struct snd_kcontrol *ctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct TW68_dev *dev = ctl->private_data; + int k = snd_ctl_get_ioffidx(ctl, &ucontrol->id); + __u32 __iomem *chbase = dev->lmmio + ((k & 4) * 0x40); + u32 gain; + + gain = ucontrol->value.integer.value[0]; + if (gain < 0 || gain > 127) + return -EINVAL; + pr_debug("%s: gain[%d]=%d\n", __func__, k, gain); + writel(gain, chbase + AUDIO_GAIN_CH0 + (k & 3)); + return 0; +} + +static const struct snd_kcontrol_new gain_control = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Mic Capture Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .info = gain_info, + .get = gain_get, + .put = gain_put, + .count = AUDIO_NCH, +}; + +/* + * ALSA PCM setup + * + * Called when initializing the board. Sets up the name and hooks up + * the callbacks + * + */ + +static int snd_card_TW68_pcm_reg(struct snd_card_tw68 *ctw, long idevice) +{ + struct snd_pcm *pcm; + struct snd_pcm_substream *ss; + int err, i; + struct snd_kcontrol *ctl; + + pr_debug("%s\n", __func__); + if ((err = snd_pcm_new(ctw->card, "TW6869 PCM", idevice, 0, AUDIO_NCH, &pcm)) < 0) //0, 1 + return err; + + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_card_TW68_capture_ops); + + pcm->private_data = ctw; + pcm->info_flags = 0; + strcpy(pcm->id, "TW68 PCM"); + strcpy(pcm->name, "TW68 Analog Audio Capture"); + + ctw->TW68_pcm = pcm; + + for (i = 0, ss = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; + ss; ss = ss->next, i++) { + sprintf(ss->name, "TW68 #%d Audio In ", i); + ctw->substream[i] = ss; + pr_debug("%s: substream[%d] %p\n", __func__, i, ctw->substream[i]); + } + + ctl = snd_ctl_new1(&gain_control, ctw->dev); + err = snd_ctl_add(ctw->card, ctl); + return err; +} + + +static void snd_TW68_free(struct snd_card * card) +{ + struct snd_card_tw68 *ctw = (struct snd_card_tw68*)card->private_data; + + pr_debug("%s: ctw %p\n", __func__, ctw); +} + +/* + * ALSA initialization + * + * Called by the init routine, once for each TW68 device present, + * it creates the basic structures and registers the ALSA devices + * + */ + +int TW68_alsa_create(struct TW68_dev *dev) +{ + + struct snd_card *card = NULL; + struct snd_card_tw68 *ctw; + static struct snd_device_ops ops = { NULL }; + + int err; + + pr_debug("%s\n", __func__); + + if(TW68_audio_nPCM > (SNDRV_CARDS-2)) + return -ENODEV; + + + err = snd_card_create(SNDRV_DEFAULT_IDX1, "TW68 SoundCard", THIS_MODULE, + sizeof(struct snd_card_tw68), &card); + if (err < 0) + return err; + + strcpy(card->driver, "TW6869 audio"); + strcpy(card->shortname, "TW68 PCM"); + sprintf(card->longname, "%s at 0x%p irq %d", + dev->name, dev->bmmio, dev->pci->irq); + + snd_card_set_dev(card, &dev->pci->dev); + + err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, dev, &ops); + if (err < 0) + return err; + + card->private_free = snd_TW68_free; + ctw = (struct snd_card_tw68 *)card->private_data; + ctw->dev = dev; + ctw->card= card; + ctw->last_audio_PB = 0xffff00; + + dev->card = card; + + spin_lock_init(&ctw->lock); + + pr_debug("alsa: %s registered as card %s ctw %p err :%d \n", card->longname, card->shortname, ctw, err); + + if ((err = snd_card_TW68_pcm_reg(ctw, 0)) < 0) + goto __nodev; + + ///snd_card_set_dev(card, dev); + + + if (err < 0) { + pr_debug("xxxxxx alsa: register TW68 card fail :%d \n", err); + return err; + } + pr_debug("alsa: %s registered as PCM card %s :%d \n",card->longname, card->shortname, err); + + if ((err = snd_card_register(card)) == 0) { + TW68_audio_nPCM++; + return 0; + } + pr_debug("xxxxxx alsa: %s registered as card %s :%d \n",card->longname, card->shortname, err); +__nodev: + pr_debug("xxxxxx alsa: register TW68 card fail :%d \n", err); + snd_card_free(card); + return err; +} + +int TW68_alsa_free(struct TW68_dev *dev) +{ + if(dev->card) { + snd_card_free(dev->card); + dev->card = NULL; + } + TW68_audio_nPCM--; + return 1; +} diff --git a/drivers/media/pci/TW68/TW68-core.c b/drivers/media/pci/TW68/TW68-core.c new file mode 100644 index 000000000000..3de2889c8e37 --- /dev/null +++ b/drivers/media/pci/TW68/TW68-core.c @@ -0,0 +1,2172 @@ +/* + * + * device driver for TW6869 based PCIe capture cards + * driver core for hardware + * + */ + +#include <linux/init.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/kmod.h> +#include <linux/sound.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/mutex.h> +#include <linux/dma-mapping.h> +#include <linux/pm.h> +#include <linux/vmalloc.h> + +#include "TW68.h" +#include "TW68_defines.h" + + +MODULE_DESCRIPTION("v4l2 driver module for TW6868/6869 based CVBS video capture cards"); +MODULE_AUTHOR("Simon Xu 2011-2013 @intersil"); +MODULE_LICENSE("GPL"); + +//0819 vma buffer modprobe videobuf_vmalloc +/* ------------------------------------------------------------------ */ + +static unsigned int irq_debug; +module_param(irq_debug, int, 0644); +MODULE_PARM_DESC(irq_debug,"enable debug messages [IRQ handler]"); + +static unsigned int core_debug; +module_param(core_debug, int, 0644); +MODULE_PARM_DESC(core_debug,"enable debug messages [core]"); + +static unsigned int gpio_tracking; +module_param(gpio_tracking, int, 0644); +MODULE_PARM_DESC(gpio_tracking,"enable debug messages [gpio]"); + +static unsigned int alsa = 1; +module_param(alsa, int, 0644); +MODULE_PARM_DESC(alsa,"enable/disable ALSA DMA sound [dmasound]"); + +static unsigned int latency = UNSET; +module_param(latency, int, 0444); +MODULE_PARM_DESC(latency,"pci latency timer"); + +int TW68_no_overlay=-1; +//module_param_named(no_overlay, TW6869_no_overlay, int, 0444); +//MODULE_PARM_DESC(no_overlay,"allow override overlay default (0 disables, 1 enables)" +// " [some VIA/SIS chipsets are known to have problem with overlay]"); + +static unsigned int video_nr[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; +static unsigned int vbi_nr[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; +static unsigned int radio_nr[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; +static unsigned int tuner[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; +static unsigned int card[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; + + +module_param_array(video_nr, int, NULL, 0444); +module_param_array(vbi_nr, int, NULL, 0444); +module_param_array(radio_nr, int, NULL, 0444); +module_param_array(tuner, int, NULL, 0444); +module_param_array(card, int, NULL, 0444); + +MODULE_PARM_DESC(video_nr, "video device number"); +MODULE_PARM_DESC(vbi_nr, "vbi device number"); +MODULE_PARM_DESC(radio_nr, "radio device number"); +MODULE_PARM_DESC(tuner, "tuner type"); +MODULE_PARM_DESC(card, "card type"); + +DEFINE_MUTEX(TW686v_devlist_lock); +EXPORT_SYMBOL(TW686v_devlist_lock); +LIST_HEAD(TW686v_devlist); +EXPORT_SYMBOL(TW686v_devlist); + +/* ------------------------------------------------------------------ */ + +//static char name_mute[] = "mute"; +//static char name_radio[] = "Radio"; +//static char name_tv[] = "Television"; +//static char name_tv_mono[] = "TV (mono only)"; +//static char name_comp[] = "Composite"; +static char name_comp1[] = "Composite1"; +static char name_comp2[] = "Composite2"; +static char name_comp3[] = "Composite3"; +static char name_comp4[] = "Composite4"; +//static char name_svideo[] = "S-Video"; + +/* ------------------------------------------------------------------ */ +/* board config info */ + +static DEFINE_MUTEX(TW68_devlist_lock); + +struct TW68_board TW68_boards[] = { + [TW68_BOARD_UNKNOWN] = { + .name = "TW6869", + .audio_clock = 0, + .tuner_type = TUNER_ABSENT, + .radio_type = UNSET, + .tuner_addr = ADDR_UNSET, + .radio_addr = ADDR_UNSET, + + .inputs = {{ + .name = name_comp1, + .vmux = 0, + .amux = LINE1, + }}, + }, + + [TW68_BOARD_A] = { + .name = "TW6869", + .audio_clock = 0, + .tuner_type = TUNER_ABSENT, + .radio_type = UNSET, + .tuner_addr = ADDR_UNSET, + .radio_addr = ADDR_UNSET, + + .inputs = {{ + .name = name_comp1, + .vmux = 0, + .amux = LINE1, + },{ + .name = name_comp2, + .vmux = 1, + .amux = LINE2, + },{ + .name = name_comp3, + .vmux = 2, + .amux = LINE3, + },{ + .name = name_comp4, + .vmux = 4, + .amux = LINE4, + }}, + }, + +}; + +const unsigned int TW68_bcount = ARRAY_SIZE(TW68_boards); + +/* ------------------------------------------------------------------ */ +/* PCI ids + subsystem IDs */ + +struct pci_device_id TW68_pci_tbl[] = { + + { + .vendor = 0x1797, + .device = 0x6869, + .subvendor = 0, + .subdevice = 0, + .driver_data = 0, + }, + + /* + { + .vendor = 0x1797, + .device = 0x6864, + .subvendor = 0, + .subdevice = 0, + .driver_data = 0, + }, + */ + // + { + /* --- end of list --- */ + } +}; +MODULE_DEVICE_TABLE(pci, TW68_pci_tbl); +/* ------------------------------------------------------------------ */ + + +static LIST_HEAD(mops_list); +static unsigned int TW68_devcount; + + +static u32 video_framerate[3][6] = { + { + 0xBFFFFFFF, //30 FULL + 0xBFFFCFFF, //28 + 0x8FFFCFFF, //26 + 0xBF3F3F3F, //24 FPS + 0xB3CFCFC3, //22 + 0x8F3CF3CF //20 FPS + }, + { 30, 28, 26, 24, 22, 20}, + { 25, 23, 20, 18, 16, 14} + +}; + + +int (*TW68_dmasound_init)(struct TW68_dev *dev); +int (*TW68_dmasound_exit)(struct TW68_dev *dev); + +void tw68v_set_framerate(struct TW68_dev *dev, u32 ch, u32 n) +{ + if (n >= 0 && n < 6) { + if(ch >=0 && ch<8) + reg_writel(DROP_FIELD_REG0+ ch, video_framerate[n][0]); // 30 FPS + pr_debug("%s: ch Id %d n:%d %d FPS\n", __func__, ch, n, video_framerate[n][1]); + } +} + + + +/* ------------------------------------------------------------------ */ + +void dma_field_init(struct dma_region *dma) +{ + dma->kvirt = NULL; + dma->dev = NULL; + dma->n_pages = 0; + dma->n_dma_pages = 0; + dma->sglist = NULL; +} + +/** + * dma_region_free - unmap and free the buffer + */ +void dma_field_free(struct dma_region *dma) +{ + if (dma->n_dma_pages) { + pci_unmap_sg(dma->dev, dma->sglist, dma->n_pages, + dma->direction); + dma->n_dma_pages = 0; + dma->dev = NULL; + } + + vfree(dma->sglist); + dma->sglist = NULL; + + vfree(dma->kvirt); + dma->kvirt = NULL; + dma->n_pages = 0; +} + +/** struct pci_dev *pci, + * dma_region_alloc - allocate the buffer and map it to the IOMMU + */ +int dma_field_alloc(struct dma_region *dma, unsigned long n_bytes, + struct pci_dev *dev, int direction) +{ + unsigned int i; + + /* round up to page size */ + /* to align the pointer to the (next) page boundary + #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) + this worked as PAGE_SIZE and PAGE_MASK were available in page.h. + */ + + n_bytes = PAGE_ALIGN(n_bytes); + + dma->n_pages = n_bytes >> PAGE_SHIFT; + //pr_debug("%s: n_bytes %d n_pages %d\n", __func__, n_bytes, dma->n_pages ); + + + dma->kvirt = vmalloc_32(n_bytes); + if (!dma->kvirt) { + //pr_err("%s: vmalloc_32() failed\n", __func__); + goto err; + } + + /* Clear the ram out, no junk to the user */ + memset(dma->kvirt, 0, n_bytes); + + /* allocate scatter/gather list */ + dma->sglist = vmalloc(dma->n_pages * sizeof(*dma->sglist)); + if (!dma->sglist) { + //pr_err("%s: vmalloc failed\n", __func__); + goto err; + } + + sg_init_table(dma->sglist, dma->n_pages); + + /* fill scatter/gather list with pages */ + for (i = 0; i < dma->n_pages; i++) { + unsigned long va = + (unsigned long)dma->kvirt + (i << PAGE_SHIFT); + + sg_set_page(&dma->sglist[i], vmalloc_to_page((void *)va), + PAGE_SIZE, 0); + } + + /* map sglist to the IOMMU */ + dma->n_dma_pages = + pci_map_sg(dev, dma->sglist, dma->n_pages, direction); + + if (dma->n_dma_pages == 0) { + //pr_err("%s: pci_map_sg() failed\n", __func__); + goto err; + } + + dma->dev = dev; + dma->direction = direction; + + return 0; + + err: + dma_field_free(dma); + return -ENOMEM; +} + + + +int TW68_buffer_pages(int size) +{ + size = PAGE_ALIGN(size); + size += PAGE_SIZE; /* for non-page-aligned buffers */ + size /= 4096; + return size; +} + +/* calc max # of buffers from size (must not exceed the 4MB virtual + * address space per DMA channel) */ +int TW68_buffer_count(unsigned int size, unsigned int count) +{ + unsigned int maxcount; + + maxcount = 1024 / TW68_buffer_pages(size); + if (count > maxcount) + count = maxcount; + + pr_debug("%s:size %d maxcount %d / C %d\n", __func__, size, maxcount, count ); + return count; +} + +int TW68_buffer_startpage(struct TW68_buf *buf) +{ + unsigned long pages, n, pgn; + pages = TW68_buffer_pages(buf->vb.bsize); + n = buf->vb.i; + pgn = pages * n; + pr_debug("%s: %ld / 0x%x(%d) %ld =%ld\n", __func__, pages, (buf->vb.bsize), + (buf->vb.bsize), n, pgn); + return pgn; +} + +unsigned long TW68_buffer_base(struct TW68_buf *buf) +{ + unsigned long base0, base; + struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); + + //void* vbuf = videobuf_to_vmalloc(&buf->vb); + base0 = TW68_buffer_startpage(buf) * 4096; + base = base0 + dma->sglist[0].offset; + + pr_debug("%s dma%x vbuf %lx TW68_buffer_base base0=%lx / base =%lx offset %x\n", + __func__, dma->bus_addr, buf->vb.baddr, base0, base, dma->sglist[0].offset); + return base; +} + +/* ------------------------------------------------------------------ */ + + +int AudioDMA_PB_alloc(struct pci_dev *pci, struct TW68_pgtable *pt) +{ + pt->size = AUDIO_CH_BUF_SIZE * AUDIO_NCH; //pt; //2 + pt->cpu = pci_alloc_consistent(pci, pt->size, &pt->dma); + if (!pt->cpu) + return -ENOMEM; + return 0; +} + + +int videoDMA_pgtable_alloc(struct pci_dev *pci, struct TW68_pgtable *pt) +{ + __le32 *cpu; + // __le32 *clean; + dma_addr_t dma_addr, phy_addr; + + cpu = pci_alloc_consistent(pci, PAGE_SIZE<<3, &dma_addr); // 8* 4096 contiguous //*2 + + if (NULL == cpu) { + return -ENOMEM; + } + + pt->size = PAGE_SIZE<<3; //pt; //2 + pt->cpu = cpu; + pt->dma = dma_addr; + phy_addr = dma_addr + (PAGE_SIZE<<2) + (PAGE_SIZE<<1); //6 pages + + pr_debug("%s: cpu:0X%p pt->size: 0x%x BD:0X%x\n", __func__, cpu, pt->size, (unsigned int)pt->cpu + pt->size ); + +#if 0 + for (clean = cpu; (unsigned int)clean < ((unsigned int)pt->cpu + pt->size); clean++ ) { + *clean++ = 0x40001000; // ctrl dw + // *clean = phy_addr; + if ((((unsigned int)pt->cpu + pt->size)-(unsigned int)clean) <6) + pr_debug("%s: mem%0d write CPU 0X%p SIZE%d, clean 0X%p = 0X%x 0X%x\n", + __func__, ((unsigned int)(clean-1) - (unsigned int)cpu), cpu, pt->size, clean, *(clean-1), *clean ); + } +#endif + return 0; +} + +void TW68_pgtable_free(struct pci_dev *pci, struct TW68_pgtable *pt) +{ + if (NULL == pt->cpu) + return; + pci_free_consistent(pci, pt->size, pt->cpu, pt->dma); + pt->cpu = NULL; +} + +/* ------------------------------------------------------------------ */ +#if 0 +void TW68_dma_free(struct videobuf_queue *q,struct TW68_buf *buf) +{ + struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); + BUG_ON(in_interrupt()); + + pr_debug(" $$$$ _dma_free :: dma->vmalloc 0x%X vb->baddr %p \n", dma->vmalloc, buf->vb.baddr); + +// 6.0 + //videobuf_waiton(&buf->vb,0,0); +// 6.1 + videobuf_waiton(q, &buf->vb,0,0); + + //videobuf_dma_unmap(q, dma); + + videobuf_dma_free(dma); + buf->vb.state = VIDEOBUF_NEEDS_INIT; +} +#endif +/* ------------------------------------------------------------------ */ + +int TW68_buffer_queue(struct TW68_dev *dev, + struct TW68_dmaqueue *q, + struct TW68_buf *buf) +{ + //pr_debug("%s: video buffer_queue %p buf %p \n", __func__, q, buf); + + /* + if (!list_empty(&q->queued)) { + list_add_tail(&buf->vb.queue, &q->queued); + buf->vb.state = VIDEOBUF_QUEUED; + pr_debug("%s: [%p/%d] appended to queued\n", + __func__, buf, buf->vb.i); + + // else if the 'active' chain doesn't yet exist we create it now + } + else + if (list_empty(&q->active)) { + pr_debug("%s: [%p/%d] first active\n", + __func__, buf, buf->vb.i); + list_add_tail(&buf->vb.queue, &q->active); + // TODO - why have we removed buf->count and q->count? + buf->activate(dev, buf, NULL); + + if (NULL == q->curr) { + q->curr = buf; + } + } + */ + /* else we would like to put this buffer on the tail of the + * active chain, provided it is "compatible". */ + + + if (NULL == q->curr) { + q->curr = buf; + buf->activate(dev,buf,NULL); + } else { + list_add_tail(&buf->vb.queue,&q->queued); // curr + buf->vb.state = VIDEOBUF_QUEUED; + } + + //TW68_buffer_requeue(dev, q); //&dev->video_dmaq[nId]); + return 0; + +} + + +/* ------------------------------------------------------------------ */ +/* + * Buffer handling routines + * + * These routines are "generic", i.e. are intended to be used by more + * than one module, e.g. the video and the transport stream modules. + * To accomplish this generality, callbacks are used whenever some + * module-specific test or action is required. + */ + +/* resends a current buffer in queue after resume */ +int TW68_buffer_requeue(struct TW68_dev *dev, + struct TW68_dmaqueue *q) +{ + struct TW68_buf *buf, *prev; + + pr_debug("%s\n", __func__); + + if (!list_empty(&q->active)) { + buf = list_entry(q->active.next, struct TW68_buf, vb.queue); + //pr_debug("%s: [%p/%d] restart dma\n", __func__, buf, buf->vb.i); + //q->start_dma(dev, q, buf); + mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT); + return 0; + } + + prev = NULL; + + if (list_empty(&q->queued)) + return 0; + buf = list_entry(q->queued.next, struct TW68_buf, vb.queue); + /* if nothing precedes this one */ + if (NULL == prev) { + list_move_tail(&buf->vb.queue, &q->active); + buf->activate(dev, buf, NULL); + pr_debug("%s: [%p/%d] first active\n", + __func__, buf, buf->vb.i); + } else { + list_move_tail(&buf->vb.queue, &q->active); + buf->activate(dev, buf, NULL); + //pr_debug("%s: [%p/ %p] move to active\n", __func__, buf, buf->vb.i); + } + //pr_debug("%s: no action taken\n", __func__); + return 0; +} + + +void TW68_buffer_finish(struct TW68_dev *dev, + struct TW68_dmaqueue *q, + unsigned int state) +{ + + if (q->dev != dev) return; + q->curr->vb.state = state; + do_gettimeofday(&q->curr->vb.ts); + + //pr_debug("%s: %p k %p\n", __func__, q->curr, k); + wake_up(&q->curr->vb.done); + q->curr = NULL; +} + +void TW68_buffer_next(struct TW68_dev *dev, + struct TW68_dmaqueue *q) +{ + struct TW68_buf *buf,*next = NULL; + BUG_ON(NULL != q->curr); + + if (!list_empty(&q->queued)) { + /* activate next one from dma queue */ + buf = list_entry(q->queued.next,struct TW68_buf,vb.queue); + + // **** remove v4l video buffer from the queue + list_del(&buf->vb.queue); + if (!list_empty(&q->queued)) + next = list_entry(q->queued.next, struct TW68_buf, vb.queue); + q->curr = buf; + + buf->vb.state = VIDEOBUF_ACTIVE; + + //pr_debug("buf->vb.state = VIDEOBUF_ACTIVE;\n"); + mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT); + } else { + /* nothing to do -- just stop DMA */ + del_timer(&q->timeout); + } +} + + +void Field_SG_Mapping(struct TW68_dev *dev, int field_PB) +{ + struct TW68_dmaqueue *q; + struct TW68_buf *buf; + struct TW68_pgtable *pt; + unsigned int i, nbytes, FieldSize, remain, nIDX, pgn; + u32 dwCtrl; + __le32 *ptr; + u32 nId =0; + u32 m_CurrentFrameStartIdx = 0; + u32 m_NextFrameStartIdx = 0; + struct videobuf_dmabuf *dma; + struct scatterlist *list; + q = &dev->video_q; + + if (!list_empty(&q->queued)) { + /* get next buffer from dma queue */ + buf = list_entry(q->queued.next,struct TW68_buf,vb.queue); + pr_debug("%s:buffer_next %p [prev=%p/next=%p] &buf->vb.queue= %p\n", + __func__, buf, q->queued.prev,q->queued.next, &buf->vb.queue); + + // fill half frame SG mapping entries + dma=videobuf_to_dma(&buf->vb); + list = dma ->sglist; + // dma channel offset = 8192 /8 /4 /2; + ptr = dev->m_Page0.cpu + (2* 128 * nId); // channel start entry address + + pr_debug("%s: size %ld Video Frame\n", __func__, buf->vb.size); + + + pt = &dev->m_Page0; + BUG_ON(NULL == pt || NULL == pt->cpu); + + + nIDX = 128; //85; + pgn = 83; + // dma channel offset = 8192 /8 /4 /2; + ptr = pt->cpu + (2* nIDX * nId); // channel start entry address 128 + //pr_debug("--_pgtable--nId 2 -- CPU ptr %p P start address %p & dma_address %p \n", pt->cpu, ptr, pt->dma ); + + FieldSize = buf->vb.size /2; + + nbytes = 0; + for (i = 0; i < dma->sglen; i++, list++) { + //for (p = 0; p * 4096 < list->length; p++, ptr++) + // switch to B + if (((nbytes + list->length) >= FieldSize) && + ((nbytes + list->length) <= (FieldSize + list->length)) ) { + + remain = FieldSize - (nbytes); + if (remain >0) { + dwCtrl = (((DMA_STATUS_HOST_READY &0x3)<<30) | + (((0)&1)<<29) | + ((m_CurrentFrameStartIdx & 0xFF) << 14) | + ((m_NextFrameStartIdx & 0xFF) << 21) | + //(((m_nIncomingFrameCnt[id]>12)&(MappingNum ==0)&1)<<13) | + //(1<<13) | + (remain & 0x1FFF)); // size + + if (field_PB) + ptr++; + else + *(ptr++) = cpu_to_le32(dwCtrl); + + if (field_PB) + ptr++; + else + *(ptr++) = cpu_to_le32(sg_dma_address(list) - list->offset ); //setup page dma address + + pr_debug("--_pgtable P/B switch ptr: %p *(ptr-1)%x, *ptr%x nbytes%d FieldSize%d remain%d i%d\n", + ptr, *(ptr-1), *ptr, nbytes, FieldSize, remain, i); + } + + + remain = (nbytes + list->length) - FieldSize; + nbytes += list->length; + + ptr = (pt->cpu + (2* nIDX * nId)) + 0x800; // 2 pages distance + pr_debug("--_pgtable P/B i%d ->B new ptr: %p pt->cpu %p nbytes%d FieldSize%d remain%d\n", + i, ptr, pt->cpu, nbytes, FieldSize, remain); + dwCtrl = (((DMA_STATUS_HOST_READY &0x3)<<30) | + (((1)&1)<<29) | + ((m_CurrentFrameStartIdx & 0xFF) << 14) | + ((m_NextFrameStartIdx & 0xFF) << 21) | + //(((m_nIncomingFrameCnt[id]>12)&(MappingNum ==0)&1)<<13) | + //(1<<13) | + (remain & 0x1FFF)); // size + + if (field_PB) + *(ptr++) = cpu_to_le32(dwCtrl); + else + ptr++; + + if (field_PB) + *(ptr++) = cpu_to_le32(sg_dma_address(list) - list->offset + list->length - remain ); //setup page dma address + else + ptr++; + + pr_debug("--_pgtable P/B switch ptr: %p *(ptr-1)%x, *ptr%x nbytes%d FieldSize%d remain%d i%d\n", + ptr, *(ptr-1), *ptr, nbytes, FieldSize, remain, i); + + //pr_debug("--_pgtable P/B switch ptr: %p nbytes%d FieldSize%d remain%d \n", ptr, nbytes, FieldSize, remain); + } else { + dwCtrl = (((DMA_STATUS_HOST_READY &0x3)<<30) | + (((i==0)&1)<<29) | + ((m_CurrentFrameStartIdx & 0x7F) << 14) | + ((m_NextFrameStartIdx & 0xFF) << 21) | + (list->length & 0x1FFF)); // size + + if (((!field_PB)&& ((nbytes + list->length) <= FieldSize)) || ((field_PB)&& (nbytes >= FieldSize))) + *(ptr++) = cpu_to_le32(dwCtrl); + else + ptr++; //pointing to the Address dword + + if (((!field_PB)&& ((nbytes + list->length) <= FieldSize)) || ((field_PB)&& (nbytes >= FieldSize))) + *(ptr++) = cpu_to_le32(sg_dma_address(list) - list->offset ); //setup page dma address + else + ptr++; //pointing to the Address dword + + nbytes += list->length; + } + } + } else { + /* nothing to do -- just stop DMA */ + pr_debug("buffer_next %p no more buffer \n",NULL); + } +} + + +void Fixed_SG_Mapping(struct TW68_dev *dev, int nDMA_channel, int Frame_size) // 0 1 +{ + // PROGRAM DMA DESCRIPTOR WITH FIXED vma dma_region sglist + struct dma_region *Field_P; + struct dma_region *Field_B; + struct scatterlist *sglist; + struct TW68_pgtable *pt; + int i, nbytes, FieldSize, remain, nIDX, pgn, pgn0; // unsigned xxx + u32 dwCtrl; + u32 m_CurrentFrameStartIdx = 0; + u32 m_NextFrameStartIdx = 0; + __le32 *ptr; + u32 nId = nDMA_channel; + + //pr_debug("@@@@ locate buffer_next %p [prev=%p/next=%p] &buf->vb.queue= %p \n", + // buf, q->queue.prev,q->queue.next, &buf->vb.queue); + + // fill P field half frame SG mapping entries + Field_P = &dev->Field_P[nId]; + Field_B = &dev->Field_B[nId]; + + pt = &dev->m_Page0; + BUG_ON(NULL == pt || NULL == pt->cpu); + FieldSize = Frame_size /2; + + //pr_debug("$$$$Fixed_SG_Mapping nId %d size %d Video Frame %d\n", nId, FieldSize, Frame_size); + //pr_debug("&&&&&&&&&&&&&&& Fill DMA table pt %p, length %d startpage %d L->length %d \n", + // pt, length, startpage, list->length); + + + nIDX = 128; //85; + // pgn = 85; //FieldSize / 4096; + pgn0 = (FieldSize + 4095) / 4096; + pgn = TW68_buffer_pages(Frame_size /2) -1; // page number for 1 field + + m_NextFrameStartIdx += pgn; + ptr = pt->cpu + (2* nIDX * nId); + pr_debug("-??????????????????-_pgtable--nId %d, pgn0 %d pgn %d m_NextFrameStartIdx: %d \n ", nId, pgn0, pgn, m_NextFrameStartIdx); + + sglist = Field_P ->sglist; + nbytes = 0; + remain = 0; + for (i = 0; i < Field_P->n_pages; i++, sglist++) { + // switch to B + if ((nbytes + sglist->length) <= FieldSize) { + remain = sglist->length; + } else { + remain = FieldSize - nbytes; + } + + if (remain != 4096) { + //pr_debug("--#######@@@@@@@@@@@@@@@@@@@@_pgtable--nId %d i=%d remain= %d \n", nId, i, remain ); + } + + if (remain <=0) + break; + //goto FieldB; + + dwCtrl = (((DMA_STATUS_HOST_READY &0x3)<<30) | + (((i==0)&1)<<29) | + ((m_CurrentFrameStartIdx & 0x7F) << 14) | + ((m_NextFrameStartIdx & 0xFF) << 21) | + ((pgn >70)<<13) | // 70 + (remain & 0x1FFF)); // size + *(ptr++) = cpu_to_le32(dwCtrl); + *(ptr++) = cpu_to_le32(sg_dma_address(sglist) - sglist->offset ); //setup page dma address + nbytes += sglist->length; + } + +//FieldB: + remain = 0; //(nbytes + sglist->length) - FieldSize; + nbytes = 0; + sglist = Field_B ->sglist; + + ptr = (pt->cpu + (2* nIDX * nId)) + 0x800; // 2 pages distance switch to B + + for (i = 0; i < Field_B->n_pages; i++, sglist++) { + // switch to B + if ((nbytes + sglist->length) <= FieldSize) { + remain = sglist->length; + } else { + remain = FieldSize - nbytes; + } + + if (remain != 4096) { + //pr_debug("--#######@@@@@@@@@@@@@@@@@@@@_pgtable--nId %d i=%d remain= %d \n", nId, i, remain ); + } + + if (remain <=0) + break; + + //if (remain >0) + { + dwCtrl = (((DMA_STATUS_HOST_READY &0x3)<<30) | + (((i==0)&1)<<29) | + ((m_CurrentFrameStartIdx & 0x7F) << 14) | //0xFF + ((m_NextFrameStartIdx & 0xFF) << 21) | + ((pgn >70)<<13) | + (remain & 0x1FFF)); // size + *(ptr++) = cpu_to_le32(dwCtrl); + *(ptr++) = cpu_to_le32(sg_dma_address(sglist) - sglist->offset ); //setup page dma address + nbytes += sglist->length; //remain + } + } +} + +/**************************************************************************************************/ +void BFDMA_setup(struct TW68_dev *dev, int nDMA_channel, int H, int W) // Field0 P B Field1 P B WidthHightPitch +{ + u32 regDW, dwV, dn; + + reg_writel((BDMA_ADDR_P_0 + nDMA_channel*8), dev->BDbuf[nDMA_channel][0].dma_addr); //P DMA page table + reg_writel((BDMA_ADDR_B_0 + nDMA_channel*8), dev->BDbuf[nDMA_channel][1].dma_addr); + reg_writel((BDMA_WHP_0 + nDMA_channel*8), (W& 0x7FF) | ((W& 0x7FF)<<11) | ((H &0x3FF)<<22)); + + reg_writel((BDMA_ADDR_P_F2_0 + nDMA_channel*8), dev->BDbuf[nDMA_channel][2].dma_addr); //P DMA page table + reg_writel((BDMA_ADDR_B_F2_0 + nDMA_channel*8), dev->BDbuf[nDMA_channel][3].dma_addr); + reg_writel((BDMA_WHP_F2_0 + nDMA_channel*8), (W& 0x7FF) | ((W& 0x7FF)<<11) | ((H &0x3FF)<<22)); + + + regDW = reg_readl(PHASE_REF_CONFIG ); + dn = (nDMA_channel<<1) + 0x10; + dwV = (0x3 << dn); + regDW |= dwV; + reg_writel(PHASE_REF_CONFIG, regDW ); + dwV = reg_readl(PHASE_REF_CONFIG ); + + //pr_debug("DMA mode setup %s: %d PHASE_REF_CONFIG dn 0x%lx 0x%lx 0x%lx H%d W%d \n", + // dev->name, nDMA_channel, regDW, dwV, dn, H, W ); +} + + /* *********************************************************************************************/ + + +int Field_Copy(struct TW68_dev *dev, int nDMA_channel, int field_PB) +{ + struct TW68_dmaqueue *q; + struct TW68_buf *buf = NULL; //,*next = NULL; + int Hmax, Wmax, h, pos, pitch; + + struct dma_region *Field_P; + struct dma_region *Field_B; + + //pr_debug(" Field_Copy: start 0000\n"); + int nId = nDMA_channel +1; + + void *vbuf, *srcbuf; // = videobuf_to_vmalloc(&buf->vb); + + //pr_debug("@@@@ locate buffer_next %p [prev=%p/next=%p] &buf->vb.queue= %p \n", + // buf, q->queue.prev,q->queue.next, &buf->vb.queue); + + // fill P field half frame SG mapping entries + Field_P = &dev->Field_P[nDMA_channel]; + Field_B = &dev->Field_B[nDMA_channel]; + if (field_PB) + srcbuf = Field_B->kvirt; + else + srcbuf = Field_P->kvirt; + + + q = &dev->video_dmaq[nId]; // &dev->video_q; + + // pr_debug(" nId%d Field_Copy: get DMA queue:%p, curr %p\n", nId, q, q->curr); + /* + pr_debug(" Field_Copy: get DMA queue list head:%p, \n", q->queue); + pr_debug(" Field_Copy: get DMA queue list head address:%p, \n", &q->queue); + */ + + + if (q->curr) { + buf = q->curr; + vbuf = videobuf_to_vmalloc(&buf->vb); + + Hmax = buf->vb.height/2; + Wmax = buf->vb.width; + + pitch = Wmax * buf->fmt->depth /8; + pos = pitch * (field_PB); + + //pr_debug(" Field_Copy: start @@@@@@@@\n"); //vbuf null + + for (h = 0; h < Hmax; h++) + { + memcpy(vbuf + pos, srcbuf, pitch); + pos += pitch*2; + srcbuf += pitch; + } + //pr_debug("%s: Done\n", __func__); + } else { + pr_debug("%s: list_empty\n", __func__); + return 0; + } + return 1; +} + + +int BF_Copy(struct TW68_dev *dev, int nDMA_channel, u32 Fn, u32 PB) +{ + struct TW68_dmaqueue *q; + struct TW68_buf *buf = NULL; //,*next = NULL; + int n, Hmax, Wmax, h, pos, pitch; + + //struct dma_region *Field_P; + //struct dma_region *Field_B; + //struct scatterlist *sglist; + + + //pr_debug(" Field_Copy: start 0000\n"); + int nId = nDMA_channel +1; + + void *vbuf, *srcbuf; // = videobuf_to_vmalloc(&buf->vb); + + //pr_debug("@@@@ locate buffer_next %p [prev=%p/next=%p] &buf->vb.queue= %p \n", + // buf, q->queue.prev,q->queue.next, &buf->vb.queue); + + // fill P field half frame SG mapping entries + pos = 0; + n =0; + if (Fn) + n = 2; + if (PB) + n++; + + srcbuf = dev->BDbuf[nDMA_channel][n].cpu; + + q = &dev->video_dmaq[nId]; // &dev->video_q; + + // pr_debug(" nId%d Field_Copy: get DMA queue:%p, curr %p\n", nId, q, q->curr); + /* + pr_debug(" Field_Copy: get DMA queue list head:%p, \n", q->queue); + pr_debug(" Field_Copy: get DMA queue list head address:%p, \n", &q->queue); + */ + + + if (q->curr) + { + buf = q->curr; + vbuf = videobuf_to_vmalloc(&buf->vb); + + Hmax = buf->vb.height/2; + Wmax = buf->vb.width; + + pitch = Wmax * buf->fmt->depth /8; + if (Fn) + pos = pitch ; + + //pr_debug(" Field_Copy: start @@@@@@@@ srcbuf:%X vbuf:%X H %d W %d P %d\n", srcbuf, vbuf, Hmax, Wmax, pitch); //vbuf null + + //vbuf += pitch * Hmax; + //if (n==1) + for (h = Hmax; h < Hmax + Hmax ; h++) + { + memcpy(vbuf + pos, srcbuf, pitch); + pos += pitch *2; + srcbuf += pitch; + } + //pr_debug(" Field_Copy: Done %%%%%%%%%\n"); + } else { + pr_debug(" Block [][] Field_Copy::::::::: list_empty \n"); + return 0; + } + return 1; +} + + + + +int QF_Field_Copy(struct TW68_dev *dev, int nDMA_channel, u32 Fn, u32 PB) +{ + struct TW68_dmaqueue *q; + struct TW68_buf *buf = NULL; //,*next = NULL; + int Hmax, Wmax, h, n, pos, pitch, stride; + + //pr_debug(" Field_Copy: start 0000\n"); + int nId = 0; + + void *vbuf, *srcbuf; // = videobuf_to_vmalloc(&buf->vb); + +/* + field_PB = dev->video_dmaq[0].FieldPB & (1<<nDMA_channel); + + Field_P = &dev->Field_P[nDMA_channel]; + Field_B = &dev->Field_B[nDMA_channel]; + if (field_PB) + srcbuf = Field_B->kvirt; + else + srcbuf = Field_P->kvirt; +*/ + + n =0; + if (Fn) + n = 2; + if (PB) + n++; + + srcbuf = dev->BDbuf[nDMA_channel][n].cpu; + + q = (&dev->video_dmaq[nId]); // &dev->video_q; (unsigned long) + + if (q->curr) { + buf = q->curr; + Hmax = buf->vb.height/2; + Wmax = buf->vb.width/2; + + pitch = 2* Wmax * buf->fmt->depth /8; + stride = pitch /2; + + if (nDMA_channel ==0) + pos =0; + if (nDMA_channel ==1) + pos += stride; + if (nDMA_channel ==2) + pos += pitch * Hmax; + if (nDMA_channel ==3) + pos += pitch * Hmax + stride; + + + vbuf = videobuf_to_vmalloc(&buf->vb); + + for (h = 0; h < Hmax-0; h++) { + memcpy(vbuf + pos, srcbuf, stride); + pos += pitch; + srcbuf += stride; + } + } else { + return 0; + } + return 1; +} + + +void DecoderResize(struct TW68_dev *dev, int nId, int nHeight, int nWidth) +{ + u32 nAddr, nHW, nH, nW, nVal, nReg, regDW; + + if(nId >=8 ) { + //pr_debug("DecoderResize() error: nId:%d,Width=%d,Height=%d\n", nId, nWidth, nHeight); + return; + } + //pr_debug("DecoderResize() ::::: nId:%d,Width=%d,Height=%d\n", nId, nWidth, nHeight); + + // only for internal 4 HDelay VDelay etc + nReg = 0xe7; // blue back color + reg_writel(MISC_CONTROL2, nReg); + + if(dev->PAL50[nId+1]) { + //VDelay + regDW = 0x18; + if (nId <4) { + nAddr = VDELAY0 + (nId *0x10); + reg_writel(nAddr, regDW); + + } else { + nAddr = VDELAY0 + ((nId-4) *0x10) + 0x100; + reg_writel(nAddr, regDW); + } + + //HDelay + regDW = 0x0A; + regDW = 0x0C; + + if (nId <4) { + nAddr = HDELAY0 + (nId *0x10); + reg_writel(nAddr, regDW); + } else { + nAddr = HDELAY0 + ((nId-4) *0x10) + 0x100; + reg_writel(nAddr, regDW); + + } + } else { + //VDelay + regDW = 0x14; + if (nId <4) { + nAddr = VDELAY0 + (nId *0x10); + reg_writel(nAddr, regDW); + } else { + nAddr = VDELAY0 + ((nId-4) *0x10) + 0x100; + reg_writel(nAddr, regDW); + } + + //HDelay + regDW = 0x0D; + regDW = 0x0E; + + if (nId <4) { + nAddr = HDELAY0 + (nId *0x10); + reg_writel(nAddr, regDW); + } else { + nAddr = HDELAY0 + ((nId-4) *0x10) + 0x100; + reg_writel(nAddr, regDW); + } + } + + + //nVal = 0; //0x0a; + //reg_writel(HDELAY0+nId, nVal); // adjust start pixel + nVal = reg_readl(HDELAY0+nId); + + // reg_writel (HACTIVE_L0+nId, 0xC0); // 2C0 704 + + + nHW = nWidth | (nHeight<<16) | (1<<31); + nH = nW = nHW; + pr_debug("DecoderResize() :: nId:%d, H:%d W:%d HW %X HDELAY0 %X\n", nId, nHeight, nWidth, nHW, nVal); //read default 0x0a; + + //Video Size + reg_writel(VIDEO_SIZE_REG, nHW); //for Rev.A backward compatible + reg_writel(VIDEO_SIZE_REG0+nId, nHW); //for Rev.B or later only + + if (((nHeight == 240) || (nHeight == 288)) &&(nWidth >= 700)) + nWidth = 720; + + if (((nHeight == 240) || (nHeight == 288))&&(nWidth > 699)) + nWidth = 720; + else + nWidth = (16*nWidth/720) +nWidth; + + //decoder Scale + nW = nWidth & 0x7FF; + nW = (720*256)/nW; + nH = nHeight & 0x1FF; + + //if (nHeight >240) //PAL + if(dev->PAL50[nId+1]) { + nH = (288*256)/nH; + } else { + nH = (240*256)/nH; + } + + nAddr = VSCALE1_LO + ((nId & 3) << 4) + ((nId & 4) * 0x40); //VSCALE1_LO + 0|0x10|0x20|0x30 + nVal = nH & 0xFF; //V + +/* + if(nId >= 4) { + //DeviceWrite2864(dev, nAddr, (unsigned char)nVal); + //nReg = DeviceRead2864(dev, nAddr); + } else { + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + } +*/ + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + + nAddr++; //V H + nVal = (((nH >> 8) & 0xF) << 4) | ((nW >> 8) & 0xF ); + + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + + nAddr++; //H + nVal = nW & 0xFF; + + + if(nId >= 4) { + //DeviceWrite2864(dev, nAddr, (unsigned char)nVal); + //nReg = DeviceRead2864(dev, nAddr); + } else { + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + } + + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + + //pr_debug("DecoderResize() ?????????????????:: nId:%d, nAddr%X nReg:%X\n", nId, nAddr, nReg); + + nAddr++; //H + nVal = nW & 0xFF; + + if(nId >= 4) { + //DeviceWrite2864(dev, nAddr, (unsigned char)nVal); + //nReg = DeviceRead2864(dev, nAddr); + } else { + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + } + + reg_writel(nAddr, nVal); + nReg = reg_readl(nAddr); + +// H Scaler + nVal = (nWidth-12 - 4)*(1<<16)/nWidth; + nVal = (4 & 0x1F) | + (((nWidth-12) & 0x3FF) << 5) | + (nVal <<15); + reg_writel(SHSCALER_REG0+nId, nVal); +} + + + +/*-------------------------------DMA start etc-------------------------------------------------- */ +void resync(unsigned long data) +{ + struct TW68_dev *dev = (struct TW68_dev*)data; + u32 dwRegE, dwRegF, k, m, mask; + //unsigned long flags; + unsigned long now = jiffies; + + mod_timer(&dev->delay_resync, jiffies+ msecs_to_jiffies(50)); + + //if (dev->videoDMA_ID == dev->videoCap_ID) + // return; + + + if (now - dev->errlog[0] < msecs_to_jiffies(50)) { + //pr_debug(" resync _reset_ sync time now%lX - errlog %lX \n", now, dev->errlog[0]); + return; + } + + m = 0; + mask = 0; + for (k=0; k<16; k++) { + mask = ((dev->videoDMA_ID ^ dev->videoCap_ID) & (1 << k)); + if ((mask)) { + m++; + dev->videoRS_ID |= mask; + if((m >1)|| dev->videoDMA_ID) + k = 16; + } + } + + + if ((dev->videoDMA_ID == 0) && dev->videoRS_ID) { + dev->videoDMA_ID = dev->videoRS_ID; + dwRegE = dev->videoDMA_ID; + + reg_writel(DMA_CHANNEL_ENABLE,dwRegE); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = (1<<31); + dwRegF |= dwRegE; + reg_writel(DMA_CMD, dwRegF); + dwRegF = reg_readl(DMA_CMD); + + dev->videoRS_ID = 0; + } +} + + +// special treatment for intel MB +u64 GetDelay(struct TW68_dev *dev, int eno) +{ + u64 delay, k, last, now, pause; + last =0; + pause = 40; // 20 30 50 + +/* + if (eno > 1) + pause = 30; + + if (eno > 3) + pause = 60; +*/ + + //pr_debug("\n $$$$$$$$$$$$$$$$ go through timers: jiffies:0x%X ", jiffies); + for (k=0; k<8; k++) { + //delay = dev->video_dmaq[k].restarter.expires; + //pr_debug(" 0X%x ", delay); + // last = (delay > last) ? delay : last; + } + + //delay = (last >jiffies) ? last : jiffies; + //pr_debug(" last 0X%x jiffies 0X%x ", last, jiffies); + now = jiffies; + if (last > now) + delay = last; + else + delay = jiffies; + + //pr_debug(" delay:0x%X ", delay); + if ((delay == jiffies)&& ((last + msecs_to_jiffies(pause)) >delay)) + delay = last + msecs_to_jiffies(pause); + //pr_debug(" delay:0x%X ", delay); + + delay += msecs_to_jiffies(pause); + + //pr_debug("\n $$$$$$$$$$$$$$$$ search delay : 40 msec %d last:0X%x jiffies:0X%x delay:0X%x \n", msecs_to_jiffies(40), last, jiffies, delay ); + return delay; +} + + + +void TW68_buffer_timeout(unsigned long data) +{ + u32 dwRegE, dwRegF; + struct TW68_dmaqueue *q = (struct TW68_dmaqueue*)data; + struct TW68_dev *dev = q->dev; + //unsigned long flags; + int nId = q->DMA_nCH; + + if (q->curr) { + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = reg_readl(DMA_CMD); + + pr_debug(" TW68_buffer_timeout ???????? DMA %d || 0x%X ||0X%X timeout on dma queue %p\n", nId, dwRegE, dwRegF, q->curr); + TW68_buffer_finish(dev,q,VIDEOBUF_ERROR); + } + TW68_buffer_next(dev,q); +} + +/* ------------------------------------------------------------------ */ + +int TW68_set_dmabits(struct TW68_dev *dev, unsigned int DMA_nCH) +{ + u32 dwRegST, dwRegER, dwRegPB, dwRegE, dwRegF, nId, k, run; + nId = DMA_nCH; + + dwRegST = reg_readl(DMA_INT_STATUS); + dwRegER = reg_readl(DMA_INT_ERROR); + dwRegPB = reg_readl(DMA_PB_STATUS); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = reg_readl(DMA_CMD); + + //pr_debug(" _dmabits _set_dmabits : DMA_INT_STATUS 0X%X DMA_INT_ERROR%X DMA_PB_STATUS%X DMA_CHANNEL_ENABLE %x DMA_CMD %X \n", dwRegST, dwRegER, dwRegPB, dwRegE, dwRegF); + + dev->video_DMA_1st_started += 1; //++ + dev->video_dmaq[DMA_nCH].FieldPB = 0; + + + dwRegE |= (1 << nId); // +1 + 0 Fixed PB + + dev->videoCap_ID |= (1 << nId) ; + dev->videoDMA_ID |= (1 << nId) ; + reg_writel(DMA_CHANNEL_ENABLE,dwRegE); + + run = 0; + + for (k=0; k<8; k++) { + if (run < dev->videoDMA_run[k]) + run = dev->videoDMA_run[k]; + } + + dev->videoDMA_run[nId] = run+1; + dwRegF = (1<<31); + dwRegF |= dwRegE; + reg_writel(DMA_CMD, dwRegF); + //dwRegF = reg_readl(DMA_CMD); + //pr_debug("%s: DMA_CHANNEL_ENABLE %x DMA_CMD %X \n", __func__, dwRegE, dwRegF); + + //pr_debug("%s: DMA_INT_STATUS%X DMA_INT_ERROR%X DMA_PB_STATUS%X DMA_CHANNEL_ENABLE %x DMA_CMD %X \n", __func__, dwRegST, dwRegER, dwRegPB, dwRegE, dwRegF); + return 0; +} + +/***********************************************************************/ + +int stop_video_DMA(struct TW68_dev *dev, unsigned int DMA_nCH) +{ + u32 dwRegER, dwRegPB, dwRegE, dwRegF, nId; + nId = DMA_nCH; //2; + + dwRegER = reg_readl(DMA_INT_ERROR); + dwRegPB = reg_readl(DMA_PB_STATUS); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = reg_readl(DMA_CMD); + + dwRegE &= ~(1 << nId); + reg_writel(DMA_CHANNEL_ENABLE, dwRegE); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dev->videoDMA_ID &= ~(1 << nId); + dev->videoCap_ID &= ~(1 << nId); + + dwRegF &= ~(1 << nId); + reg_writel(DMA_CMD, dwRegF); + dwRegF = reg_readl(DMA_CMD); + + dev->videoDMA_run[nId] = 0; + + if (dev->videoCap_ID ==0) { + reg_writel(DMA_CMD, 0); + reg_writel(DMA_CHANNEL_ENABLE, 0); + } + + //pr_debug("%s: DMA_CHANNEL_ENABLE 0x%X, DMA_CMD 0x%X, DMA_INT_STATUS 0x%08X \n", + // __func__, dwRegE, dwRegF, dwRegST); + return 0; +} + + +int VideoDecoderDetect(struct TW68_dev *dev, unsigned int DMA_nCH) +{ + u32 regDW, dwReg; + + if (DMA_nCH < 4) { + regDW = reg_readl(DECODER0_STATUS + (DMA_nCH* 0x10)); + dwReg = reg_readl(DECODER0_SDT + (DMA_nCH* 0x10)); + } else { // 6869 VD 5-8 + regDW = reg_readl(DECODER0_STATUS + ((DMA_nCH -4)* 0x10) + 0x100); + dwReg = reg_readl(DECODER0_SDT + ((DMA_nCH -4)* 0x10) + 0x100); + //pr_debug("\n\n Decoder 0x%X VideoStandardDetect DMA_nCH %d regDW 0x%x dwReg%d \n", (DECODER0_STATUS + (DMA_nCH* 0x10) + 0x100), regDW, dwReg ); + } + + if (regDW & 1) { //&& (!(dwReg & 0x80))) //skip the detection glitch //detect properly + // set to PAL 50 for real... + // VDelay + pr_debug("50HZ VideoStandardDetect DMA_nCH %d regDW 0x%x dwReg%d \n", DMA_nCH, regDW, dwReg ); + return 50; + } else { + pr_debug("60HZ VideoStandardDetect DMA_nCH %d regDW 0x%x dwReg%d \n", DMA_nCH, regDW, dwReg ); + return 60; + } +} + +/* ------------------------------------------------------------------ */ + +static irqreturn_t TW68_irq(int irq, void *dev_id) //hardware dev id for the ISR +{ + struct TW68_dev *dev = (struct TW68_dev*) dev_id; + unsigned long flags, audio_ch, k, eno, handled; + u32 dwRegST, dwRegER, dwRegPB, dwRegE, dwRegF, dwRegVP, dwErrBit; + static int INT1st = 1; + + //__le32 *pdmaP, *pdmaB; + audio_ch = 1; + handled = 1; + + spin_lock_irqsave(&dev->slock, flags); + + dwRegPB = reg_readl(DMA_PB_STATUS); + dwRegST = reg_readl(DMA_INT_STATUS); + dwRegER = reg_readl(DMA_INT_ERROR); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dwRegVP = reg_readl(VIDEO_PARSER_STATUS); + dwRegF = reg_readl(DMA_CMD); + spin_unlock_irqrestore(&dev->slock, flags); + + pr_debug("%s: PB=0x%x ST=0x%x ER=0x%x E=0x%x VP=0x%x CMD=0x%x\n", + __func__, dwRegPB, dwRegST, dwRegER, dwRegE, dwRegVP, dwRegF); + + if (dev->videoDMA_ID != dwRegE) { + INT1st++; + if (INT1st < 10) + pr_debug("%s: dwRegE=0x%x, dwRegF=0x%x, dwRegST=0x%x videoDMA_ID=0x%x\n", + __func__, dwRegE, dwRegF, dwRegST, dev->videoDMA_ID); + } + + if((dwRegER &0xFF000000) && dev->video_DMA_1st_started && dev->err_times<9) { + dev->video_DMA_1st_started --; + if (dev->video_DMA_1st_started < 0) + dev->video_DMA_1st_started = 0; + + dev->err_times++; + pr_debug("%s: err_times:%d dwRegER=0x%x dwRegVP=0x%x dwRegST=0x%x dwRegE=0x%x\n", + __func__, dev->err_times, dwRegER, dwRegVP, dwRegST, dwRegE); + } else { + if((dwRegER>>16 ) || dwRegVP || (dwRegST >>24)) { //stop + //err_exist, such as cpl error, tlp error, time-out + dwErrBit = 0; + dwErrBit |= ((dwRegST >>24) & 0xFF); + dwErrBit |= (((dwRegVP >>8) |dwRegVP )& 0xFF); + //dwErrBit |= (((dwRegER >>24) |(dwRegER >>16) |(dwRegER ))& 0xFF); + dwErrBit |= (((dwRegER >>24) |(dwRegER >>16))& 0xFF); + + eno =0; + for(k=0; k<8; k++) { + if (dwErrBit & (1 << k) ) { + eno++; + // Disable DMA channel + dwRegE &= ~((1<< k)); + if (eno >2) + dwRegE &= ~((0xFF)); + } + } + + // stop all error channels + spin_lock_irqsave(&dev->slock, flags); + dev->videoDMA_ID = dwRegE; + reg_writel(DMA_CHANNEL_ENABLE, dwRegE); + dwRegF = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = (1<<31); + dwRegF |= dwRegE; + reg_writel(DMA_CMD, dwRegF); + dwRegF = reg_readl(DMA_CMD); + spin_unlock_irqrestore(&dev->slock, flags); + + pr_debug("%s:dwErrBit=0x%x dwRegER=0x%x dwRegVP=0x%x dwRegST=0x%x dwRegE=0x%x dwRegF=0x%x\n", + __func__, dwErrBit, dwRegER, dwRegVP, dwRegST, dwRegE, dwRegF); + dev->errlog[0] = jiffies; + } else { + // Normal interrupt: + if (dwRegST & (0xFF00) & dev->videoDMA_ID) { + TW68_alsa_irq(dev, dwRegST, dwRegPB); + } + + if ((dwRegST & (0xFF)) && (!(dwRegER >>16))) { + for(k=0; k<8; k++) { + if ((dwRegST & dev->videoDMA_ID) & (1 << k)) { //exclude inactive dev + TW68_irq_video_done(dev, k+1, dwRegPB); + if (!dev->video_dmaq[k+1].FieldPB) { // first time after dma start + /* + Reg8b <<= 16; + dev->video_dmaq[k+1].FieldPB &= 0x0000FFFF; + dev->video_dmaq[k+1].FieldPB |= Reg8b; // add + //pr_debug(" IRQ DMA normal ist time k:%d Reg8b 0x%x: PB 0x%x FieldPB 0X%X DMA_CHANNEL_ENABLE %x DMA_CMD %X \n", + // k, Reg8b, dwRegPB, dev->video_dmaq[k].FieldPB, dwRegE, dwRegF); + if (Reg8b &0x10) + dev->video_dmaq[k].FieldPB |= 0xF0; + */ + } + + if (dev->video_dmaq[k+1].FieldPB & 0xF0) { + dev->video_dmaq[k+1].FieldPB &= 0xFFFF0000; + } else { + dev->video_dmaq[k+1].FieldPB &= 0xFFFF00FF; // clear PB + dev->video_dmaq[k+1].FieldPB |= (dwRegPB & (1<<k))<<8; + dev->video_dmaq[k+1].FCN++; + } + } + } + } + + if (dev->videoRS_ID) { + dev->videoDMA_ID |= dev->videoRS_ID; + dev->videoRS_ID = 0; + dwRegE = dev->videoDMA_ID; + + reg_writel(DMA_CHANNEL_ENABLE, dwRegE); + dwRegF = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = (1<<31); + dwRegF |= dwRegE; + reg_writel(DMA_CMD, dwRegF); + dwRegF = reg_readl(DMA_CMD); + } + } + } + if (!dwRegER && !dwRegST) { // skip the interrupt conflicts + //need to stop it + /* + reg_writel(DMA_CHANNEL_ENABLE, 0); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + + reg_writel(DMA_CMD, 0); + dwRegF = reg_readl(DMA_CMD); + */ + + if (dev->videoCap_ID ==0) { + reg_writel(DMA_CMD, 0); + reg_writel(DMA_CHANNEL_ENABLE,0); + dwRegE = reg_readl(DMA_CHANNEL_ENABLE); + dwRegF = reg_readl(DMA_CMD); + } + + handled = 0; + //pr_debug("---+++++++++ skip IRQ: DMA_INT_STATUS 0X%X DMA_INT_ERROR%X DMA_PB_STATUS%X DMA_CHANNEL_ENABLE %x DMA_CMD %X k:%x\n", dwRegST, dwRegER, dwRegPB, dwRegE, dwRegF, k); + } + return IRQ_RETVAL(handled); +} + + +/* ------------------------------------------------------------------ */ + +/* early init (no i2c, no irq) */ + +static int TW68_hwinit1(struct TW68_dev *dev) +{ + u32 m_StartIdx, m_EndIdx, m_nVideoFormat, m_dwCHConfig, dwReg; + u32 m_bHorizontalDecimate=0, m_bVerticalDecimate=0, m_nDropChannelNum; + u32 m_bDropMasterOrSlave, m_bDropField, m_bDropOddOrEven, m_nCurVideoChannelNum; + u32 regDW, val1, k, ChannelOffset, pgn; + // Audio P + int audio_ch; + u32 dmaP; + + pr_debug(" TW6869 hwinit1 \n"); + mutex_init(&dev->lock); + spin_lock_init(&dev->slock); + + + pci_read_config_dword(dev->pci, PCI_VENDOR_ID, ®DW); + + //pr_debug("%s: found with ID: 0x%lx\n", dev->name, regDW ); + + pci_read_config_dword(dev->pci, PCI_COMMAND, ®DW); // 04 PCI_COMMAND + pr_debug("%s: CFG[0x04] PCI_COMMAND : 0x%x\n", dev->name, regDW ); + + regDW |= 7; + regDW &= 0xfffffbff; + pci_write_config_dword(dev->pci, PCI_COMMAND, regDW); + pci_read_config_dword(dev->pci, 0x4, ®DW); + //pr_debug("%s: CFG[0x04] 0x%lx\n", dev->name, regDW ); + + pci_read_config_dword(dev->pci, 0x3c, ®DW); + //pr_debug("%s: CFG[0x3c] 0x%lx\n", dev->name, regDW ); + + // MSI CAP disable MSI + pci_read_config_dword(dev->pci, 0x50, ®DW); + regDW &= 0xfffeffff; + pci_write_config_dword(dev->pci, 0x50, regDW); + pci_read_config_dword(dev->pci, 0x50, ®DW); + //pr_debug("%s: CFG[0x50] 0x%lx\n", dev->name, regDW ); + //MSIX CAP disable + pci_read_config_dword(dev->pci, 0xac, ®DW); + regDW &= 0x7fffffff; + pci_write_config_dword(dev->pci, 0xac, regDW); + pci_read_config_dword(dev->pci, 0xac, ®DW); + //pr_debug("%s: CFG[0xac] 0x%lx\n", dev->name, regDW ); + + //PCIe Cap registers + pci_read_config_dword(dev->pci, 0x70, ®DW); + //pr_debug("%s: CFG[0x70] 0x%lx\n", dev->name, regDW ); + pci_read_config_dword(dev->pci, 0x74, ®DW); + //pr_debug("%s: CFG[0x74] 0x%lx\n", dev->name, regDW ); + + pci_read_config_dword(dev->pci, 0x78, ®DW); + regDW &= 0xfffffe1f; + regDW |= (0x8 <<5); // 8 - 128 || 9 - 256 || A - 512 + pci_write_config_dword(dev->pci, 0x78, regDW); + + pci_read_config_dword(dev->pci, 0x78, ®DW); + //pr_debug("%s: CFG[0x78] 0x%lx\n", dev->name, regDW ); + + pci_read_config_dword(dev->pci, 0x730, ®DW); + //pr_debug("%s: CFG[0x730] 0x%lx\n", dev->name, regDW ); + + pci_read_config_dword(dev->pci, 0x734, ®DW); + //pr_debug("%s: CFG[0x734] 0x%lx\n", dev->name, regDW ); + + pci_read_config_dword(dev->pci, 0x738, ®DW); + // pr_debug("%s: CFG[0x738] 0x%lx\n", dev->name, regDW ); + + mdelay(20); + reg_writel(DMA_CHANNEL_ENABLE, 0); + mdelay(50); + reg_writel(DMA_CMD, 0); + + reg_readl(DMA_CHANNEL_ENABLE); + reg_readl(DMA_CMD); + + //Trasmit Posted FC credit Status + reg_writel(EP_REG_ADDR, 0x730); // + regDW = reg_readl(EP_REG_DATA ); + //pr_debug("%s: PCI_CFG[Posted 0x730]= 0x%lx\n", dev->name, regDW ); + + //Trasnmit Non-Posted FC credit Status + reg_writel(EP_REG_ADDR, 0x734); // + regDW = reg_readl(EP_REG_DATA ); + //pr_debug("%s: PCI_CFG[Non-Posted 0x734]= 0x%lx\n", dev->name, regDW ); + + //CPL FC credit Status + reg_writel(EP_REG_ADDR, 0x738); // + regDW = reg_readl(EP_REG_DATA ); + //pr_debug("%s: PCI_CFG[CPL 0x738]= 0x%lx\n", dev->name, regDW ); + + regDW = reg_readl((SYS_SOFT_RST) ); + //pr_debug("HWinit %s: SYS_SOFT_RST 0x%lx \n", dev->name, regDW ); + //regDW = tw_readl(SYS_SOFT_RST ); + //pr_debug("DMA %s: SYS_SOFT_RST 0x%lx \n", dev->name, regDW ); + + reg_writel((SYS_SOFT_RST), 0x01); //??? 01 09 + reg_writel((SYS_SOFT_RST), 0x0F); + regDW = reg_readl(SYS_SOFT_RST ); + //pr_debug(" After software reset DMA %s: SYS_SOFT_RST 0x%lx \n", dev->name, regDW ); + + regDW = reg_readl(PHASE_REF_CONFIG ); + //pr_debug("HWinit %s: PHASE_REF_CONFIG 0x%lx \n", dev->name, regDW ); + regDW = 0x1518; + reg_writel(PHASE_REF_CONFIG, regDW&0xFFFF ); + + // Allocate PB DMA pagetable total 16K filled with 0xFF + videoDMA_pgtable_alloc(dev->pci, &dev->m_Page0); + AudioDMA_PB_alloc(dev->pci, &dev->m_AudioBuffer); + + for (k =0; k<8; k++) { + if (dma_field_alloc(&dev->Field_P[k], 720*300*2, dev->pci, + PCI_DMA_BIDIRECTIONAL)) { + //pr_err("Failed to allocate dma buffer"); + dma_field_free(&dev->Field_P[k]); + return -1; + } + + if (dma_field_alloc(&dev->Field_B[k], 720*300*2, dev->pci, + PCI_DMA_BIDIRECTIONAL)) { + //pr_err("Failed to allocate dma buffer"); + dma_field_free(&dev->Field_B[k]); + return -1; + } + } + + ChannelOffset = pgn = 128; //125; + pgn = 85; // starting for 720 * 240 * 2 + m_nDropChannelNum = 0; + m_bDropMasterOrSlave = 1; // master + m_bDropField = 0; + m_bDropOddOrEven = 0; + + //m_nVideoFormat = VIDEO_FORMAT_RGB565; + m_nVideoFormat = VIDEO_FORMAT_YUYV; + for (k = 0; k <MAX_NUM_SG_DMA; k++) { + m_StartIdx = ChannelOffset * k; + m_EndIdx = m_StartIdx + pgn; + m_nCurVideoChannelNum = 0; // real-time video channel starts 0 + m_nVideoFormat = 0; //0; //VIDEO_FORMAT_UYVY; + + m_dwCHConfig = (m_StartIdx&0x3FF) | // 10 bits + ((m_EndIdx&0x3FF)<<10) | // 10 bits + ((m_nVideoFormat&7)<<20) | + ((m_bHorizontalDecimate&1)<<23)| + ((m_bVerticalDecimate&1)<<24) | + ((m_nDropChannelNum&3)<<25) | + ((m_bDropMasterOrSlave&1)<<27) | // 1 bit + ((m_bDropField&1)<<28) | + ((m_bDropOddOrEven&1)<<29) | + ((m_nCurVideoChannelNum&3)<<30); + reg_writel(DMA_CH0_CONFIG+ k,m_dwCHConfig); + dwReg = reg_readl(DMA_CH0_CONFIG+ k); + //pr_debug(" ********#### buffer_setup%d:: m_StartIdx 0X%x 0x%X dwReg: 0x%X m_dwCHConfig 0x%X \n", k, m_StartIdx, pgn, m_dwCHConfig, dwReg ); + + reg_writel(VERTICAL_CTRL, 0x24); //0x26 will cause ch0 and ch1 have dma_error. 0x24 + reg_writel(LOOP_CTRL, 0xA5 ); // 0xfd 0xA5 //1005 + reg_writel(DROP_FIELD_REG0+ k, 0); //m_nDropFiledReg + } + +// setup audio DMA + for (audio_ch =0; audio_ch < AUDIO_NCH; audio_ch++) { + dmaP = dev->m_AudioBuffer.dma + AUDIO_CH_BUF_SIZE * audio_ch; + reg_writel(DMA_CH8_CONFIG_P + audio_ch*2, dmaP ); + //Audio B = P+1 + reg_writel(DMA_CH8_CONFIG_B + audio_ch*2, dmaP + AUDIO_DMA_PAGE); + + //pr_debug("---Audio DMA 0x19-0x29 config --- CH%02d write dmaP 0X%p read 0X%x 0X%x\n", + // audio_ch, dmaP, reg_readl(DMA_CH8_CONFIG_P + audio_ch*2), reg_readl(DMA_CH8_CONFIG_B + audio_ch*2) ); + } + + //pr_debug(" Mmio %s: CFG[0x78] cpu 0x%x dma 0x%x \n", dev->name, (unsigned int)dev->m_Page0.cpu, dev->m_Page0.dma ); + + regDW = reg_readl((DMA_PAGE_TABLE0_ADDR) ); + pr_debug("DMA %s: DMA_PAGE_TABLE0_ADDR 0x%x \n", dev->name, regDW ); + regDW = reg_readl((DMA_PAGE_TABLE1_ADDR) ); + pr_debug("DMA %s: DMA_PAGE_TABLE1_ADDR 0x%x \n", dev->name, regDW ); + + reg_writel((DMA_PAGE_TABLE0_ADDR), dev->m_Page0.dma); //P DMA page table + reg_writel((DMA_PAGE_TABLE1_ADDR), dev->m_Page0.dma + (PAGE_SIZE <<1)); //B DMA page table + + + regDW = reg_readl((DMA_PAGE_TABLE0_ADDR) ); + pr_debug("DMA %s: DMA_PAGE_TABLE0_ADDR 0x%x \n", dev->name, regDW ); + regDW = reg_readl((DMA_PAGE_TABLE1_ADDR) ); + pr_debug("DMA %s: DMA_PAGE_TABLE1_ADDR 0x%x \n", dev->name, regDW ); + + /* + regDW = tw_readl((DMA_PAGE_TABLE0_ADDR) ); + pr_debug("DMA %s: tw DMA_PAGE_TABLE0_ADDR 0x%x \n", dev->name, regDW ); + regDW = tw_readl((DMA_PAGE_TABLE1_ADDR) ); + pr_debug("DMA %s: tw DMA_PAGE_TABLE1_ADDR 0x%x \n", dev->name, regDW ); + */ + + reg_writel(AVSRST,0x3F); // u32 + regDW = reg_readl(AVSRST); + pr_debug("DMA %s: tw AVSRST _u8 %x :: 0x%x \n", dev->name, (AVSRST<<2), regDW ); + + reg_writel(DMA_CMD, 0); // u32 + regDW = reg_readl(DMA_CMD ); + pr_debug("DMA %s: tw DMA_CMD _u8 %x :: 0x%x \n", dev->name, (DMA_CMD<<2), regDW ); + + reg_writel(DMA_CHANNEL_ENABLE,0); + regDW = reg_readl(DMA_CHANNEL_ENABLE ); + pr_debug("DMA %s: tw DMA_CHANNEL_ENABLE %x :: 0x%x \n", dev->name, DMA_CHANNEL_ENABLE, regDW ); + + regDW = reg_readl(DMA_CHANNEL_ENABLE ); + pr_debug("DMA %s: tw DMA_CHANNEL_ENABLE %x :: 0x%x \n", dev->name, DMA_CHANNEL_ENABLE, regDW ); + //reg_writel(DMA_CHANNEL_TIMEOUT, 0x180c8F88); // 860 a00 0x140c8560 0x1F0c8b08 0xF00F00 140c8E08 0x140c8D08 + reg_writel(DMA_CHANNEL_TIMEOUT, (0x3E << 24) | (0x7f0 << 12) | 0xff0); // longer timeout setting + regDW = reg_readl(DMA_CHANNEL_TIMEOUT ); + pr_debug("DMA %s: tw DMA_CHANNEL_TIMEOUT %x :: 0x%x \n", dev->name, DMA_CHANNEL_TIMEOUT, regDW ); + + reg_writel(DMA_INT_REF, 0x1c000); // 2a000 2b000 2c000 3932e 0x3032e + regDW = reg_readl(DMA_INT_REF ); + pr_debug("DMA %s: tw DMA_INT_REF %x :: 0x%x \n", dev->name, DMA_INT_REF, regDW ); + + + reg_writel(DMA_CONFIG, 0x00FF0004); + regDW = reg_readl(DMA_CONFIG ); + pr_debug("DMA %s: tw DMA_CONFIG %x :: 0x%x \n", dev->name, DMA_CONFIG, regDW ); + + regDW = (0xFF << 16) | (VIDEO_GEN_PATTERNS <<8) | VIDEO_GEN; + pr_debug(" set tw68 VIDEO_CTRL2 %x :: 0x%x \n", VIDEO_CTRL2, regDW ); + + reg_writel(VIDEO_CTRL2, regDW); + regDW = reg_readl(VIDEO_CTRL2 ); + pr_debug("DMA %s: tw DMA_CONFIG %x :: 0x%x \n", dev->name, VIDEO_CTRL2, regDW ); + + //VDelay + regDW = 0x014; + + reg_writel(VDELAY0, regDW); + reg_writel(VDELAY1, regDW); + reg_writel(VDELAY2, regDW); + reg_writel(VDELAY3, regDW); + // +4 decoder 0x100 + // 6869 + reg_writel(VDELAY0 +0x100, regDW); + reg_writel(VDELAY1 +0x100, regDW); + reg_writel(VDELAY2 +0x100, regDW); + reg_writel(VDELAY3 +0x100, regDW); + + + //Show Blue background if no signal + regDW = 0xe7; + reg_writel(MISC_CONTROL2, regDW); + + // 6869 + reg_writel(MISC_CONTROL2 +0x100, regDW); + + regDW = reg_readl(VDELAY0 ); + pr_debug(" read tw68 VDELAY0 %x :: 0x%x \n", VDELAY0, regDW ); + + regDW = reg_readl(MISC_CONTROL2 ); + pr_debug(" read tw68 MISC_CONTROL2 %x :: 0x%x \n", MISC_CONTROL2, regDW ); + + // 2864 #1/External, Muxed-656 + //Reset 2864s + + val1 = reg_readl(CSR_REG); + val1 &= 0x7FFF; + reg_writel(CSR_REG, val1); + //pr_debug("2864 init CSR_REG 0x%x]= I2C 2864 val1:0X%x %x\n", CSR_REG, val1 ); + + mdelay(100); + val1 |= 0x8002; // Pull out from reset and enable I2S + reg_writel(CSR_REG, val1); + //pr_debug("2864 init CSR_REG 0x%x]= I2C 2864 val1:0X%x %x\n", CSR_REG, val1 ); + + // device data structure initialization + TW68_video_init1(dev); + + // decoder parameter setup + TW68_video_init2(dev); // set TV param + + dev->video_DMA_1st_started =0; // initial value for skipping startup DMA error + dev->err_times =0; // DMA error counter + dev->TCN = 16; + + for (k=0; k<8; k++) { + dev->videoDMA_run[k]=0;; + } + return 0; +} + +/* shutdown */ +static int TW68_hwfini(struct TW68_dev *dev) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static int vdev_init(struct TW68_dev *dev, struct video_device *template, char *type) +{ + struct video_device* vfdev[9]; //QF 0 + 8 + int k=1; + int err0; + + for (k =1; k<9; k++ ) { // dev0 QF muxer dev 1 ~ 4 + vfdev[k] = video_device_alloc(); + //vfdev[k] = vfd; + + if (NULL == vfdev[k]) { + pr_info("%s:Null vfdev %d\n", __func__, k); + return k; + } + *(vfdev[k]) = *template; + + vfdev[k]->v4l2_dev = &dev->v4l2_dev; + vfdev[k]->release = video_device_release; + vfdev[k]->debug = 0; + snprintf(vfdev[k]->name, sizeof(vfdev[k]->name), "%s %s (%s22)", + dev->name, type, TW68_boards[dev->board].name); + + dev->video_device[k] = vfdev[k]; + pr_debug("*****%d*****video DEVICE NAME : %s vfdev[%d] 0x%p tvnorm::0x%p \n", k, dev->video_device[k]->name, k, vfdev[k], dev->tvnorm); // vfdev[k]->name, + + err0 = video_register_device(dev->video_device[k], VFL_TYPE_GRABBER, video_nr[dev->nr]); + dev->vfd_DMA_num[k] = vfdev[k]->num; + pr_debug("*****%d*****video DEVICE NAME : %s minor %d DMA %d err0 %d \n", k, vfdev[k]->name, dev->video_device[k]->minor, dev->vfd_DMA_num[k], err0); + } + + pr_debug("%s Video DEVICE NAME : %s \n", __func__, dev->video_device[1]->name); + return k; +} + +static void TW68_unregister_video(struct TW68_dev *dev) +{ + int k; + for (k = 1; k < 9; k++) { //0 + 4 + if (dev->video_device[k]) + if (-1 != dev->video_device[k]->minor) { + video_unregister_device(dev->video_device[k]); + pr_debug("video_unregister_device(dev->video_dev %d \n", k ); + } + } +} + + +static int TW68_initdev(struct pci_dev *pci_dev, + const struct pci_device_id *pci_id) +{ + struct TW68_dev *dev; + int err, err0; + + pr_debug("PCI register init called\n"); + + if (TW68_devcount == TW68_MAXBOARDS) + return -ENOMEM; + + dev = kzalloc(sizeof(*dev),GFP_KERNEL); + if (NULL == dev) + return -ENOMEM; + + err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); + if (err) { + pr_err("%s: v4l2_device_register failed %d\n", __func__, err); + goto fail0; + } + + /* pci init */ + dev->pci = pci_dev; + if (pci_enable_device(pci_dev)) { + pr_err("%s: pci_enable_device failed\n", __func__); + err = -EIO; + goto fail1; + } + + dev->nr = TW68_devcount; + sprintf(dev->name,"TW%x[%d]",pci_dev->device,dev->nr); + + pr_debug(" %s TW68_devcount: %d \n", dev->name, TW68_devcount ); + + /* pci quirks */ + if (pci_pci_problems) { + if (pci_pci_problems & PCIPCI_TRITON) + pr_debug("%s: quirk: PCIPCI_TRITON\n", dev->name); + if (pci_pci_problems & PCIPCI_NATOMA) + pr_debug("%s: quirk: PCIPCI_NATOMA\n", dev->name); + if (pci_pci_problems & PCIPCI_VIAETBF) + pr_debug("%s: quirk: PCIPCI_VIAETBF\n", dev->name); + if (pci_pci_problems & PCIPCI_VSFX) + pr_debug("%s: quirk: PCIPCI_VSFX\n",dev->name); +#ifdef PCIPCI_ALIMAGIK + if (pci_pci_problems & PCIPCI_ALIMAGIK) { + pr_debug("%s: quirk: PCIPCI_ALIMAGIK -- latency fixup\n", + dev->name); + latency = 0x0A; + } +#endif + if (pci_pci_problems & (PCIPCI_FAIL|PCIAGP_FAIL)) { + pr_debug("%s: quirk: this driver and your " + "chipset may not work together" + " in overlay mode.\n",dev->name); + if (!TW68_no_overlay) { + pr_debug("%s: quirk: overlay " + "mode will be disabled.\n", + dev->name); + TW68_no_overlay = 1; + } else { + pr_debug("%s: quirk: overlay " + "mode will be forced. Use this" + " option at your own risk.\n", + dev->name); + } + } + } + +/* + if (UNSET != latency) { + pr_debug("%s: setting pci latency timer to %d\n", + dev->name,latency); + pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency); + } +*/ + + /* print pci info */ + pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); + + pr_debug("%s: found at %s, rev: %d, irq: %d, " + "latency: %d, mmio: 0x%llx\n", dev->name, + pci_name(pci_dev), dev->pci_rev, pci_dev->irq, + dev->pci_lat,(unsigned long long)pci_resource_start(pci_dev,0)); + + pci_set_master(pci_dev); + pci_set_drvdata(pci_dev, &(dev->v4l2_dev)); + + if (!pci_dma_supported(pci_dev, DMA_BIT_MASK(32))) { + pr_debug("%s: Oops: no 32bit PCI DMA ???\n",dev->name); + err = -EIO; + goto fail1; + } else { + pr_debug("%s: Hi: 32bit PCI DMA supported \n",dev->name); + } + + dev->board = 1; + pr_debug("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n", + dev->name,pci_dev->subsystem_vendor, + pci_dev->subsystem_device,TW68_boards[dev->board].name, + dev->board, dev->autodetected ? + "autodetected" : "insmod option"); + + + /* get mmio */ + if (!request_mem_region(pci_resource_start(pci_dev,0), + pci_resource_len(pci_dev,0), + dev->name)) { + err = -EBUSY; + pr_err("%s: can't get MMIO memory @ 0x%llx\n", + dev->name,(unsigned long long)pci_resource_start(pci_dev,0)); + goto fail1; + } + + // no cache + dev->lmmio = ioremap_nocache(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0)); + + dev->bmmio = (__u8 __iomem *)dev->lmmio; + + if (NULL == dev->lmmio) { + err = -EIO; + pr_err("%s: can't ioremap() MMIO memory\n", dev->name); + goto fail2; + } + + //pr_debug(" TW6869 PCI_BAR0 mapped registers: phy: 0x%X dev->lmmio 0X%x dev->bmmio 0X%x length: %x \n", + // pci_resource_start(pci_dev, 0), (unsigned int)dev->lmmio, (unsigned int)dev->bmmio, (unsigned int)pci_resource_len(pci_dev,0) ); + + /* initialize hardware #1 */ + TW68_hwinit1(dev); + //InitExternal2864(dev); + /* get irq */ + pr_debug("%s: %s: request IRQ %d\n", __func__, dev->name,pci_dev->irq); + + err = request_irq(pci_dev->irq, TW68_irq, IRQF_SHARED , dev->name, dev); // IRQF_SHARED | IRQF_DISABLED + + if (err < 0) { + pr_err("%s: can't get IRQ %d\n", dev->name,pci_dev->irq); + goto fail3; + } + + v4l2_prio_init(&dev->prio); + + pr_info("Adding TW686v_devlist %p\n", &TW686v_devlist); + list_add_tail(&dev->devlist, &TW686v_devlist); + //add current TW68_dev device structure node + + /* register v4l devices */ + if (TW68_no_overlay > 0) + pr_debug("%s: Overlay support disabled.\n", dev->name); + else + pr_debug("%s: Overlay supported %d .\n", dev->name, TW68_no_overlay); + + err0 = vdev_init(dev, &TW68_video_template,"video"); + + if (err0 < 0) { + pr_debug("%s: can't register video device\n", + dev->name); + goto fail4; + } + + TW68_devcount++; + pr_debug("%s: registered PCI device %d [v4l2]:%d err: |%d| \n", + dev->name, TW68_devcount, dev->video_device[1]->num, err0); + + err0 = TW68_alsa_create(dev); + return 0; + + fail4: + TW68_unregister_video(dev); + free_irq(pci_dev->irq, dev); + fail3: + TW68_hwfini(dev); + iounmap(dev->lmmio); + fail2: + release_mem_region(pci_resource_start(pci_dev,0), + pci_resource_len(pci_dev,0)); + fail1: + v4l2_device_unregister(&dev->v4l2_dev); + fail0: + kfree(dev); + return err; +} + +static void TW68_finidev(struct pci_dev *pci_dev) +{ + int m, n, k = 0; + struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); + struct TW68_dev *dev = container_of(v4l2_dev, struct TW68_dev, v4l2_dev); + + pr_debug("%s: Starting unregister video device %d\n", + dev->name, dev->video_device[1]->num); + + + pr_debug(" /* shutdown hardware */ dev 0x%p \n" , dev); + + /* shutdown hardware */ + TW68_hwfini(dev); + + /* shutdown subsystems */ + + /* unregister */ + mutex_lock(&TW68_devlist_lock); + list_del(&dev->devlist); + mutex_unlock(&TW68_devlist_lock); + TW68_devcount--; + + pr_debug(" list_del(&dev->devlist) \n "); + + + /* the DMA sound modules should be unloaded before reaching + this, but just in case they are still present... */ + //if (dev->dmasound.priv_data != NULL) { + // free_irq(pci_dev->irq, &dev->dmasound); + // dev->dmasound.priv_data = NULL; + //} + + del_timer(&dev->delay_resync); + + /* release resources */ + //remove IRQ + free_irq(pci_dev->irq, dev); //0420 + iounmap(dev->lmmio); + release_mem_region(pci_resource_start(pci_dev,0), + pci_resource_len(pci_dev,0)); + + TW68_pgtable_free(dev->pci, &dev->m_Page0); + + + for (n =0; n<8; n++) + for (m =0; m<4; m++) { + pci_free_consistent(dev->pci, 800*300*2, dev->BDbuf[n][m].cpu, dev->BDbuf[n][m].dma_addr); + } + + TW68_pgtable_free(dev->pci, &dev->m_AudioBuffer); + for (k =0; k<8; k++) { + dma_field_free(&dev->Field_P[k]); + dma_field_free(&dev->Field_B[k]); + } + + TW68_unregister_video(dev); + TW68_alsa_free(dev); + pr_debug(" TW68_unregister_video(dev); \n "); + + //v4l2_device_unregister(&dev->v4l2_dev); + pr_debug(" unregistered v4l2_dev device %d %d %d\n", + TW68_VERSION_CODE >>16, (TW68_VERSION_CODE >>8)&0xFF, TW68_VERSION_CODE &0xFF); + /* free memory */ + kfree(dev); +} + + + +/* ----------------------------------------------------------- */ + +static struct pci_driver TW68_pci_driver = { + .name = "TW6869", + .id_table = TW68_pci_tbl, + .probe = TW68_initdev, + .remove = TW68_finidev, + +//#ifdef CONFIG_PM +// .suspend = TW68_suspend, +// .resume = TW68_resume +//#endif +}; +/* ----------------------------------------------------------- */ + +static int TW68_init(void) +{ + INIT_LIST_HEAD(&TW686v_devlist); + pr_debug("TW68_: v4l2 driver version %d.%d.%d loaded\n", + TW68_VERSION_CODE >>16, (TW68_VERSION_CODE >>8)&0xFF, TW68_VERSION_CODE &0xFF); + + return pci_register_driver(&TW68_pci_driver); +} + +static void TW68_fini(void) +{ + pci_unregister_driver(&TW68_pci_driver); + pr_debug("TW68_: v4l2 driver version %d.%d.%d removed\n", + TW68_VERSION_CODE >>16, (TW68_VERSION_CODE >>8)&0xFF, TW68_VERSION_CODE &0xFF); + +} + +module_init(TW68_init); +module_exit(TW68_fini); diff --git a/drivers/media/pci/TW68/TW68-video.c b/drivers/media/pci/TW68/TW68-video.c new file mode 100644 index 000000000000..7883faa5aeca --- /dev/null +++ b/drivers/media/pci/TW68/TW68-video.c @@ -0,0 +1,2620 @@ +/* + * + * device driver for TW6868 based PCIe analog video capture cards + * video4linux video interface + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/sort.h> + +#include <media/v4l2-common.h> +/// #include <media/rds.h> + +#include "TW68.h" +#include "TW68_defines.h" + +/* ------------------------------------------------------------------ */ + +static unsigned int gbuffers = 8; +static unsigned int noninterlaced; /* 0 */ +static unsigned int gbufsize = 800*576*4; +static unsigned int gbufsize_max = 800*576*4; +static char secam[] = "--"; +static unsigned int VideoFrames_limit = 64; //16 + +module_param(gbuffers, int, 0444); +MODULE_PARM_DESC(gbuffers,"number of capture buffers, range 2-32"); +module_param(noninterlaced, int, 0644); +MODULE_PARM_DESC(noninterlaced,"capture non interlaced video"); +module_param_string(secam, secam, sizeof(secam), 0644); +MODULE_PARM_DESC(secam, "force SECAM variant, either DK,L or Lc"); + +/* ------------------------------------------------------------------ */ +/* data structs for video */ +/* +static int video_out[][9] = { + [CCIR656] = { 0x00, 0xb1, 0x00, 0xa1, 0x00, 0x04, 0x06, 0x00, 0x00 }, +}; +*/ + +static struct TW68_format formats[] = { + { + .name = "15 bpp RGB, le", + .fourcc = V4L2_PIX_FMT_RGB555, + .depth = 16, + .pm = 0x13 | 0x80, + },{ + .name = "16 bpp RGB, le", + .fourcc = V4L2_PIX_FMT_RGB565, + .depth = 16, + .pm = 0x10 | 0x80, + },{ + .name = "4:2:2 packed, YUYV", + .fourcc = V4L2_PIX_FMT_YUYV, + .depth = 16, + .pm = 0x00, + .bswap = 1, + .yuv = 1, + },{ + .name = "4:2:2 packed, UYVY", + .fourcc = V4L2_PIX_FMT_UYVY, + .depth = 16, + .pm = 0x00, + .yuv = 1, + } +}; + +#define FORMATS ARRAY_SIZE(formats) + +#define NORM_625_50 \ + .h_start = 0, \ + .h_stop = 719, \ + .video_v_start = 24, \ + .video_v_stop = 311, \ + .vbi_v_start_0 = 7, \ + .vbi_v_stop_0 = 22, \ + .vbi_v_start_1 = 319, \ + .src_timing = 4 + +#define NORM_525_60 \ + .h_start = 0, \ + .h_stop = 719, \ + .video_v_start = 23, \ + .video_v_stop = 262, \ + .vbi_v_start_0 = 10, \ + .vbi_v_stop_0 = 21, \ + .vbi_v_start_1 = 273, \ + .src_timing = 7 + +static struct TW68_tvnorm tvnorms[] = { + { + .name = "PAL", /* autodetect */ + .id = V4L2_STD_PAL, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x40, + .chroma_ctrl1 = 0x81, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x06, + .vgate_misc = 0x1c, + + },{ + .name = "PAL-BG", + .id = V4L2_STD_PAL_BG, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x40, + .chroma_ctrl1 = 0x81, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x06, + .vgate_misc = 0x1c, + + },{ + .name = "PAL-I", + .id = V4L2_STD_PAL_I, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x40, + .chroma_ctrl1 = 0x81, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x06, + .vgate_misc = 0x1c, + + },{ + .name = "PAL-DK", + .id = V4L2_STD_PAL_DK, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x40, + .chroma_ctrl1 = 0x81, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x06, + .vgate_misc = 0x1c, + + },{ + .name = "NTSC", + .id = V4L2_STD_NTSC, + NORM_525_60, + + .sync_control = 0x59, + .luma_control = 0x40, + .chroma_ctrl1 = 0x89, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x0e, + .vgate_misc = 0x18, + + },{ + .name = "SECAM", + .id = V4L2_STD_SECAM, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x1b, + .chroma_ctrl1 = 0xd1, + .chroma_gain = 0x80, + .chroma_ctrl2 = 0x00, + .vgate_misc = 0x1c, + + },{ + .name = "SECAM-DK", + .id = V4L2_STD_SECAM_DK, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x1b, + .chroma_ctrl1 = 0xd1, + .chroma_gain = 0x80, + .chroma_ctrl2 = 0x00, + .vgate_misc = 0x1c, + + },{ + .name = "SECAM-L", + .id = V4L2_STD_SECAM_L, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x1b, + .chroma_ctrl1 = 0xd1, + .chroma_gain = 0x80, + .chroma_ctrl2 = 0x00, + .vgate_misc = 0x1c, + + },{ + .name = "SECAM-Lc", + .id = V4L2_STD_SECAM_LC, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x1b, + .chroma_ctrl1 = 0xd1, + .chroma_gain = 0x80, + .chroma_ctrl2 = 0x00, + .vgate_misc = 0x1c, + + },{ + .name = "PAL-M", + .id = V4L2_STD_PAL_M, + NORM_525_60, + + .sync_control = 0x59, + .luma_control = 0x40, + .chroma_ctrl1 = 0xb9, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x0e, + .vgate_misc = 0x18, + + },{ + .name = "PAL-Nc", + .id = V4L2_STD_PAL_Nc, + NORM_625_50, + + .sync_control = 0x18, + .luma_control = 0x40, + .chroma_ctrl1 = 0xa1, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x06, + .vgate_misc = 0x1c, + + },{ + .name = "PAL-60", + .id = V4L2_STD_PAL_60, + + .h_start = 0, + .h_stop = 719, + .video_v_start = 23, + .video_v_stop = 262, + .vbi_v_start_0 = 10, + .vbi_v_stop_0 = 21, + .vbi_v_start_1 = 273, + .src_timing = 7, + + .sync_control = 0x18, + .luma_control = 0x40, + .chroma_ctrl1 = 0x81, + .chroma_gain = 0x2a, + .chroma_ctrl2 = 0x06, + .vgate_misc = 0x1c, + } +}; +#define TVNORMS ARRAY_SIZE(tvnorms) + +#define V4L2_CID_PRIVATE_INVERT (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_PRIVATE_Y_ODD (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_PRIVATE_Y_EVEN (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_PRIVATE_AUTOMUTE (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_PRIVATE_LASTP1 (V4L2_CID_PRIVATE_BASE + 4) + +static const struct v4l2_queryctrl no_ctrl = { + .name = "42", + .flags = V4L2_CTRL_FLAG_DISABLED, +}; +static const struct v4l2_queryctrl video_ctrls[] = { + /* --- video --- */ + { + .id = V4L2_CID_BRIGHTNESS, + .name = "Brightness", + .minimum = 0, + .maximum = 255, + .step = 1, + .default_value = 125, + .type = V4L2_CTRL_TYPE_INTEGER, + },{ + .id = V4L2_CID_CONTRAST, + .name = "Contrast", + .minimum = 0, + .maximum = 200, //127 + .step = 1, + .default_value = 96, + .type = V4L2_CTRL_TYPE_INTEGER, + },{ + .id = V4L2_CID_SATURATION, + .name = "Saturation", + .minimum = 0, + .maximum = 127, + .step = 1, + .default_value = 64, + .type = V4L2_CTRL_TYPE_INTEGER, + },{ + .id = V4L2_CID_HUE, + .name = "Hue", + .minimum = -124, //-128, + .maximum = 125, // 127, + .step = 1, + .default_value = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + },{ + .id = V4L2_CID_HFLIP, + .name = "Mirror", + .minimum = 0, + .maximum = 1, + .type = V4L2_CTRL_TYPE_BOOLEAN, + }, + /* --- audio --- */ + { + .id = V4L2_CID_AUDIO_MUTE, + .name = "Mute", + .minimum = 0, + .maximum = 1, + .type = V4L2_CTRL_TYPE_BOOLEAN, + },{ + .id = V4L2_CID_AUDIO_VOLUME, + .name = "Volume", + .minimum = -15, + .maximum = 15, + .step = 1, + .default_value = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, + /* --- private --- */ + { + .id = V4L2_CID_PRIVATE_INVERT, + .name = "Invert", + .minimum = 0, + .maximum = 1, + .type = V4L2_CTRL_TYPE_BOOLEAN, + },{ + .id = V4L2_CID_PRIVATE_Y_ODD, + .name = "y offset odd field", + .minimum = 0, + .maximum = 128, + .step = 1, + .default_value = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + },{ + .id = V4L2_CID_PRIVATE_Y_EVEN, + .name = "y offset even field", + .minimum = 0, + .maximum = 128, + .step = 1, + .default_value = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + },{ + .id = V4L2_CID_PRIVATE_AUTOMUTE, + .name = "automute", + .minimum = 0, + .maximum = 1, + .default_value = 1, + .type = V4L2_CTRL_TYPE_BOOLEAN, + } +}; +static const unsigned int CTRLS = ARRAY_SIZE(video_ctrls); + +static const struct v4l2_queryctrl* ctrl_by_id(unsigned int id) +{ + unsigned int i; + + for (i = 0; i < CTRLS; i++) + if (video_ctrls[i].id == id) + return video_ctrls+i; + return NULL; +} + +static struct TW68_format* format_by_fourcc(unsigned int fourcc) +{ + unsigned int i; + + for (i = 0; i < FORMATS; i++) { + if (formats[i].fourcc == fourcc) { + pr_debug("%s:%d - %x\n", __func__, i, fourcc); + return formats+i; + } + } + pr_info("%s: %x not found\n", __func__, fourcc); + return NULL; +} + +/* ----------------------------------------------------------------------- */ +/* resource management */ + +static int res_get(struct TW68_dev *dev, struct TW68_fh *fh, unsigned int bit) +{ + u32 nId; + + nId = fh->DMA_nCH; + if (nId == 0xF) nId = 0; + + //if (nId >4) return 0; // this for 6864/6868 4 Ch + + /* is it already allocated */ + if (fh->resources & bit) + return 1; + + /* is it free? */ + mutex_lock(&dev->lock); + if (dev->resources[nId] & bit) { + /* no, someone else uses it */ + mutex_unlock(&dev->lock); + + pr_debug("%s: %d dev->resources[nId] %x\n", __func__, bit, dev->resources[nId]); + return 0; + } + /* it's free, grab it */ + fh->resources |= bit; + + //dev->resources[nId] |= bit; + pr_debug("%s: %d\n", __func__, bit); + mutex_unlock(&dev->lock); + return 1; +} + +static int res_check(struct TW68_fh *fh, unsigned int bit) +{ + return (fh->resources & bit); +} + +static int res_locked(struct TW68_fh *fh, struct TW68_dev *dev, unsigned int bit) +{ + u32 nId = fh->DMA_nCH; + + if (nId == 0xF) nId = 0; + // if (nId >4) return 0; + + return (dev->resources[nId] & bit); +} + +static +void res_free(struct TW68_fh *fh, unsigned int bits) +{ + struct TW68_dev *dev = fh->dev; + + //BUG_ON((fh->resources & bits) != bits); + + u32 nId = fh->DMA_nCH; + if (nId == 0xF) nId = 0; + //if (nId >4) return 0; + + mutex_lock(&dev->lock); + fh->resources &= ~bits; + dev->resources[nId] &= ~bits; + pr_debug("%s: put %d\n", __func__, bits); + mutex_unlock(&dev->lock); +} + +/* ------------------------------------------------------------------ */ + +static void set_tvnorm(struct TW68_dev *dev, struct TW68_tvnorm *norm) +{ + int framesize; + + pr_debug("%s: %s\n", __func__, norm->name); + dev->tvnorm = norm; + + /* setup cropping */ + dev->crop_bounds.left = norm->h_start; + dev->crop_defrect.left = norm->h_start; + dev->crop_bounds.width = norm->h_stop - norm->h_start +1; + dev->crop_defrect.width = norm->h_stop - norm->h_start +1; + + dev->crop_bounds.top = (norm->vbi_v_stop_0+1)*2; + dev->crop_defrect.top = norm->video_v_start*2; + dev->crop_bounds.height = ((norm->id & V4L2_STD_525_60) ? 524 : 622) - dev->crop_bounds.top; + dev->crop_defrect.height = (norm->video_v_stop - norm->video_v_start +1)*2; + + dev->crop_current = dev->crop_defrect; + + framesize = dev->crop_bounds.width * dev->crop_bounds.height * 16 >> 3; // calculate byte size for 1 frame + + + pr_debug("%s: crop setting %s, width%d height%d size %d\n", + __func__, norm->name, dev->crop_bounds.width, dev->crop_bounds.height, framesize); + +} + +#if 0 +static void video_mux(struct TW68_dev *dev, int input) +{ + pr_debug("%s: %d input = %d [%s]\n", __func__, dev->ctl_input, input, card_in(dev, input).name); + dev->ctl_input = input; + + pr_debug("%s: dev %p dev->tvnorm=%p\n", __func__, dev, dev->tvnorm); + if (dev->tvnorm) + set_tvnorm(dev, dev->tvnorm); + else + set_tvnorm(dev, &tvnorms[0]); + +} +#endif + + +/* ------------------------------------------------------------------ */ + +struct cliplist { + __u16 position; + __u8 enable; + __u8 disable; +}; + + + +/* ------------------------------------------------------------------ */ + +static int buffer_activate(struct TW68_dev *dev, ///unsigned int nId, + struct TW68_buf *buf, + struct TW68_buf *next) +{ + /// pr_debug("buffer_activate buf=%p\n",buf); + buf->vb.state = VIDEOBUF_ACTIVE; + buf->top_seen = 0; + + return 0; //-1; +} + + + +static void free_buffer(struct videobuf_queue *q, struct TW68_buf *buf) +{ + // struct TW68_fh *fh = q->priv_data; + // struct TW68_dev *dev = fh->dev; + + pr_debug("%s: state= %i\n", __func__, buf->vb.state); + + videobuf_vmalloc_free(&buf->vb); + buf->vb.state = VIDEOBUF_NEEDS_INIT; + pr_debug("%s: %p vb(%p)\n", __func__, buf, &buf->vb ); +} + + +static int buffer_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct TW68_fh *fh = q->priv_data; + struct TW68_dev *dev = fh->dev; + struct TW68_buf *buf = container_of(vb,struct TW68_buf,vb); + unsigned int size; + unsigned int DMA_nCH = fh->DMA_nCH; + unsigned int nId = 0; + + int err; + + if (DMA_nCH == 0XF) + ///DMA_nCH =0; + nId = 0; + //pr_debug(" >>>>buffer_prepare DMA_nCH%x %p vb->baddr:%p, vb->bsize:%d \n", DMA_nCH, vb, vb->baddr, vb->bsize ); + /* sanity checks */ + if (NULL == fh->fmt) + return -EINVAL; + //////////////////////////////////////////////////// + /* + if (fh->width < 48 || + fh->height < 32 || + fh->width/4 > dev->crop_current.width || + fh->height/4 > dev->crop_current.height || + fh->width > dev->crop_bounds.width || + fh->height > dev->crop_bounds.height) + return -EINVAL; + */ + size = (fh->width * fh->height * fh->fmt->depth) >> 3; + if (0 != buf->vb.baddr && buf->vb.bsize < size) + return -EINVAL; + //// cause PAL stop +/////////////////////////////////////////////////////////////////////////////// + if (VIDEOBUF_NEEDS_INIT == buf->vb.state) + { + + buf->vb.width = fh->width; + buf->vb.height = fh->height; + buf->vb.size = size; + buf->vb.field = field; + buf->fmt = fh->fmt; + buf->pt = &fh->pt_cap; + nId = DMA_nCH +1; + + dev->video_dmaq[nId].curr = NULL; + + //pr_debug("buffer_prepare INIT vb->baddr:%x, vb->bsize:%d \n", vb->baddr, vb->bsize ); + + /* + * If I understand correctly, the videobuf_iolock function is + * responsible for mapping user pages to kernel. This works fine + * as long as user application allocates memory/buffer using + * some standard API (malloc/memalign). + * + * But it fails where; user application has allocated memory/ + * buffer using ioremap from another driver. The use case + * scenario is something - + * - Open V4L2 device (which supports scatter gather DMA) + * - Configure the parameters + * (especially .memory=V4L2_MEMORY_USERPTR) + * - Request and query the buffer + * - open another device which will be responsible for + * allocating memory either using ioremap/ + * dma_alloc_coherent/get_free_pages + * - Queue the buffers with buffer address received from + * previous step + * + * Here it internally calls drv_prepare function, which call + * videobuf_iolock API for mapping the user pages to kernel + * and will create scatter-gather (dma->sglist) list. But this + * API returns from videobuf_dma_init_user_locked with -EFAULT. + * + * I found the get_user_pages returns due to flag VM_IO and + * VM_PFNMAP for the corresponding vma. + * + * Any suggestions on how can I achieve this? + */ + err = videobuf_iolock(q,&buf->vb,&dev->ovbuf); // + if (err< 0) + goto oops; + } + + buf->vb.state = VIDEOBUF_PREPARED; + buf->activate = buffer_activate; //set activate fn ptr + return 0; + + oops: + pr_info("%s: OOPS\n", __func__); + free_buffer(q, buf); + return err; +} + + +int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size) +{ + unsigned int ChannelOffset, nId, pgn; + u32 m_dwCHConfig, dwReg, dwRegH, dwRegW, nScaler, dwReg2; + u32 m_StartIdx, m_EndIdx, m_nVideoFormat, \ + m_bHorizontalDecimate, m_bVerticalDecimate, m_nDropChannelNum, \ + m_bDropMasterOrSlave, m_bDropField, m_bDropOddOrEven, m_nCurVideoChannelNum; + + struct TW68_dev *dev; + struct TW68_fh *fh = q->priv_data; + //struct TW68_buf *buf = container_of(vb,struct TW68_buf,vb); + dev = fh->dev; + + ChannelOffset = (PAGE_SIZE <<1) /8 /8; + // NTSC FIELD entry number for 720*240*2 + // ChannelOffset = 128; ///85; + + fh = q->priv_data; + nId = fh ->DMA_nCH; // DMA channel + + dwReg2 = reg_readl(DMA_CH0_CONFIG+ 2); + dwReg = reg_readl(DMA_CH0_CONFIG+ nId); + + pr_debug("%s: CH%d:: dwReg2: 0x%X deReg 0x%X \n", __func__, nId, dwReg2, dwReg ); + + + if (nId == 0XF) { + buffer_setup_QF(q, count, size); + return 0; + } + + *size = fh->fmt->depth * fh->width * fh->height >> 3; // calculate byte size for 1 frame + + + if (nId < 4) { + dwReg = reg_readl(DECODER0_SDT+ (nId*0x10)); + //pr_debug(" ####%%%%%%%%%%%%%%%%%%%%%%% buffer_setup:: DECODER0_SDT %d, 0X%X \n", nId, dwReg); + reg_writel(DECODER0_SDT+ (nId*0x10), 7); /// 0 NTSC + } else { + //pr_debug(" ####%%%%%%%%%%%%%%%%%%%%%%% buffer_setup:: DECODER0_SDT %d, 0X%X \n", nId, dwReg); + } + +////////////////////////////// decoder resize ////////////////////////////////////////// + + + DecoderResize(dev, nId, fh->height/2, fh->width); + + /// Fixed_SG_Mapping(dev, nId, *size); // nDMA_channel + + BFDMA_setup(dev, nId, (fh->height /2), (*size /fh->height)); // BFbuf setup DMA mode ... + + dwReg2 = reg_readl(DMA_CH0_CONFIG+ 2); + dwReg = reg_readl(DMA_CH0_CONFIG+ nId); + + pr_debug("%s: CH%d:: dwReg2: 0x%X deReg 0x%X H:%d W:%d\n", + __func__, nId, dwReg2, dwReg, fh->height /2, (*size /fh->height) ); + + + if (0 == *count) + *count = gbuffers; + + //pgn = (*size + PAGE_SIZE -1) /PAGE_SIZE; + pgn = TW68_buffer_pages(*size /2) -1; // page number for 1 field + + //pgn = (pages+1) /2; + + + //*count = TW68_buffer_count(*size,*count); + while (*size * *count > VideoFrames_limit * 1024 * 1024 *2 ) + (*count)--; + + m_nDropChannelNum = 0; + m_bDropMasterOrSlave = 1; // master + m_bDropField = 0; ////////////////////// 1 + m_bDropOddOrEven = 0; + m_bHorizontalDecimate =0; + m_bVerticalDecimate = 0; + + m_StartIdx = ChannelOffset * nId; + m_EndIdx = m_StartIdx + pgn; ///pgn; 85 :: 720 * 480 + m_nCurVideoChannelNum = 0; // real-time video channel starts 0 + m_nVideoFormat = dev -> nVideoFormat[nId]; + + pr_debug("%s: W:%d H:%d frame size: %d, gbuffers: %d, ChannelOffset: %d field pgn: %d m_StartIdx %d m_EndIdx %d \n", + __func__, fh->width, fh->height, *size, *count, ChannelOffset, pgn, m_StartIdx, m_EndIdx ); + + + m_dwCHConfig = (m_StartIdx & 0x3FF) | // 10 bits + ((m_EndIdx&0x3FF)<<10) | // 10 bits + ((m_nVideoFormat&7)<<20) | + ((m_bHorizontalDecimate&1)<<23) | + ((m_bVerticalDecimate&1)<<24) | + ((m_nDropChannelNum&3)<<25) | + ((m_bDropMasterOrSlave&1)<<27) | // 1 bit + ((m_bDropField&1)<<28) | + ((m_bDropOddOrEven&1)<<29) | + ((m_nCurVideoChannelNum&3)<<30); + + reg_writel(DMA_CH0_CONFIG+ nId, m_dwCHConfig); + dwReg = reg_readl(DMA_CH0_CONFIG+ nId); + pr_debug("%s: CH%d:: m_StartIdx 0X%x pgn%d m_dwCHConfig: 0x%X dwReg: 0x%X \n", + __func__, nId, m_StartIdx, pgn, m_dwCHConfig, dwReg ); + + +//////external video decoder settings////////////////////////////////////////////////////////////////////////// + + dwRegW = fh->width; + dwRegH = fh->height /2; // frame height + + dwReg = dwRegW | (dwRegH<<16) | (1<<31); + dwRegW = dwRegH = dwReg; + + //Video Size + reg_writel(VIDEO_SIZE_REG, dwReg); //for Rev.A backward compatible + /// xxx dwReg = reg_readl(VIDEO_SIZE_REG); + + pr_debug("%s: VIDEO_SIZE_REG: 0x%X, 0x%X \n", __func__, VIDEO_SIZE_REG, dwReg); + + reg_writel(VIDEO_SIZE_REG0+nId, dwReg); //for Rev.B or later only + + //Scaler + dwRegW &= 0x7FF; + dwRegW = (720*256)/dwRegW; + dwRegH = (dwRegH>>16)&0x1FF; + // 60HZ video + dwRegH = (240*256)/dwRegH; + +// 0915 rev B black .... + nScaler = VSCALE1_LO ; /// + (nId<<4); //VSCALE1_LO + 0|0x10|0x20|0x30 + + dwReg = dwRegH & 0xFF; //V + //if(nId >= 4) DeviceWrite2864(nAddr,tmp); + + // reg_writel(nScaler, dwReg); + + nScaler++; //VH + + dwReg = (((dwRegH >> 8)& 0xF) << 4) | ((dwRegW>>8) & 0xF ); + //if(nId >= 4) DeviceWrite2864(nAddr,tmp); + + // reg_writel(nScaler, dwReg); + + nScaler++; //H + dwReg = dwRegW & 0xFF; + ///if(nId >= 4) DeviceWrite2864(nAddr,tmp); + + /// reg_writel(nScaler, dwReg); + + //setup for Black stripe remover + dwRegW = fh->width; /// -12; //EndPos + dwRegH = 4; //StartPos + dwReg = (dwRegW - dwRegH)*(1<<16)/ fh->width; + dwReg = (dwRegH & 0x1F) | + ((dwRegH & 0x3FF) << 5) | + (dwReg <<15); + + reg_writel(DROP_FIELD_REG0+ nId, 0xBFFFFFFF); //28 // B 30 FPS + + //reg_writel(DROP_FIELD_REG0+ nId, 0xBFFFCFFF); // 28 // 26 FPS last xx FC + //reg_writel(DROP_FIELD_REG0+ nId, 0x8FFCFCFF); // 28 // 26 FPS last xx FC + //reg_writel(DROP_FIELD_REG0+ nId, 0xBF3F3F3F); // 24 FPS + //reg_writel(DROP_FIELD_REG0+ nId, 0x8FCFCFCF); // 24 FPS + + dwReg2 = reg_readl(DMA_CH0_CONFIG+ 2); + dwReg = reg_readl(DMA_CH0_CONFIG+ nId); + + pr_debug("%s: CH%d:: dwReg2: 0x%X deReg 0x%X \n", __func__, nId, dwReg2, dwReg ); + return 0; +} + + +static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct TW68_fh *fh = q->priv_data; + struct TW68_buf *buf = container_of(vb,struct TW68_buf,vb); + int nId = fh->DMA_nCH; + + //TW68_buffer_queue(fh->dev,&fh->dev->video_q,buf); + pr_debug("%s: for video DMA nId %x \n", __func__, nId); + + if (nId == 0XF) + nId = 0; + else + nId++; + + TW68_buffer_queue(fh->dev,&fh->dev->video_dmaq[nId], buf); + +} + + +static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct TW68_buf *buf = container_of(vb,struct TW68_buf,vb); + + pr_debug("%s\n", __func__); + free_buffer(q, buf); + +} + + +static struct videobuf_queue_ops video_qops = { + .buf_setup = buffer_setup, + .buf_prepare = buffer_prepare, + .buf_queue = buffer_queue, + .buf_release = buffer_release, +}; + +/* ------------------------------------------------------------------ */ + + +int TW68_g_ctrl_internal(struct TW68_dev *dev, struct TW68_fh *fh, struct v4l2_control *c) +{ + const struct v4l2_queryctrl* ctrl; + int DMA_nCH = fh->DMA_nCH; + int nId = (DMA_nCH +1)& 0xF; + int regval =0; + + ctrl = ctrl_by_id(c->id); + if (NULL == ctrl) + return -EINVAL; + + + switch (c->id) { + case V4L2_CID_BRIGHTNESS: + if (DMA_nCH == 0xF) DMA_nCH = 0; + if (DMA_nCH<4) { + regval = reg_readl(CH1_BRIGHTNESS_REG + DMA_nCH *0x10 ); + regval = (regval + 0x80) &0xFF; + } else { + regval = reg_readl(CH1_BRIGHTNESS_REG + 0x100 + (DMA_nCH -4) *0x10 ); + regval = (regval + 0x80) &0xFF; + } + c->value = dev->video_param[nId].ctl_bright = regval; + break; + case V4L2_CID_HUE: ///-128 +127 + if (DMA_nCH == 0xF) DMA_nCH = 0; + if (DMA_nCH<4) { + regval = reg_readl(CH1_HUE_REG + DMA_nCH *0x10 ); + } else { + regval = reg_readl(CH1_HUE_REG + 0x100 + (DMA_nCH -4) *0x10 ); + } + if (regval < 0x80) + c->value = dev->video_param[nId].ctl_hue = regval; + else + c->value = dev->video_param[nId].ctl_hue = (regval -0x100); + break; + case V4L2_CID_CONTRAST: + if (DMA_nCH == 0xF) DMA_nCH = 0; + if (DMA_nCH<4) { + regval = reg_readl(CH1_CONTRAST_REG + DMA_nCH *0x10 ); + } else { + regval = reg_readl(CH1_CONTRAST_REG + 0x100 + (DMA_nCH -4) *0x10 ); + } + c->value = dev->video_param[nId].ctl_contrast = regval; + break; + case V4L2_CID_SATURATION: + if (DMA_nCH == 0xF) DMA_nCH = 0; + if (DMA_nCH<4) { + regval = reg_readl(CH1_SAT_U_REG + DMA_nCH *0x10 ); + } else { + regval = reg_readl(CH1_SAT_U_REG + 0x100 + (DMA_nCH -4) *0x10 ); + } + c->value = dev->video_param[nId].ctl_saturation = regval /2; + break; + case V4L2_CID_AUDIO_MUTE: + c->value = dev->video_param[nId].ctl_mute; + break; + case V4L2_CID_AUDIO_VOLUME: + c->value = dev->video_param[nId].ctl_volume; + break; + /* + case V4L2_CID_PRIVATE_INVERT: + c->value = dev->video_param[k].ctl_invert; + break; + case V4L2_CID_HFLIP: + c->value = dev->ctl_mirror; + break; + */ + case V4L2_CID_PRIVATE_Y_EVEN: + c->value = dev->video_param[nId].ctl_y_even; + break; + case V4L2_CID_PRIVATE_Y_ODD: + c->value = dev->video_param[nId].ctl_y_odd; + break; + case V4L2_CID_PRIVATE_AUTOMUTE: + c->value = dev->video_param[nId].ctl_automute; + break; + default: + return -EINVAL; + } + pr_debug("%s:nId%d TW68_g_ctrl_internal Get_control name=%s val=%d regval 0x%X \n", + __func__, nId, ctrl->name,c->value, regval); + return 0; +} + + +///EXPORT_SYMBOL_GPL(TW68_g_ctrl_internal); + +static int TW68_g_ctrl(struct file *file, void *priv, struct v4l2_control *c) +{ + struct TW68_fh *fh = priv; + + return TW68_g_ctrl_internal(fh->dev, fh, c); +} + +int TW68_s_ctrl_internal(struct TW68_dev *dev, struct TW68_fh *fh, struct v4l2_control *c) +{ + const struct v4l2_queryctrl* ctrl; + int restart_overlay = 0; + int DMA_nCH, nId, err; + int regval =0;; + DMA_nCH = fh->DMA_nCH; + nId = (DMA_nCH +1)& 0xF; + + + ctrl = ctrl_by_id(c->id); + if (NULL == ctrl) + goto error; + + pr_debug("%s:set_control name=%s val=%d\n", + __func__, ctrl->name,c->value); + + switch (ctrl->type) { + case V4L2_CTRL_TYPE_BOOLEAN: + case V4L2_CTRL_TYPE_MENU: + case V4L2_CTRL_TYPE_INTEGER: + if (c->value < ctrl->minimum) + c->value = ctrl->minimum; + if (c->value > ctrl->maximum) + c->value = ctrl->maximum; + break; + default: + /* nothing */; + }; + + switch (c->id) { + case V4L2_CID_BRIGHTNESS: + dev->video_param[nId].ctl_bright = c->value; + regval = ((c->value - 0x80)) &0xFF; + if (DMA_nCH<4) { + reg_writel(CH1_BRIGHTNESS_REG + DMA_nCH *0x10, regval ); + } else { + if (DMA_nCH<8) { + reg_writel(CH1_BRIGHTNESS_REG + 0x100 +(DMA_nCH -4) *0x10, regval); + } else if (DMA_nCH == 0xF) { + reg_writel(CH1_BRIGHTNESS_REG, regval); + reg_writel(CH2_BRIGHTNESS_REG, regval); + reg_writel(CH3_BRIGHTNESS_REG, regval); + reg_writel(CH4_BRIGHTNESS_REG, regval); + } + } + break; + case V4L2_CID_CONTRAST: + dev->video_param[nId].ctl_contrast = c->value; + if (DMA_nCH<4) { + reg_writel(CH1_CONTRAST_REG + DMA_nCH *0x10, c->value); + } else { + if (DMA_nCH<8) { + reg_writel(CH1_CONTRAST_REG + 0x100 +(DMA_nCH -4) *0x10, c->value); + } else if (DMA_nCH == 0xF) { + reg_writel(CH1_CONTRAST_REG, c->value); + reg_writel(CH2_CONTRAST_REG, c->value); + reg_writel(CH3_CONTRAST_REG, c->value); + reg_writel(CH4_CONTRAST_REG, c->value); + } + } + break; + + case V4L2_CID_HUE: + dev->video_param[nId].ctl_hue = c->value; + regval = c->value; // &0xFF; + if (DMA_nCH<4) { + reg_writel(CH1_HUE_REG + DMA_nCH *0x10, regval); + } else { + if (DMA_nCH<8) { + reg_writel(CH1_HUE_REG + 0x100 +(DMA_nCH -4) *0x10, regval); + } else if (DMA_nCH == 0xF) { + reg_writel(CH1_HUE_REG, regval); + reg_writel(CH2_HUE_REG, regval); + reg_writel(CH3_HUE_REG, regval); + reg_writel(CH4_HUE_REG, regval); + } + } + break; + + case V4L2_CID_SATURATION: + dev->video_param[nId].ctl_saturation = c->value; + regval = c->value *2; + if (DMA_nCH<4) { + reg_writel(CH1_SAT_U_REG + DMA_nCH *0x10, regval); + reg_writel(CH1_SAT_V_REG + DMA_nCH *0x10, regval); + } else { + if (DMA_nCH<8) { + reg_writel(CH1_SAT_U_REG + 0x100 + (DMA_nCH -4)*0x10, regval); + reg_writel(CH1_SAT_V_REG + 0x100 + (DMA_nCH -4)*0x10, regval); + } else if (DMA_nCH == 0xF) { // write wrong addr hang + reg_writel(CH1_SAT_U_REG, regval); + reg_writel(CH1_SAT_V_REG, regval); + reg_writel(CH2_SAT_U_REG, regval); + reg_writel(CH2_SAT_V_REG, regval); + reg_writel(CH3_SAT_U_REG, regval); + reg_writel(CH3_SAT_V_REG, regval); + reg_writel(CH4_SAT_U_REG, regval); + reg_writel(CH4_SAT_V_REG, regval); + } + } + break; + case V4L2_CID_AUDIO_MUTE: + dev->video_param[nId].ctl_mute = c->value; + //TW68__setmute(dev); + break; + case V4L2_CID_AUDIO_VOLUME: + dev->video_param[nId].ctl_volume = c->value; + //TW68_tvaudio_setvolume(dev,dev->ctl_volume); + break; + + case V4L2_CID_PRIVATE_Y_EVEN: + dev->video_param[nId].ctl_y_even = c->value; + restart_overlay = 1; + break; + case V4L2_CID_PRIVATE_Y_ODD: + dev->video_param[nId].ctl_y_odd = c->value; + restart_overlay = 1; + break; + case V4L2_CID_PRIVATE_AUTOMUTE: + { + dev->video_param[nId].ctl_automute = c->value; + break; + } + default: + goto error; + } + err = 0; + pr_debug("%s: set_control name=%s REAL val=%d reg 0x%X\n", + __func__, ctrl->name,c->value, regval); + +error: + return err; +} + + +///EXPORT_SYMBOL_GPL(TW68_s_ctrl_internal); + +static int TW68_s_ctrl(struct file *file, void *f, struct v4l2_control *c) +{ + struct TW68_fh *fh = f; + + return TW68_s_ctrl_internal(fh->dev, fh, c); +} + +/* ------------------------------------------------------------------ */ + +static struct videobuf_queue* TW68_queue(struct TW68_fh *fh) +{ + struct videobuf_queue* q = NULL; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + q = &fh->cap; + //pr_debug("%s: V4L2_BUF_TYPE_VIDEO_CAPTURE 0x%X\n", __func__, q); + break; + case V4L2_BUF_TYPE_VBI_CAPTURE: + q = &fh->vbi; + //pr_debug("%s: V4L2_BUF_TYPE_VBI_CAPTURE .\n", __func__); + break; + default: + pr_err("%s: not valid type, break out\n", __func__); + BUG(); + } + return q; +} + +//////////////////////////////////////////////////////////////////////////// +static int TW68_resource(struct TW68_fh *fh) +{ + if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + return RESOURCE_VIDEO; + + if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) + return RESOURCE_VBI; + + BUG(); + return 0; +} +//////////////////////////////////////////////////////////////////////////// + +static int video_open(struct file *file) +{ + int minor = video_devdata(file)->minor; + struct TW68_dev *dev; + struct TW68_fh *fh; + enum v4l2_buf_type type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + unsigned int request =0; + unsigned int dmaCH; + + int k; //, used; + + // return -ENODEV; + mutex_lock(&TW686v_devlist_lock); + + list_for_each_entry(dev, &TW686v_devlist, devlist) { + pr_debug("%s: minor=%d type=%s opened:%x\n", + __func__, minor, v4l2_type_names[type], dev->video_opened); + + //if (dev->video_dev && (dev->video_dev->minor == minor))v->video_open + //if (dev->video_device[0] && (dev->video_device[0]->minor == minor)) + + for (k=0; k < ARRAY_SIZE(dev->video_device); k++) { + struct video_device *vdev = dev->video_device[k]; + + if (vdev) { + pr_debug("%s: search k=%d vdev=%p, vdev->minor:%d\n", + __func__, k, vdev, vdev->minor); + + if (vdev->minor == minor) + goto found; + } + } + } + + //if (dev->vbi_dev && (dev->vbi_dev->minor == minor)) { + // type = V4L2_BUF_TYPE_VBI_CAPTURE; + // goto found; + //} + + pr_debug("%s: no real device found XXXX \n", __func__); + + mutex_unlock(&TW686v_devlist_lock); + return -ENODEV; + +found: + mutex_unlock(&TW686v_devlist_lock); + if (k ==0) // QF output + request = 0x0F; // internal 4 decoders mux QF + else + request = 1 << (k-1); + + // check video decoder video standard and change default tvnormf + dmaCH =0xF; + if (k>0) dmaCH = k-1; + + pr_debug("%s: ID:%d dmaCH %x request %X \n", __func__, k, dmaCH, request); + + + if (dev->video_opened & request) { + mutex_unlock(&TW686v_devlist_lock); + pr_debug("%s: EBUSY dev->video_opened %x request %x \n", + __func__, dev->video_opened, request); + return -EBUSY; + } + + dev->video_opened = dev->video_opened |request; + + if (k) + dev->video_dmaq[k].DMA_nCH = k-1; + else + dev->video_dmaq[k].DMA_nCH = 0x0F; // 0X0F; + + /* allocate + initialize per filehandle data */ + fh = kzalloc(sizeof(*fh),GFP_KERNEL); + if (NULL == fh) + return -ENOMEM; + + pr_debug("%s: kzalloc successful!\n", __func__); + + if (VideoDecoderDetect(dev, dmaCH) == 50) { + dev->tvnormf[k] = &tvnorms[0]; + dev->PAL50[k] = 1; + fh->dW = PAL_default_width; + fh->dH = PAL_default_height; + } else { + dev->tvnormf[k] = &tvnorms[4]; + dev->PAL50[k] = 0; + fh->dW = NTSC_default_width; + fh->dH = NTSC_default_height; + } + + pr_debug("%s: 0X%p open /dev/video%d minor%d type=%s video_opened=0x%X k:%d tvnorm::%s %d\n", + __func__, dev, dev->video_device[k]->num, minor, // 0901 array + v4l2_type_names[V4L2_BUF_TYPE_VIDEO_CAPTURE], dev->video_opened, k, dev->tvnormf[k]->name, dev->PAL50[k]); + + file->private_data = fh; + fh->dev = dev; + fh->DMA_nCH = dev->video_dmaq[k].DMA_nCH; /// k; /// DMA index +1 + fh->type = type; + /// fh->fmt = format_by_fourcc(V4L2_PIX_FMT_UYVY); /// RGB24 + fh->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV); /// YUY2 by default + fh->width = fh->dW; //704; //720; + fh->height = fh->dH; //576; + + pr_debug("%s: minor=%d fh->DMA_nCH= 0x%X type=%s\n", + __func__, minor, fh->DMA_nCH, v4l2_type_names[type]); + + v4l2_prio_open(&dev->prio,&fh->prio); + pr_debug("%s: v4l2_prio_open() successful!\n", __func__); + +//6.1 add mutex * + videobuf_queue_vmalloc_init(&fh->cap, &video_qops, + NULL, &dev->slock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_INTERLACED, + sizeof(struct TW68_buf), + fh + //); //6.0 + , NULL); + // 6.1 + + //video_mux(dev,dev->ctl_input); + return 0; +} + +static ssize_t video_read(struct file *file, char __user *data, size_t count, + loff_t *ppos) +{ + struct TW68_fh *fh = file->private_data; + + switch (fh->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + if (res_locked(fh, fh->dev,RESOURCE_VIDEO)) + return -EBUSY; + return videobuf_read_one(TW68_queue(fh), + data, count, ppos, + file->f_flags & O_NONBLOCK); + case V4L2_BUF_TYPE_VBI_CAPTURE: + if (!res_get(fh->dev,fh,RESOURCE_VBI)) + return -EBUSY; + return videobuf_read_stream(TW68_queue(fh), + data, count, ppos, 1, + file->f_flags & O_NONBLOCK); + break; + default: + BUG(); + return 0; + } +} + +static unsigned int +video_poll(struct file *file, struct poll_table_struct *wait) +{ + struct TW68_fh *fh = file->private_data; + struct videobuf_buffer *buf = NULL; + unsigned int rc = 0; + + //pr_debug("%s\n", __func__); + if (V4L2_BUF_TYPE_VIDEO_CAPTURE != fh->type) + return POLLERR; + + ///return videobuf_poll_stream(file, q, wait); + + if (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type) + return videobuf_poll_stream(file, &fh->vbi, wait); + + if (res_check(fh,RESOURCE_VIDEO)) { + //mutex_lock(&fh->cap.vb_lock); + if (!list_empty(&fh->cap.stream)) + buf = list_entry(fh->cap.stream.next, struct videobuf_buffer, stream); + } else { + mutex_lock(&fh->cap.vb_lock); + if (UNSET == fh->cap.read_off) { + /* need to capture a new frame */ + if (res_locked(fh, fh->dev,RESOURCE_VIDEO)) + goto err; + if (0 != fh->cap.ops->buf_prepare(&fh->cap,fh->cap.read_buf,fh->cap.field)) + goto err; + fh->cap.ops->buf_queue(&fh->cap,fh->cap.read_buf); + fh->cap.read_off = 0; + } + mutex_unlock(&fh->cap.vb_lock); + buf = fh->cap.read_buf; + } + + if (!buf) + goto err; + + poll_wait(file, &buf->done, wait); + if (buf->state == VIDEOBUF_DONE || + buf->state == VIDEOBUF_ERROR) + rc = POLLIN|POLLRDNORM; + mutex_unlock(&fh->cap.vb_lock); + return rc; + +err: + mutex_unlock(&fh->cap.vb_lock); + return POLLERR; +} + + +static int video_release(struct file *file) +{ + int minor = video_devdata(file)->minor; + + struct TW68_fh *fh = file->private_data; + struct TW68_dev *dev = fh->dev; + int DMA_nCH = fh->DMA_nCH; + int nId = DMA_nCH +1; + + pr_debug("%s: minor:%d DMA_nCH: %X video_fieldcount 0x%X ! \n", + __func__, minor, DMA_nCH, dev->video_fieldcount[DMA_nCH]); /// 0-8 + + + if (DMA_nCH ==0x0F) { + dev->video_opened &= ~(DMA_nCH ); + dev->video_dmaq[0].DMA_nCH = 0; + dev->video_fieldcount[0] =0; + stop_video_DMA(dev, 0); + stop_video_DMA(dev, 1); + stop_video_DMA(dev, 2); + stop_video_DMA(dev, 3); + + dev->video_fieldcount[0] =0; + stop_video_DMA(dev, 0); + del_timer(&dev->video_dmaq[0].timeout); + + } else { + dev->video_opened &= ~(1 << DMA_nCH ); /// set opened flag free + stop_video_DMA(dev, DMA_nCH ); // fh->DMA_nCH = DMA ID + dev->video_dmaq[nId].DMA_nCH = 0; + dev->video_fieldcount[nId] =0; + del_timer(&dev->video_dmaq[nId].timeout); + + } + + pr_debug("%s: dev->video_opened: 0x%x \n", __func__, dev->video_opened); + videobuf_streamoff(&fh->cap); + + //pr_debug(" stop video capture CALLED ! \n"); + + if (fh->cap.read_buf) { + buffer_release(&fh->cap,fh->cap.read_buf); + kfree(fh->cap.read_buf); + } + + //v4l2_prio_close(&dev->prio, (enum v4l2_priority *)(&fh->prio)); + file->private_data = NULL; + kfree(fh); + return 0; +} + +static int video_mmap(struct file *file, struct vm_area_struct * vma) +{ + struct TW68_fh *fh = file->private_data; + + pr_debug("%s: vma= %lx %lx %lx \n", __func__, vma->vm_start, + vma->vm_end, (vma->vm_end - vma->vm_start)); + return videobuf_mmap_mapper(TW68_queue(fh), vma); +} + +/* ------------------------------------------------------------------ */ + +static int TW68_try_get_set_fmt_vbi_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + struct TW68_tvnorm *norm = dev->tvnorm; + + f->fmt.vbi.sampling_rate = 6750000 * 4; + f->fmt.vbi.samples_per_line = 2048 /* VBI_LINE_LENGTH */; + f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY; + f->fmt.vbi.offset = 64 * 4; + f->fmt.vbi.start[0] = norm->vbi_v_start_0; + f->fmt.vbi.count[0] = norm->vbi_v_stop_0 - norm->vbi_v_start_0 +1; + f->fmt.vbi.start[1] = norm->vbi_v_start_1; + f->fmt.vbi.count[1] = f->fmt.vbi.count[0]; + f->fmt.vbi.flags = 0; /* VBI_UNSYNC VBI_INTERLACED */ + + return 0; +} + +static int TW68_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct TW68_fh *fh = priv; + + pr_debug("%s: fh(%p) v4l2_format(%p)\n", __func__, priv, f); + + f->fmt.pix.width = fh->width; + f->fmt.pix.height = fh->height; + f->fmt.pix.field = fh->cap.field; + f->fmt.pix.pixelformat = fh->fmt->fourcc; + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fh->fmt->depth) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + + pr_debug("%s: width %d height %d \n", __func__, f->fmt.pix.width, f->fmt.pix.height); + return 0; +} + +static int TW68_g_fmt_vid_overlay(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct TW68_fh *fh = priv; + + TW68_g_fmt_vid_cap(file, priv, f); + return 0; + + + /* + if (TW68_no_overlay > 0) { + pr_err("V4L2_BUF_TYPE_VIDEO_OVERLAY: no_overlay\n"); + return -EINVAL; + } + f->fmt.win = fh->win; + */ + + f->fmt.pix.width = fh->width; + f->fmt.pix.height = fh->height; + f->fmt.pix.field = fh->cap.field; + f->fmt.pix.pixelformat = fh->fmt->fourcc; + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fh->fmt->depth) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + + pr_debug("%s: width %d height %d \n", __func__, f->fmt.pix.width, f->fmt.pix.height); + return 0; +} + +static int TW68_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + struct TW68_format *fmt; + enum v4l2_field field; + unsigned int maxw, maxh; + u32 k; + u32 nId = fh ->DMA_nCH; + + fmt = format_by_fourcc(f->fmt.pix.pixelformat); + pr_debug("TW68 input nId:%x try_fmt:: %x | width %d height %d\n", + nId, f->fmt.pix.pixelformat, f->fmt.pix.width, f->fmt.pix.height ); + + if (NULL == fmt ) { + pr_debug("TW68 fmt:: no valid pixel format \n"); + return -EINVAL; + } + + + if ((V4L2_PIX_FMT_YUYV) != fmt->fourcc) { + if ((V4L2_PIX_FMT_UYVY) != fmt->fourcc) { /// Only allow UYVY 0727)) + pr_debug("TW68 fmt:: not YUV422 !!!!!!!!!!!!!!!!!!! \n"); + return -EINVAL; + } else { + if (nId<8) { + dev -> nVideoFormat[nId] = VIDEO_FORMAT_UYVY; + } else { + dev -> nVideoFormat[0] = VIDEO_FORMAT_UYVY; + dev -> nVideoFormat[1] = VIDEO_FORMAT_UYVY; + dev -> nVideoFormat[2] = VIDEO_FORMAT_UYVY; + dev -> nVideoFormat[3] = VIDEO_FORMAT_UYVY; + } + } + } else { + if (nId<8) { + dev -> nVideoFormat[nId] = VIDEO_FORMAT_YUYV; + } else { + dev -> nVideoFormat[0] = VIDEO_FORMAT_YUYV; + dev -> nVideoFormat[1] = VIDEO_FORMAT_YUYV; + dev -> nVideoFormat[2] = VIDEO_FORMAT_YUYV; + dev -> nVideoFormat[3] = VIDEO_FORMAT_YUYV; + } + } + + if (nId > 8) + k =0; + else + k = nId+1; + + if (dev->tvnormf[k]->id & V4L2_STD_525_60) { + maxw = 720; + maxh = 480; + } else { + maxw = 720; + maxh = 576; + } + + pr_debug("%s: tvnormf %d ->name %s id %X maxh %d \n", __func__, nId, + dev->tvnormf[nId]->name, (unsigned int)dev->tvnormf[nId]->id, maxh); + + field = f->fmt.pix.field; + + if (V4L2_FIELD_ANY == field) { + field = (f->fmt.pix.height > maxh/2) + ? V4L2_FIELD_INTERLACED + : V4L2_FIELD_BOTTOM; + } + switch (field) { + case V4L2_FIELD_TOP: + case V4L2_FIELD_BOTTOM: + case V4L2_FIELD_ALTERNATE: + maxh = maxh / 2; + break; + case V4L2_FIELD_INTERLACED: + break; + default: + return -EINVAL; + } + + f->fmt.pix.field = field; + + pr_debug("%s: pixelformat %x field: %d _fmt: width %d height %d \n", + __func__, fmt->fourcc, field, f->fmt.pix.width, f->fmt.pix.height); + + v4l_bound_align_image(&f->fmt.pix.width, 128, maxw, 2, // 4 pixel test 360 4, + &f->fmt.pix.height, 60, maxh, 0, 0); + + f->fmt.pix.bytesperline = + (f->fmt.pix.width * fmt->depth) >> 3; + f->fmt.pix.sizeimage = + f->fmt.pix.height * f->fmt.pix.bytesperline; + + pr_debug("%s: width %d height %d %d %d \n", __func__, f->fmt.pix.width, f->fmt.pix.height, maxw, maxh); + return 0; +} + + +static int TW68_try_fmt_vid_overlay(struct file *file, void *priv, + struct v4l2_format *f) +{ + //struct TW68_fh *fh = priv; + //struct TW68_dev *dev = fh->dev; + + TW68_try_fmt_vid_cap(file, priv, f); + return 0; + + if (TW68_no_overlay > 0) { + pr_err("V4L2_BUF_TYPE_VIDEO_OVERLAY: no_overlay\n"); + return -EINVAL; + } + return 0; //verify_preview(dev, &f->fmt.win); +} + +static int TW68_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct TW68_fh *fh = priv; + int err; + + pr_debug("%s: %x W:%d H:%d field:%X\n", __func__, f->fmt.pix.pixelformat, fh->width, fh->height, fh->cap.field); + + err = TW68_try_fmt_vid_cap(file, priv, f); + if (0 != err) + return err; + + fh->fmt = format_by_fourcc(f->fmt.pix.pixelformat); + fh->width = f->fmt.pix.width; + fh->height = f->fmt.pix.height; + fh->cap.field = f->fmt.pix.field; + + pr_debug("%s: fh->fmt W:%d H:%d field:%X\n", __func__, fh->width, fh->height, fh->cap.field); + return 0; +} + + +static int TW68_s_fmt_vid_overlay(struct file *file, void *priv, + struct v4l2_format *f) +{ + pr_debug("%s\n", __func__); + TW68_try_fmt_vid_cap(file, priv, f); + return 0; +} + +int TW68_queryctrl(struct file *file, void *priv, struct v4l2_queryctrl *c) +{ + const struct v4l2_queryctrl *ctrl; + + if ((c->id < V4L2_CID_BASE || + c->id >= V4L2_CID_LASTP1) && + (c->id < V4L2_CID_PRIVATE_BASE || + c->id >= V4L2_CID_PRIVATE_LASTP1)) + return -EINVAL; + ctrl = ctrl_by_id(c->id); + *c = (NULL != ctrl) ? *ctrl : no_ctrl; + return 0; +} +///EXPORT_SYMBOL_GPL(TW68_queryctrl); + +static int TW68_enum_input(struct file *file, void *priv, + struct v4l2_input *i) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + unsigned int n; + + n = i->index; + pr_debug("%s: i=%p n:%x\n", __func__, i, n); + + if (n >= 4) + return -EINVAL; + if (NULL == card_in(dev, i->index).name) + return -EINVAL; + memset(i, 0, sizeof(*i)); + i->index = n; + i->type = V4L2_INPUT_TYPE_CAMERA; + strcpy(i->name, card_in(dev, n).name); + /* + if (card_in(dev, n).tv) + i->type = V4L2_INPUT_TYPE_TUNER; + i->audioset = 1; + */ + if (n == dev->ctl_input) { + } + i->std = TW68_NORMS; + + i->type = V4L2_INPUT_TYPE_CAMERA; + sprintf(i->name, "Composite%d", n); + + /* + ///if(n == dev->input) { + if (n == dev->ctl_input) { + vstatus = dev->vstatus; + if (0 != (vstatus & BIT(7))) + i->status |= V4L2_IN_ST_NO_SIGNAL; + if (0 == (vstatus & BIT(6))) + i->status |= V4L2_IN_ST_NO_H_LOCK; + if (0 != (vstatus & BIT(1))) + i->status |= V4L2_IN_ST_NO_COLOR; + } + */ + return 0; +} + +static int TW68_g_input(struct file *file, void *priv, unsigned int *i) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + + *i = dev->ctl_input; + return 0; +} + +static int TW68_s_input(struct file *file, void *priv, unsigned int i) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + + pr_debug("%s: i=%d\n", __func__, i); + + if (i < 0 || i >= TW68_INPUT_MAX) + return -EINVAL; + if (NULL == card_in(dev, i).name) + return -EINVAL; + + pr_debug("%s: card in name: %s i=%d\n", + __func__, card_in(dev, i).name, i); + return 0; +} + +static int TW68_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + + // unsigned int tuner_type = dev->tuner_type; + + pr_debug("%s\n", __func__); + + strcpy(cap->driver, "TW--6868"); + strlcpy(cap->card, TW68_boards[dev->board].name, + sizeof(cap->card)); + sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci)); + cap->version = TW68_VERSION_CODE; + cap->capabilities = + V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_VBI_CAPTURE | + V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING | + V4L2_CAP_TUNER; + if (TW68_no_overlay <= 0) + cap->capabilities |= V4L2_CAP_VIDEO_OVERLAY; + + pr_debug("%s exit\n", __func__); + return 0; +} + +int TW68_s_std_internal(struct TW68_dev *dev, struct TW68_fh *fh, v4l2_std_id id) +{ + unsigned int i, nId; + v4l2_std_id fixup; + + for (i = 0; i < TVNORMS; i++) + if (id == tvnorms[i].id) + break; + + if (i == TVNORMS) + for (i = 0; i < TVNORMS; i++) + if (id & tvnorms[i].id) + break; + if (i == TVNORMS) + return -EINVAL; + + if ((id & V4L2_STD_SECAM) && (secam[0] != '-')) { + if (secam[0] == 'L' || secam[0] == 'l') { + if (secam[1] == 'C' || secam[1] == 'c') + fixup = V4L2_STD_SECAM_LC; + + else + fixup = V4L2_STD_SECAM_L; + } else { + if (secam[0] == 'D' || secam[0] == 'd') + fixup = V4L2_STD_SECAM_DK; + else + fixup = V4L2_STD_SECAM; + } + for (i = 0; i < TVNORMS; i++) + if (fixup == tvnorms[i].id) + break; + } + + id = tvnorms[i].id; + + pr_debug("%s: id=%x i=%x\n", __func__, (int)id, i); + nId = fh->DMA_nCH; + + if (nId == 0XF) + nId = 0; + + mutex_lock(&dev->lock); + set_tvnorm(dev, &tvnorms[i]); + dev ->tvnormf[nId] = &tvnorms[i]; + mutex_unlock(&dev->lock); + return 0; +} + + +static int TW68_s_std(struct file *file, void *priv, v4l2_std_id id) +{ + struct TW68_fh *fh = priv; + // struct TW68_dev *dev = fh->dev; + int nId = fh->DMA_nCH; + + if (nId == 0XF) + nId = 0; + + pr_debug("%s:id=%d\n", __func__, (int)id); + return TW68_s_std_internal(fh->dev, fh, id); +} + + +static int TW68_g_std(struct file *file, void *priv, v4l2_std_id *id) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + int nId = fh->DMA_nCH; + + *id = dev->tvnorm->id; + + if (nId == 0XF) + nId = 0; + + + *id = dev->tvnormf[nId]->id; + + pr_debug("%s: id=%d\n", __func__, (int)*id); + return 0; +} + +static int TW68_cropcap(struct file *file, void *priv, + struct v4l2_cropcap *cap) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + + pr_debug("%s\n", __func__); + + if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) + return -EINVAL; + + cap->bounds = dev->crop_bounds; + cap->defrect = dev->crop_defrect; + cap->pixelaspect.numerator = 1; + cap->pixelaspect.denominator = 1; + + pr_debug("%s dev->tvnorm->id:0x%x\n", __func__, (unsigned)dev->tvnorm->id); + if (dev->tvnorm->id & V4L2_STD_525_60) { + cap->pixelaspect.numerator = 11; + cap->pixelaspect.denominator = 10; + } + if (dev->tvnorm->id & V4L2_STD_625_50) { + cap->pixelaspect.numerator = 54; + cap->pixelaspect.denominator = 59; + } + + pr_debug("%s success\n", __func__); + return 0; +} + +static int TW68_g_crop(struct file *file, void *f, struct v4l2_crop *crop) +{ + struct TW68_fh *fh = f; + struct TW68_dev *dev = fh->dev; + + pr_debug("%s\n", __func__); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) + return -EINVAL; + crop->c = dev->crop_current; + return 0; +} + +static int TW68_s_crop(struct file *file, void *f, const struct v4l2_crop *crop) +{ + struct TW68_fh *fh = f; + struct TW68_dev *dev = fh->dev; + struct v4l2_rect *b = &dev->crop_bounds; + struct v4l2_rect c; + + pr_debug("%s\n", __func__); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) + return -EINVAL; + if (crop->c.height < 0) + return -EINVAL; + if (crop->c.width < 0) + return -EINVAL; + + if (res_locked(fh, fh->dev, RESOURCE_OVERLAY)) + return -EBUSY; + if (res_locked(fh, fh->dev, RESOURCE_VIDEO)) + return -EBUSY; + + c = crop->c; + if (c.top < b->top) + c.top = b->top; + if (c.top > b->top + b->height) + c.top = b->top + b->height; + if (c.height > b->top - crop->c.top + b->height) + c.height = b->top - crop->c.top + b->height; + + if (c.left < b->left) + c.left = b->left; + if (c.left > b->left + b->width) + c.left = b->left + b->width; + if (c.width > b->left - crop->c.left + b->width) + c.width = b->left - crop->c.left + b->width; + + dev->crop_current = c; + return 0; +} + + + +static int TW68_g_tuner(struct file *file, void *priv, + struct v4l2_tuner *t) +{ + if (t->index != 0) + return -EINVAL; + return 0; +} + +static int TW68_s_tuner(struct file *file, void *priv, + const struct v4l2_tuner *t) +{ + return 0; +} + +static int TW68_g_frequency(struct file *file, void *priv, + struct v4l2_frequency *f) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + + f->frequency = dev->ctl_freq; + return 0; +} + + +static int TW68_s_frequency(struct file *file, void *priv, + const struct v4l2_frequency *f) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + + if (0 != f->tuner) + return -EINVAL; + mutex_lock(&dev->lock); + dev->ctl_freq = f->frequency; + + //reg_call_all(dev, tuner, s_frequency, f); + + mutex_unlock(&dev->lock); + return 0; +} + + +static int TW68_g_audio(struct file *file, void *priv, struct v4l2_audio *a) +{ + strcpy(a->name, "audio"); + return 0; +} + +static int TW68_s_audio(struct file *file, void *priv, const struct v4l2_audio *a) +{ + return 0; +} + + +static int TW68_g_priority(struct file *file, void *f, enum v4l2_priority *p) +{ + struct TW68_fh *fh = f; + struct TW68_dev *dev = fh->dev; + + *p = v4l2_prio_max(&dev->prio); + return 0; +} + + +static int TW68_s_priority(struct file *file, void *f, + enum v4l2_priority prio) +{ + return 0; +} + +static int TW68_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + + if (f->index >= FORMATS) + return -EINVAL; + + strlcpy(f->description, formats[f->index].name, + sizeof(f->description)); + + f->pixelformat = formats[f->index].fourcc; + + pr_debug("%s: description %s \n", __func__, f->description); + + return 0; +} + +static int TW68_enum_fmt_vid_overlay(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + pr_debug("%s\n", __func__); + + if (TW68_no_overlay > 0) { + pr_err("V4L2_BUF_TYPE_VIDEO_OVERLAY: no_overlay\n"); + return -EINVAL; + } + + if ((f->index >= FORMATS) || formats[f->index].planar) + return -EINVAL; + + strlcpy(f->description, formats[f->index].name, + sizeof(f->description)); + + f->pixelformat = formats[f->index].fourcc; + return 0; +} + +static int TW68_g_fbuf(struct file *file, void *f, + struct v4l2_framebuffer *fb) +{ + struct TW68_fh *fh = f; + struct TW68_dev *dev = fh->dev; + + pr_debug("%s\n", __func__); + *fb = dev->ovbuf; + fb->capability = V4L2_FBUF_CAP_LIST_CLIPPING; + return 0; +} + +static int TW68_s_fbuf(struct file *file, void *f, + const struct v4l2_framebuffer *fb) +{ + struct TW68_fh *fh = f; + struct TW68_dev *dev = fh->dev; + struct TW68_format *fmt; + + pr_debug("%s\n", __func__); + + if (!capable(CAP_SYS_ADMIN) && + !capable(CAP_SYS_RAWIO)) + return -EPERM; + + /* check args */ + fmt = format_by_fourcc(fb->fmt.pixelformat); + if (NULL == fmt) + return -EINVAL; + + /* ok, accept it */ + dev->ovbuf = *fb; + dev->ovfmt = fmt; + if (0 == dev->ovbuf.fmt.bytesperline) + dev->ovbuf.fmt.bytesperline = + dev->ovbuf.fmt.width*fmt->depth/8; + return 0; +} + +static int TW68_overlay(struct file *file, void *f, unsigned int on) +{ + struct TW68_fh *fh = f; + struct TW68_dev *dev = fh->dev; + // unsigned long flags; + + pr_debug("%s\n", __func__); + if (on) { + if (TW68_no_overlay > 0) { + pr_debug("no_overlay\n"); + return -EINVAL; + } + + if (!res_get(dev, fh, RESOURCE_OVERLAY)) + return -EBUSY; + } + if (!on) { + if (!res_check(fh, RESOURCE_OVERLAY)) + return -EINVAL; + res_free(fh, RESOURCE_OVERLAY); + } + return 0; +} + +#ifdef CONFIG_VIDEO_V4L1_COMPAT +static int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf) +{ + struct TW68_fh *fh = file->private_data; + return videobuf_cgmbuf(TW68_queue(fh), mbuf, 8); +} +#endif + +static int TW68_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *p) +{ + struct TW68_fh *fh = priv; + return videobuf_reqbufs(TW68_queue(fh), p); +} + +static int TW68_querybuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct TW68_fh *fh = priv; + return videobuf_querybuf(TW68_queue(fh), b); +} + +static int TW68_qbuf(struct file *file, void *priv, struct v4l2_buffer *b) +{ + struct TW68_fh *fh = priv; + + struct videobuf_queue* q = NULL; + q = TW68_queue(fh); + + //pr_debug("%s: videobuf_queue: 0X%p v4l2_buffer: 0X%p.\n", __func__, q, b); + + return videobuf_qbuf(q, b); +} + +static int TW68_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) +{ + struct TW68_fh *fh = priv; + + struct videobuf_queue* q = NULL; + q = &fh->cap; + + //pr_debug("%s: videobuf_queue: 0X%p 0X%p v4l2_buffer: 0X%p.\n", __func__, q, TW68_queue(fh), b); + //TW68_queue(fh) + + return videobuf_dqbuf(q, b, file->f_flags & O_NONBLOCK); +} + +static int TW68_streamon(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + struct videobuf_queue *q; + int res = TW68_resource(fh); + int streaming; + u32 nId; + + + if (!res_get(dev, fh, res)) { + return -EBUSY; + } + + // fh->resources |= res; + + nId = fh->DMA_nCH; + if (nId == 0XF) + nId = 0; + + q = TW68_queue(fh); + + //TW68_buffer_requeue(dev, &dev->video_dmaq[nId]); + streaming = videobuf_streamon(q); + pr_debug("%s: %s: DMA %d q->streaming:%X streaming:%x.\n", + __func__, dev->name, fh->DMA_nCH, q->streaming, streaming); + + /////////////////////////////////////////// + + //dwReg2 = reg_readl(DMA_CH0_CONFIG+ 2); + //dwReg = reg_readl(DMA_CH0_CONFIG+ nId); + + //pr_debug("%s: CH%d:: dwReg2: 0x%X deReg 0x%X \n", __func__, nId, dwReg2, dwReg ); + + //read dma config + if (fh->DMA_nCH == 0XF) { + dev->video_dmaq[0].DMA_nCH = 0xF; + dev->video_dmaq[0].DMA_nCH = 0xF; // mark in use + + dev->video_DMA_1st_started += 4; //++ + dev->videoCap_ID |= 0xF ; + dev->videoDMA_ID |= 0xF ; + } else { + TW68_set_dmabits(dev, fh->DMA_nCH); + } + + return streaming; +} + + +static int TW68_streamoff(struct file *file, void *priv, + enum v4l2_buf_type type) +{ + int err; + struct TW68_fh *fh = priv; + struct TW68_dev *dev = fh->dev; + int DMA_nCH = fh->DMA_nCH; + int nId = DMA_nCH +1; + struct videobuf_queue *q; + int res = TW68_resource(fh); + q=TW68_queue(fh); + + + if (DMA_nCH ==0x0F) { + dev->video_fieldcount[0] =0; + stop_video_DMA(dev, 0); // + stop_video_DMA(dev, 1); // + stop_video_DMA(dev, 2); // + stop_video_DMA(dev, 3); // + + dev->video_fieldcount[0] =0; + stop_video_DMA(dev, 0); // + del_timer(&dev->video_dmaq[0].timeout); + } else { + nId = DMA_nCH +1; + dev->video_fieldcount[nId] =0; + stop_video_DMA(dev, DMA_nCH ); // + del_timer(&dev->video_dmaq[nId].timeout); + } + + pr_debug("%s: %s: DMA_nCH:%x videobuf_streamoff delete video timeout \n", + __func__, dev->name, fh->DMA_nCH); + stop_video_DMA(dev, fh->DMA_nCH); + + err = videobuf_streamoff(q); + res_free(fh, res); + pr_debug("%s: %s:%d q->streaming:%x return err:%x \n", + __func__, dev->name, fh->DMA_nCH, q->streaming, err ); + + return 0; +} + + +static int TW68_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + return 0; +} + + + +static const struct v4l2_file_operations video_fops = +{ + .owner = THIS_MODULE, + .open = video_open, + .release = video_release, + .read = video_read, + .poll = video_poll, + .mmap = video_mmap, + .ioctl = video_ioctl2, +}; + +static const struct v4l2_ioctl_ops video_ioctl_ops = { + .vidioc_querycap = TW68_querycap, + .vidioc_enum_fmt_vid_cap = TW68_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = TW68_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = TW68_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = TW68_s_fmt_vid_cap, + .vidioc_enum_fmt_vid_overlay = TW68_enum_fmt_vid_overlay, + .vidioc_g_fmt_vid_overlay = TW68_g_fmt_vid_overlay, + .vidioc_try_fmt_vid_overlay = TW68_try_fmt_vid_overlay, + .vidioc_s_fmt_vid_overlay = TW68_s_fmt_vid_overlay, + .vidioc_g_fmt_vbi_cap = TW68_try_get_set_fmt_vbi_cap, + .vidioc_try_fmt_vbi_cap = TW68_try_get_set_fmt_vbi_cap, + .vidioc_s_fmt_vbi_cap = TW68_try_get_set_fmt_vbi_cap, + .vidioc_g_audio = TW68_g_audio, + .vidioc_s_audio = TW68_s_audio, + .vidioc_cropcap = TW68_cropcap, + .vidioc_reqbufs = TW68_reqbufs, + .vidioc_querybuf = TW68_querybuf, + .vidioc_qbuf = TW68_qbuf, + .vidioc_dqbuf = TW68_dqbuf, + .vidioc_s_std = TW68_s_std, + .vidioc_g_std = TW68_g_std, + .vidioc_enum_input = TW68_enum_input, + .vidioc_g_input = TW68_g_input, + .vidioc_s_input = TW68_s_input, + .vidioc_queryctrl = TW68_queryctrl, + .vidioc_g_ctrl = TW68_g_ctrl, + .vidioc_s_ctrl = TW68_s_ctrl, + .vidioc_streamon = TW68_streamon, + .vidioc_streamoff = TW68_streamoff, + .vidioc_g_tuner = TW68_g_tuner, + .vidioc_s_tuner = TW68_s_tuner, +#ifdef CONFIG_VIDEO_V4L1_COMPAT + .vidiocgmbuf = vidiocgmbuf, +#endif + .vidioc_g_crop = TW68_g_crop, + .vidioc_s_crop = TW68_s_crop, + .vidioc_g_fbuf = TW68_g_fbuf, + .vidioc_s_fbuf = TW68_s_fbuf, + .vidioc_overlay = TW68_overlay, + .vidioc_g_priority = TW68_g_priority, + .vidioc_s_priority = TW68_s_priority, + .vidioc_g_parm = TW68_g_parm, + .vidioc_g_frequency = TW68_g_frequency, + .vidioc_s_frequency = TW68_s_frequency, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .vidioc_g_register = vidioc_g_register, + .vidioc_s_register = vidioc_s_register, +#endif +}; + + +/* ----------------------------------------------------------- */ +/* exported stuff */ + +struct video_device TW68_video_template = { + .name = "TW686v-video", + .fops = &video_fops, + .ioctl_ops = &video_ioctl_ops, + .minor = -1, + .tvnorms = TW68_NORMS, + .current_norm = V4L2_STD_NTSC, +}; + + + +int TW68_video_init1(struct TW68_dev *dev) +{ + int k, m, n; + __le32 *cpu; + dma_addr_t dma_addr; + /* sanitycheck insmod options */ + if (gbuffers < 2 || gbuffers > VIDEO_MAX_FRAME) + gbuffers = 2; + if (gbufsize < 0 || gbufsize > gbufsize_max) + gbufsize = gbufsize_max; + gbufsize = (gbufsize + PAGE_SIZE - 1) & PAGE_MASK; + +// pci_alloc_consistent 32 4 * 8 continuous field memory buffer + + for (n = 0; n < 8; n++) { + for (m = 0; m < 4; m++) { + cpu = pci_alloc_consistent(dev->pci, 800*300*2, &dma_addr); // 8* 4096 contiguous //*2 + dev->BDbuf[n][m].cpu = cpu; + dev->BDbuf[n][m].dma_addr = dma_addr; + //pr_debug("%s: n:%dm:%d cpu:%x dma:%x \n", __func__, n, m, cpu, dma_addr); + // assume aways successful 480k each field total 32 <16MB + } + } + /* put some sensible defaults into the data structures ... */ + dev->ctl_bright = ctrl_by_id(V4L2_CID_BRIGHTNESS)->default_value; + dev->ctl_contrast = ctrl_by_id(V4L2_CID_CONTRAST)->default_value; + dev->ctl_hue = ctrl_by_id(V4L2_CID_HUE)->default_value; + dev->ctl_saturation = ctrl_by_id(V4L2_CID_SATURATION)->default_value; + dev->ctl_volume = ctrl_by_id(V4L2_CID_AUDIO_VOLUME)->default_value; + dev->ctl_mute = 1; // ctrl_by_id(V4L2_CID_AUDIO_MUTE)->default_value; + dev->ctl_invert = ctrl_by_id(V4L2_CID_PRIVATE_INVERT)->default_value; + dev->ctl_automute = ctrl_by_id(V4L2_CID_PRIVATE_AUTOMUTE)->default_value; + + ////////////////////////////////////////////////////////xxxxxxxxxxx + INIT_LIST_HEAD(&dev->video_q.queued); + + init_timer(&dev->delay_resync); //1021 + dev->delay_resync.function = resync; + dev->delay_resync.data = (unsigned long)dev; ///(unsigned long)(&dev); + mod_timer(&dev->delay_resync, jiffies+ msecs_to_jiffies(30)); + + + ////////////////////////////////////////////////////////xxxxxxxxxxx + + for (k=0; k<9; k++) { + INIT_LIST_HEAD(&dev->video_dmaq[k].queued); + + INIT_LIST_HEAD(&dev->video_dmaq[k].active); + + dev->video_dmaq[k].dev = dev; + init_timer(&dev->video_dmaq[k].timeout); + + dev->video_dmaq[k].timeout.function = TW68_buffer_timeout; + dev->video_dmaq[k].timeout.data = (unsigned long)(&dev->video_dmaq[k]); + + if (0) { + dev->video_param[k].ctl_bright = ctrl_by_id(V4L2_CID_BRIGHTNESS)->default_value; + dev->video_param[k].ctl_contrast = ctrl_by_id(V4L2_CID_CONTRAST)->default_value; + dev->video_param[k].ctl_hue = ctrl_by_id(V4L2_CID_HUE)->default_value; + dev->video_param[k].ctl_saturation = ctrl_by_id(V4L2_CID_SATURATION)->default_value; + dev->video_param[k].ctl_volume = ctrl_by_id(V4L2_CID_AUDIO_VOLUME)->default_value; + dev->video_param[k].ctl_mute = 1; // ctrl_by_id(V4L2_CID_AUDIO_MUTE)->default_value; + dev->video_param[k].ctl_automute = ctrl_by_id(V4L2_CID_PRIVATE_AUTOMUTE)->default_value; + } + + if (k<4) { + dev->video_param[k].ctl_bright = reg_readl(CH1_BRIGHTNESS_REG + k *0x10); + dev->video_param[k].ctl_contrast = reg_readl(CH1_CONTRAST_REG + k *0x10); + dev->video_param[k].ctl_hue = reg_readl(CH1_HUE_REG + k *0x10); + dev->video_param[k].ctl_saturation = reg_readl(CH1_SAT_U_REG + k *0x10) /2; + dev->video_param[k].ctl_mute = reg_readl(CH1_SAT_V_REG + k *0x10) /2; + } else if (k<8) { + dev->video_param[k].ctl_bright = reg_readl(CH1_BRIGHTNESS_REG + (k-4) *0x10 +0x100); + dev->video_param[k].ctl_contrast = reg_readl(CH1_CONTRAST_REG + (k-4) *0x10 +0x100); + dev->video_param[k].ctl_hue = reg_readl(CH1_HUE_REG + (k-4) *0x10 +0x100); + dev->video_param[k].ctl_saturation = reg_readl(CH1_SAT_U_REG + (k-4) *0x10 +0x100) /2; + dev->video_param[k].ctl_mute = reg_readl(CH1_SAT_V_REG + (k-4) *0x10 +0x100) /2; + } + + pr_debug("%s: get decoder %d default AMP: BRIGHTNESS %d CONTRAST %d HUE_ %d SAT_U_%d SAT_V_%d\n", + __func__, k, dev->video_param[k].ctl_bright, + dev->video_param[k].ctl_contrast, + dev->video_param[k].ctl_hue, + dev->video_param[k].ctl_saturation, + dev->video_param[k].ctl_mute); + + } + + for (k=8; k>0; k--) { + dev->video_param[k].ctl_bright = dev->video_param[k-1].ctl_bright; + dev->video_param[k].ctl_contrast = dev->video_param[k-1].ctl_contrast; + dev->video_param[k].ctl_hue = dev->video_param[k-1].ctl_hue; + dev->video_param[k].ctl_saturation = dev->video_param[k-1].ctl_saturation; + dev->video_param[k].ctl_mute = dev->video_param[k-1].ctl_mute; + pr_debug("%s: get decoder %d default AMP: BRIGHTNESS %d CONTRAST %d HUE_ %d SAT_U_%d SAT_V_%d\n", + __func__, k, dev->video_param[k].ctl_bright, + dev->video_param[k].ctl_contrast, + dev->video_param[k].ctl_hue, + dev->video_param[k].ctl_saturation, + dev->video_param[k].ctl_mute); + } + + // Normalize the reg value to standard value range + for (k=0; k<9; k++) { + dev->video_param[k].ctl_bright = (dev->video_param[k].ctl_bright + 0x80) & 0xFF; + dev->video_param[k].ctl_contrast = dev->video_param[k].ctl_contrast & 0x7F; + dev->video_param[k].ctl_hue = dev->video_param[k].ctl_hue & 0xFF; + dev->video_param[k].ctl_saturation = dev->video_param[k].ctl_saturation & 0xFF; + dev->video_param[k].ctl_mute = dev->video_param[k].ctl_mute & 0xFF; + pr_debug("%s: remap decoder %d default AMP: BRIGHTNESS %d CONTRAST %d HUE_ %d SAT_U_%d SAT_V_%d\n", + __func__, k, dev->video_param[k].ctl_bright, + dev->video_param[k].ctl_contrast, + dev->video_param[k].ctl_hue, + dev->video_param[k].ctl_saturation, + dev->video_param[k].ctl_mute); + } + return 0; +} + + +int TW68_video_init2(struct TW68_dev *dev) +{ + /* init video hw */ + + int k; + pr_debug("%s\n", __func__); + set_tvnorm(dev,&tvnorms[0]); + + for (k=0; k<9; k++) + dev->tvnormf[k] = &tvnorms[0]; + + + //video_mux(dev,0); ///0 3 + //TW68_tvaudio_setmute(dev); + //TW68_tvaudio_setvolume(dev,dev->ctl_volume); + return 0; +} + +void TW68_irq_video_done(struct TW68_dev *dev, unsigned int nId, u32 dwRegPB) +{ + enum v4l2_field field; + static int Done; + int Fn, PB; /// d0, w0, + + Fn = (dwRegPB >>24) & (1<< (nId-1)); + PB = (dwRegPB ) & (1<< (nId-1)); + + if ((dev->video_dmaq[0].DMA_nCH == 0xF ) && ((nId-1) < 4) ) { + if ((dev->video_dmaq[0].curr)) { + //if (dev->QFbit ^ (1 << nId)) { + dev->video_dmaq[0].FieldPB = dwRegPB; + QF_Field_Copy(dev, (nId-1), Fn, PB); + dev->QFbit |= (1 << (nId-1)); + //} + pr_debug("%s: dev->QFbit=0X%x nId=0X%x\n", __func__, dev->QFbit, nId); + + if ((dev->QFbit & 0xF) == 0xF) { + dev->QFbit =0; + TW68_buffer_finish(dev, &dev->video_dmaq[0], VIDEOBUF_DONE); + TW68_buffer_next(dev,&(dev->video_dmaq[0])); + } + } + return; + } + + + pr_debug("%s: nId=0x%x .curr(%p) dwRegPB=0x%x\n", __func__, nId, dev->video_dmaq[nId].curr, dwRegPB); + if (dev->video_dmaq[nId].curr) { + dev->video_fieldcount[nId]++; + field = dev->video_dmaq[nId].curr->vb.field; + //pr_debug("%s: video_dmaq[nId].curr nId %x dwRegPB 0x%X\n", __func__, nId, dwRegPB); + dev->video_dmaq[nId].curr->vb.field_count = dev->video_fieldcount[nId]; + + Fn = (dwRegPB >>24) & (1<< (nId-1)); + PB = (dwRegPB ) & (1<< (nId-1)); + //pr_debug("%s: d0:%d w0:%d \n", __func__, d0, w0); + + // skip a field +#if 0 + if (d0 == w0) { + //dev->video_dmaq[nId].FieldPB = 0; + pr_debug("%s: dropped a field d0:%d w0:%d \n", __func__, d0, w0); + goto done; + } +#endif + + //if (dev->video_fieldcount[nId] %2) + // weave frame output + if (Fn ==0) { + // field 0 interrupt program update P field mapping + Done = BF_Copy(dev, nId-1, Fn, PB); + //Done =1; + //pr_debug("%s: nId%x Fn:%d field count = %d\n", __func__, nId, Fn, dev->video_fieldcount[nId]); + goto done; + } else { + // copy bottom field + //dev->video_dmaq[nId].FieldPB &= (~1); + if (Done) + BF_Copy(dev, nId-1, Fn, PB); + //pr_debug("%s: nId%x Fn:%d BBB field count = %d \n", __func__, nId, Fn, dev->video_fieldcount[nId]); + if(!Done) + goto done; + TW68_buffer_finish(dev, &dev->video_dmaq[nId], VIDEOBUF_DONE); + } + } + // B field interrupt program update P field mapping + TW68_buffer_next(dev,&(dev->video_dmaq[nId])); + done: + return; +} + + +int buffer_setup_QF(struct videobuf_queue *q, unsigned int *count, unsigned int *size) +{ + unsigned int ChannelOffset, nId, pgn; + u32 m_dwCHConfig, dwReg, dwRegH, dwRegW, nScaler, nW, nH, nSize; + u32 m_StartIdx, m_EndIdx, m_nVideoFormat, \ + m_bHorizontalDecimate, m_bVerticalDecimate, m_nDropChannelNum, \ + m_bDropMasterOrSlave, m_bDropField, m_bDropOddOrEven, m_nCurVideoChannelNum; + + struct TW68_dev *dev; + struct TW68_fh *fh = q->priv_data; + dev = fh->dev; + + dev->video_dmaq[0].DMA_nCH = 0xF; + dev->video_dmaq[0].curr = 0; + dev->QFbit = 0; + + ChannelOffset = (PAGE_SIZE <<1) /8 /8; + // NTSC FIELD entry number for 720*240*2 + /// ChannelOffset = 128; ///85; + + fh = q->priv_data; + + *size = fh->fmt->depth * fh->width * fh->height >> 3; // calculate byte size for 1 frame + + nW = fh->width /2; + nH = fh->height /2; + nSize = *size /4; // field size + + for (nId = 0; nId < 4; nId++) { + if (nId < 4) { + dwReg = reg_readl(DECODER0_SDT+ (nId*0x10)); + pr_debug("%s: nId %d, 0X%X nW%d nH%d nSize%d\n", + __func__, nId, dwReg, nW, nH, nSize); + reg_writel(DECODER0_SDT+ (nId*0x10), 7); /// 0 NTSC + } + ////////////////////////////// decoder resize ////////////////////////////////////////// + + DecoderResize(dev, nId, nH, nW); // Field size + + //Fixed_SG_Mapping(dev, nId, nSize*2); // nDMA_channel + + BFDMA_setup(dev, nId, fh->height /2, (*size /fh->height /2)); // BFbuf setup DMA mode ... + + if (0 == *count) + *count = gbuffers; + + //pgn = (*size + PAGE_SIZE -1) /PAGE_SIZE; + pgn = TW68_buffer_pages(nSize) -1; // page number for 1 field + + m_nDropChannelNum = 0; + m_bDropMasterOrSlave = 1; // master + m_bDropField = 0; ////////////////////// 1 + m_bDropOddOrEven = 0; + m_bHorizontalDecimate = 0; + m_bVerticalDecimate = 0; + + m_StartIdx = ChannelOffset * nId; + m_EndIdx = m_StartIdx + pgn; ///pgn; 85 :: 720 * 480 + m_nCurVideoChannelNum = 0; // real-time video channel starts 0 + m_nVideoFormat = dev -> nVideoFormat[nId]; + //if (m_nVideoFormat != dev -> nVideoFormat[nId]) + pr_debug("%s: N%d F%d to %d\n", __func__, nId, + m_nVideoFormat, dev -> nVideoFormat[nId]); + + pr_debug("%s: W:%d H:%d frame size: %d, gbuffers: %d, ChannelOffset: %d field pgn: %d m_StartIdx %d m_EndIdx %d m_nVideoFormat %x\n", + __func__, fh->width, fh->height, *size, *count, + ChannelOffset, pgn, m_StartIdx, m_EndIdx, m_nVideoFormat ); + + m_dwCHConfig = (m_StartIdx & 0x3FF) | // 10 bits + ((m_EndIdx&0x3FF)<<10) | // 10 bits + ((m_nVideoFormat&7)<<20) | + ((m_bHorizontalDecimate&1)<<23) | + ((m_bVerticalDecimate&1)<<24) | + ((m_nDropChannelNum&3)<<25) | + ((m_bDropMasterOrSlave&1)<<27) | // 1 bit + ((m_bDropField&1)<<28) | + ((m_bDropOddOrEven&1)<<29) | + ((m_nCurVideoChannelNum&3)<<30); + + reg_writel(DMA_CH0_CONFIG+ nId, m_dwCHConfig); + dwReg = reg_readl(DMA_CH0_CONFIG+ nId); + pr_debug("%s: CH%d:: m_StartIdx 0X%x pgn%d dwReg: 0x%X m_dwCHConfig 0x%X \n", + __func__, nId, m_StartIdx, pgn, m_dwCHConfig, dwReg ); + + + /* external video decoder settings */ + + dwRegW = nW; + dwRegH = nH; // field height + + dwReg = dwRegW | (dwRegH<<16) | (1<<31); + dwRegW = dwRegH = dwReg; + + //Video Size + reg_writel(VIDEO_SIZE_REG, dwReg); //for Rev.A backward compatible + //xxx dwReg = reg_readl(VIDEO_SIZE_REG); + + pr_debug("%s: VIDEO_SIZE_REG: 0x%X, 0x%X \n", __func__, VIDEO_SIZE_REG, dwReg); + + reg_writel(VIDEO_SIZE_REG0+nId, dwReg); //for Rev.B or later only + + //Scaler + dwRegW &= 0x7FF; + dwRegW = (720*256)/dwRegW; + dwRegH = (dwRegH>>16)&0x1FF; + // 60HZ video + dwRegH = (240*256)/dwRegH; + + /// 0915 rev B black .... + nScaler = VSCALE1_LO ; /// + (nId<<4); //VSCALE1_LO + 0|0x10|0x20|0x30 + + + dwReg = dwRegH & 0xFF; //V + nScaler++; //VH + + dwReg = (((dwRegH >> 8)& 0xF) << 4) | ((dwRegW>>8) & 0xF ); + ///if(nId >= 4) DeviceWrite2864(nAddr,tmp); + + /// reg_writel(nScaler, dwReg); + + nScaler++; //H + dwReg = dwRegW & 0xFF; + + //setup for Black stripe remover + dwRegW = fh->width; ///-12; //EndPos + dwRegH = 4; //StartPos + dwReg = (dwRegW - dwRegH)*(1<<16)/ fh->width; + dwReg = (dwRegH & 0x1F) | + ((dwRegH & 0x3FF) << 5) | + (dwReg <<15); + reg_writel(DROP_FIELD_REG0+ nId, 0xBFFFFFFF); //28 // B 30 FPS + } + return 0; +} diff --git a/drivers/media/pci/TW68/TW68.h b/drivers/media/pci/TW68/TW68.h new file mode 100644 index 000000000000..fcf9ba093f32 --- /dev/null +++ b/drivers/media/pci/TW68/TW68.h @@ -0,0 +1,704 @@ +/* + * + * v4l2 device driver for TW6868 based CVBS PCIe cards + * + * (c) 2011,2012 Simon Xu @ Intersil + * + */ + +#include <linux/version.h> +#include <linux/pci.h> +#include <linux/i2c.h> +#include <linux/videodev2.h> +#include <linux/kdev_t.h> +#include <linux/input.h> +#include <linux/notifier.h> +#include <linux/delay.h> +#include <linux/mutex.h> + +#include <asm/io.h> +#include <linux/kthread.h> +#include <linux/highmem.h> +#include <linux/freezer.h> + +#include <media/videobuf-vmalloc.h> +#include <media/v4l2-common.h> +#include <media/v4l2-ioctl.h> +#include <media/v4l2-device.h> +#include <media/tuner.h> +////#include <media/ir-common.h> +////#include <media/ir-kbd-i2c.h> +#include <media/videobuf-dma-sg.h> +#include <sound/core.h> +#include <sound/pcm.h> + +#define TW68_VERSION_CODE KERNEL_VERSION(2, 3, 1) + +#define UNSET (-1U) + +/* ----------------------------------------------------------- */ +/* enums */ + +enum TW68_tvaudio_mode { + TVAUDIO_FM_MONO = 1, + TVAUDIO_FM_BG_STEREO = 2, + TVAUDIO_FM_SAT_STEREO = 3, + TVAUDIO_FM_K_STEREO = 4, + TVAUDIO_NICAM_AM = 5, + TVAUDIO_NICAM_FM = 6, +}; + +enum TW68_audio_in { + TV = 1, + LINE1 = 2, + LINE2 = 3, + LINE3 = 4, + LINE4 = 5, + LINE2_LEFT, +}; + +enum TW68_video_out { + CCIR656 = 1, +}; + +/* ----------------------------------------------------------- */ +/* static data */ + +struct TW68_tvnorm { + char *name; + v4l2_std_id id; + + /* video decoder */ + unsigned int sync_control; + unsigned int luma_control; + unsigned int chroma_ctrl1; + unsigned int chroma_gain; + unsigned int chroma_ctrl2; + unsigned int vgate_misc; + + /* video scaler */ + unsigned int h_start; + unsigned int h_stop; + unsigned int video_v_start; + unsigned int video_v_stop; + unsigned int vbi_v_start_0; + unsigned int vbi_v_stop_0; + unsigned int src_timing; + unsigned int vbi_v_start_1; +}; + +struct TW68_tvaudio { + char *name; + v4l2_std_id std; + enum TW68_tvaudio_mode mode; + int carr1; + int carr2; +}; + +struct TW68_format { + char *name; + unsigned int fourcc; + unsigned int depth; + unsigned int pm; + unsigned int vshift; /* vertical downsampling (for planar yuv) */ + unsigned int hshift; /* horizontal downsampling (for planar yuv) */ + unsigned int bswap:1; + unsigned int wswap:1; + unsigned int yuv:1; + unsigned int planar:1; + unsigned int uvswap:1; +}; + +/* ----------------------------------------------------------- */ +/* card configuration */ + +#define TW68_BOARD_UNKNOWN 0 +#define TW68_BOARD_A 1 + + +#define TW68_MAXBOARDS 4 +#define TW68_INPUT_MAX 4 + +#define PAL_default_width 704 +#define NTSC_default_width 704 + +#define PAL_default_height 576 +#define NTSC_default_height 480 + +/* ----------------------------------------------------------- */ +/* Since we support 2 remote types, lets tell them apart */ + +#define TW68_REMOTE_GPIO 1 +#define TW68_REMOTE_I2C 2 + +/* ----------------------------------------------------------- */ +/* Video Output Port Register Initialization Options */ + +#define SET_T_CODE_POLARITY_NON_INVERTED (1 << 0) +#define SET_CLOCK_NOT_DELAYED (1 << 1) +#define SET_CLOCK_INVERTED (1 << 2) +#define SET_VSYNC_OFF (1 << 3) + +struct TW68_input { + char *name; + unsigned int vmux; + enum TW68_audio_in amux; + unsigned int gpio; + unsigned int tv:1; +}; + + +struct TW68_board { + char *name; + unsigned int audio_clock; + + /* input switching */ + unsigned int gpiomask; + struct TW68_input inputs[TW68_INPUT_MAX]; + struct TW68_input radio; + struct TW68_input mute; + + /* i2c chip info */ + + unsigned int tuner_type; + unsigned int radio_type; + unsigned char tuner_addr; + unsigned char radio_addr; + unsigned char empress_addr; + unsigned char rds_addr; + + unsigned int tuner_config; + + /* peripheral I/O */ + enum TW68_video_out video_out; + unsigned int vid_port_opts; +}; + +/* +#define card_has_radio(dev) (NULL != TW6864_boards[dev->board].radio.name) +#define card_is_empress(dev) (TW6864_MPEG_EMPRESS == TW6864_boards[dev->board].mpeg) +#define card_is_dvb(dev) (TW6864_MPEG_DVB == TW6864_boards[dev->board].mpeg) +#define card_has_mpeg(dev) (TW6864_MPEG_UNUSED != TW6864_boards[dev->board].mpeg) +*/ +#define card(dev) (TW68_boards[dev->board]) +#define card_in(dev,n) (TW68_boards[dev->board].inputs[n]) + +/* ----------------------------------------------------------- */ +/* device / file handle status */ + +#define RESOURCE_OVERLAY 1 +#define RESOURCE_VIDEO 2 +#define RESOURCE_VBI 4 + +#define INTERLACE_AUTO 0 +#define INTERLACE_ON 1 +#define INTERLACE_OFF 2 + +#define BUFFER_TIMEOUT msecs_to_jiffies(500) /* 0.5 seconds */ +#define TS_BUFFER_TIMEOUT msecs_to_jiffies(1000) /* 1 second */ + +#define RINGSIZE 8 + +struct TW68_dev; + +/* TW686_ page table */ +struct TW68_pgtable { + unsigned int size; + __le32 *cpu; + dma_addr_t dma; +}; + +/* tvaudio thread status */ +struct TW68_thread { + struct task_struct *thread; + unsigned int scan1; + unsigned int scan2; + unsigned int mode; + unsigned int stopped; +}; + +/* buffer for one video/vbi/ts frame */ +struct TW68_buf { + /* common v4l buffer stuff -- must be first */ + struct videobuf_buffer vb; + + struct TW68_format *fmt; + unsigned int top_seen; + int (*activate)(struct TW68_dev *dev, + struct TW68_buf *buf, + struct TW68_buf *next); + + /* page tables */ + struct TW68_pgtable *pt; +}; + +struct TW68_dmaqueue { + struct TW68_dev *dev; + struct TW68_buf *curr; + + struct list_head active; + struct list_head queued; + struct timer_list timeout; + unsigned int DMA_nCH; /// + unsigned int FieldPB; /// Top Bottom status, field copy order; + unsigned int FCN; /// + struct timer_list restarter; +}; + +/* video filehandle status */ +struct TW68_fh { + struct TW68_dev *dev; + unsigned int DMA_nCH; + enum v4l2_buf_type type; + unsigned int resources; + enum v4l2_priority prio; + + /* video overlay */ + struct v4l2_window win; + struct v4l2_clip clips[8]; + unsigned int nclips; + + /* video capture */ + struct TW68_format *fmt; + unsigned int width,height; + + //set default video standard and frame size + unsigned int dW, dH; // default width hight + + struct videobuf_queue cap; + struct TW68_pgtable pt_cap; + + /* vbi capture */ + struct videobuf_queue vbi; + struct TW68_pgtable pt_vbi; + + +}; + +/* dmasound dsp status */ +struct TW68_dmasound { + struct mutex lock; + int minor_mixer; + int minor_dsp; + unsigned int users_dsp; + + /* mixer */ + enum TW68_audio_in input; + unsigned int count; + unsigned int line1; + unsigned int line2; + + /* dsp */ + unsigned int afmt; + unsigned int rate; + unsigned int channels; + unsigned int recording_on; + unsigned int dma_running; + unsigned int blocks; + unsigned int blksize; + unsigned int bufsize; + struct TW68_pgtable pt; + struct videobuf_dmabuf dma; + unsigned int dma_blk; + unsigned int read_offset; + unsigned int read_count; + void * priv_data; + struct snd_pcm_substream *substream; +}; + + + +/** + * struct dma_region - large non-contiguous DMA buffer + * @virt: kernel virtual address + * @dev: PCI device + * @n_pages: number of kernel pages + * @n_dma_pages: number of IOMMU pages + * @sglist: IOMMU mapping + * @direction: PCI_DMA_TODEVICE, etc. + * + * a large, non-physically-contiguous DMA buffer with streaming, asynchronous + * usage characteristics + */ + +struct DMA_Descriptor { + u32 control; + u32 address; +}; + +struct dma_region { + unsigned char *kvirt; + struct pci_dev *dev; + unsigned int n_pages; + unsigned int n_dma_pages; + struct scatterlist *sglist; + int direction; +}; + +struct video_ctrl { + int ctl_bright; + int ctl_contrast; + int ctl_hue; + int ctl_saturation; + int ctl_freq; + int ctl_mute; /* audio */ + int ctl_volume; + int ctl_y_odd; + int ctl_y_even; + int ctl_automute; +}; + +struct dma_mem{ + __le32 *cpu; + dma_addr_t dma_addr; +}; + +/* global device status */ +struct TW68_dev { + struct list_head devlist; + struct mutex lock; + spinlock_t slock; + struct v4l2_prio_state prio; + struct v4l2_device v4l2_dev; + + struct snd_card *card; // sound card + + /* workstruct for loading modules */ + struct work_struct request_module_wk; + + /* insmod option/autodetected */ + int autodetected; + + /* various device info */ + unsigned int video_opened; + int video_DMA_1st_started; + int err_times; // DMA errors counter + unsigned int vfd_DMA_num[9]; + unsigned int deadbeef[9]; + struct timer_list delay_resync; + unsigned int resources[16]; + struct video_device *video_dev; + struct video_device *video_device[9]; /// QF 0 + 8 + struct dma_region Field_P[8]; + struct dma_region Field_B[8]; + unsigned int nVideoFormat[8]; + struct dma_mem BDbuf[8][4]; + + struct video_device *radio_dev; + struct video_device *vbi_dev; + struct TW68_dmasound dmasound; + + /// DMA smart control + unsigned int videoDMA_ID; + unsigned int videoCap_ID; + unsigned int videoRS_ID; + + unsigned int videoDMA_run[8]; + unsigned int videoDecoderST[8]; + + + unsigned int TCN; + unsigned int skip; + + + struct ringbuf { + int rxhead, rxtail; + int PB_REG[ RINGSIZE ]; + int ST_REG[ RINGSIZE ]; + } DMA_PB; + + u64 errlog[9]; // latest errors jiffies + + /* infrared remote */ + int has_remote; + struct card_ir *remote; + + /* pci i/o */ + char name[32]; + int nr; + struct pci_dev *pci; + unsigned char pci_rev,pci_lat; + __u32 __iomem *lmmio; + __u8 __iomem *bmmio; + +// 2010 +// allocate common buffer for DMA entry tables SG buffer P&B + struct TW68_pgtable m_Page0; + struct TW68_pgtable m_Page1; + + struct TW68_pgtable m_AudioBuffer; + + /* config info */ + unsigned int board; + unsigned int tuner_type; + + + /* video overlay */ + struct v4l2_framebuffer ovbuf; + struct TW68_format *ovfmt; + unsigned int ovenable; + enum v4l2_field ovfield; + + /* video+ts+vbi capture */ + struct TW68_dmaqueue video_q; + struct TW68_dmaqueue vbi_q; + + unsigned int QFbit; // Quad Frame interrupt bits + struct TW68_dmaqueue video_dmaq[9]; + unsigned int video_fieldcount[9]; + //unsigned int vbi_fieldcount; + + /* various v4l controls */ + struct TW68_tvnorm *tvnorm; /* video */ + struct TW68_tvnorm *tvnormf[9]; /* video */ + unsigned int PAL50[9]; + + struct TW68_tvaudio *tvaudio; + + unsigned int ctl_input; + int ctl_bright; + int ctl_contrast; + int ctl_hue; + int ctl_saturation; + int ctl_freq; + int ctl_mute; /* audio */ + int ctl_volume; + int ctl_invert; /* private */ + int ctl_mirror; + int ctl_y_odd; + int ctl_y_even; + int ctl_automute; + + struct video_ctrl video_param[9]; + + + /* crop */ + struct v4l2_rect crop_bounds; + struct v4l2_rect crop_defrect; + struct v4l2_rect crop_current; + + /* other global state info */ + unsigned int automute; + struct TW68_thread thread; + struct TW68_input *input; + struct TW68_input *hw_input; + unsigned int hw_mute; + int last_carrier; + int nosignal; + unsigned int insuspend; + + /* I2C keyboard data */ +/// struct i2c_board_info info; +/// struct IR_i2c_init_data init_data; + + void (*gate_ctrl)(struct TW68_dev *dev, int open); +}; + + +/* ----------------------------------------------------------- */ + +#define reg_readl(reg) readl(dev->lmmio + (reg)) +#define reg_writel(reg,value) writel((value), dev->lmmio + (reg)); +#define reg_andorl(reg,mask,value) \ + writel((readl(dev->lmmio+(reg)) & ~(mask)) |\ + ((value) & (mask)), dev->lmmio+(reg)) +#define reg_setl(reg,bit) reg_andorl((reg),(bit),(bit)) +#define reg_clearl(reg,bit) reg_andorl((reg),(bit),0) + +#define reg_readb(reg) readb(dev->bmmio + (reg)) +#define reg_writeb(reg,value) writeb((value), dev->bmmio + (reg)); +#define reg_andorb(reg,mask,value) \ + writeb((readb(dev->bmmio+(reg)) & ~(mask)) |\ + ((value) & (mask)), dev->bmmio+(reg)) +#define reg_setb(reg,bit) reg_andorb((reg),(bit),(bit)) +#define reg_clearb(reg,bit) reg_andorb((reg),(bit),0) + +#define reg_wait(us) { udelay(us); } + +#define TW68_NORMS (\ + V4L2_STD_PAL | V4L2_STD_PAL_N | \ + V4L2_STD_PAL_Nc | V4L2_STD_SECAM | \ + V4L2_STD_NTSC | V4L2_STD_PAL_M | \ + V4L2_STD_PAL_60) + +/* +#define GRP_EMPRESS (1) +#define reg_call_all(dev, o, f, args...) do { \ + if (dev->gate_ctrl) \ + dev->gate_ctrl(dev, 1); \ + v4l2_device_call_all(&(dev)->v4l2_dev, 0, o, f , ##args); \ + if (dev->gate_ctrl) \ + dev->gate_ctrl(dev, 0); \ +} while (0) + +#define reg_call_empress(dev, o, f, args...) ({ \ + long _rc; \ + if (dev->gate_ctrl) \ + dev->gate_ctrl(dev, 1); \ + _rc = v4l2_device_call_until_err(&(dev)->v4l2_dev, \ + GRP_EMPRESS, o, f , ##args); \ + if (dev->gate_ctrl) \ + dev->gate_ctrl(dev, 0); \ + _rc; \ +}) +*/ +/* ----------------------------------------------------------- */ +/* TW68-core.c */ + +#define _PGTABLE_SIZE 4096 + +extern struct list_head TW686v_devlist; +extern struct mutex TW686v_devlist_lock; + +extern int TW68_no_overlay; + +//void TW68_track_gpio(struct TW6864_dev *dev, char *msg); +//void TW68_set_gpio(struct TW6864_dev *dev, int bit_no, int value); + +///void GPIOI2C(struct TW68_dev *dev, unsigned int GPIOaddr); +///unsigned char DeviceRead2864(struct TW68_dev *dev, unsigned long byte_addr); +///void DeviceWrite2864(struct TW68_dev *dev, unsigned long byte_addr, unsigned char value); + +void tw68v_set_framerate(struct TW68_dev *dev, u32 ch, u32 n); + +int videoDMA_pgtable_alloc(struct pci_dev *pci, struct TW68_pgtable *pt); +int AudioDMA_PB_alloc(struct pci_dev *pci, struct TW68_pgtable *pt); + +/// struct pci_dev *pci, TW68 +int _pgtable_build(struct TW68_pgtable *pt, + struct scatterlist *list, unsigned int length, + unsigned int startpage, unsigned int size); +void _pgtable_free(struct pci_dev *pci, struct TW68_pgtable *pt); + +int _buffer_count(unsigned int size, unsigned int count); +int _buffer_startpage(struct TW68_buf *buf); +unsigned long TW68_buffer_base(struct TW68_buf *buf); +int TW68_buffer_pages(int size); + + +int TW68_buffer_queue(struct TW68_dev *dev, struct TW68_dmaqueue *q, struct TW68_buf *buf); +void TW68_buffer_finish(struct TW68_dev *dev, struct TW68_dmaqueue *q, unsigned int state); +void TW68_buffer_next(struct TW68_dev *dev, struct TW68_dmaqueue *q); +int TW68_buffer_requeue(struct TW68_dev *dev, struct TW68_dmaqueue *q); + +void DecoderResize(struct TW68_dev *dev, int nId, int H, int W); +void Field_SG_Mapping(struct TW68_dev *dev, int field_PB); +void Fixed_SG_Mapping(struct TW68_dev *dev, int nDMA_channel, int Frame_size); // 0 1 +void BFDMA_setup(struct TW68_dev *dev, int nDMA_channel, int H, int W); + +int Field_Copy(struct TW68_dev *dev, int nDMA_channel, int field_PB); +int BF_Copy(struct TW68_dev *dev, int nDMA_channel, u32 Fn, u32 PB); +int QF_Field_Copy(struct TW68_dev *dev, int nDMA_channel, u32 Fn, u32 PB); + +void DMAstarter(unsigned long data); +void RestartDMA(unsigned long data); +void resync(unsigned long data); +void TW68_buffer_timeout(unsigned long data); +void TW68_dma_free(struct videobuf_queue *q,struct TW68_buf *buf); + +int TW68_set_dmabits(struct TW68_dev *dev, unsigned int DMA_nCH); +int stop_video_DMA(struct TW68_dev *dev, unsigned int DMA_nCH); +int Hardware_reset(struct TW68_dev *dev); +int VideoDecoderDetect(struct TW68_dev *dev, unsigned int DMA_nCH); + +extern int (*TW68_dmasound_init)(struct TW68_dev *dev); +extern int (*TW68_dmasound_exit)(struct TW68_dev *dev); + +u64 GetDelay(struct TW68_dev *dev, int no); + +/* ----------------------------------------------------------- */ +extern struct TW68_board TW68_boards[]; +extern const unsigned int TW68_bcount; +extern struct pci_device_id TW68_pci_tbl[]; + + + +/* ----------------------------------------------------------- */ +/* TW68-i2c.c */ + +int TW68_i2c_register(struct TW68_dev *dev); +int TW68_i2c_unregister(struct TW68_dev *dev); + + +/* ----------------------------------------------------------- */ +/* TW68-video.c */ + +extern struct video_device TW68_video_template; +//extern struct video_device TW68_radio_template; + + +/* ----------------------------------------------------------- */ +/* TW68-alsa.c */ +/* Audio */ +extern int TW68_alsa_create(struct TW68_dev *dev); +extern int TW68_alsa_free(struct TW68_dev *dev); +extern void TW68_alsa_irq(struct TW68_dev *dev, u32 dma_status, u32 pb_status); +//extern int TW68_alsa_resetdma(struct TW68_chip *chip, u32 dma_cmd); + +/* ----------------------------------------------------------- */ +/* TW68-audio.c */ +/* Audio */ +extern int TW68_audio_create(struct TW68_dev *dev); +extern int TW68_audio_free(struct TW68_dev *dev); +extern void TW68_audio_irq(struct TW68_dev *dev, u32 dma_status, u32 pb_status); +//extern int TW68_audio_param(struct TW68_dev *dev, struct TW68_aparam* ap); +//extern int TW68_audio_data(struct TW68_dev *dev, struct TW68_adata* ap); +//extern int TW68_audio_resetdma(struct TW68_chip *chip, u32 dma_cmd); +//extern int TW68_audio_trigger(struct TW68_dev *dev, int cmd); + + + +int TW68_s_ctrl_internal(struct TW68_dev *dev, struct TW68_fh *fh, struct v4l2_control *c); +int TW68_g_ctrl_internal(struct TW68_dev *dev, struct TW68_fh *fh, struct v4l2_control *c); +int TW68_queryctrl(struct file *file, void *priv, struct v4l2_queryctrl *c); +int TW68_s_std_internal(struct TW68_dev *dev, struct TW68_fh *fh, v4l2_std_id id); + +int TW68_videoport_init(struct TW68_dev *dev); +// void TW68_set_tvnorm_hw(struct TW68_dev *dev); + +int TW68_video_init1(struct TW68_dev *dev); +int TW68_video_init2(struct TW68_dev *dev); +void TW68_irq_video_signalchange(struct TW68_dev *dev); +void TW68_irq_video_done(struct TW68_dev *dev, unsigned int nId, u32 dwRegPB); + +int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size); +int buffer_setup_QF(struct videobuf_queue *q, unsigned int *count, unsigned int *size); + + +/* TW68-tvaudio.c */ + +int TW68_tvaudio_rx2mode(u32 rx); + +void TW68_tvaudio_setmute(struct TW68_dev *dev); +void TW68_tvaudio_setinput(struct TW68_dev *dev, struct TW68_input *in); +void TW68_tvaudio_setvolume(struct TW68_dev *dev, int level); +int TW68_tvaudio_getstereo(struct TW68_dev *dev); + +void TW68_tvaudio_init(struct TW68_dev *dev); +int TW68_tvaudio_init2(struct TW68_dev *dev); +int TW68_tvaudio_fini(struct TW68_dev *dev); +int TW68_tvaudio_do_scan(struct TW68_dev *dev); + +//void TW68_enable_i2s(struct TW68_dev *dev); + +/* ----------------------------------------------------------- */ + +extern const struct file_operations TW68_dsp_fops; +extern const struct file_operations TW68_mixer_fops; + +/* ----------------------------------------------------------- */ +/* TW68-input.c */ + +int TW68_input_init1(struct TW68_dev *dev); +void TW68_input_fini(struct TW68_dev *dev); +void TW68_input_irq(struct TW68_dev *dev); +void TW68_probe_i2c_ir(struct TW68_dev *dev); +void TW68_ir_start(struct TW68_dev *dev, struct card_ir *ir); +void TW68_ir_stop(struct TW68_dev *dev); + + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/drivers/media/pci/TW68/TW68_defines.h b/drivers/media/pci/TW68/TW68_defines.h new file mode 100644 index 000000000000..0fd53f071405 --- /dev/null +++ b/drivers/media/pci/TW68/TW68_defines.h @@ -0,0 +1,366 @@ +/****************************************************************/ +////TW68_defines.h +/****************************************************************/ + +#pragma once + +#define AUDIO_NCH 8 +#define AUDIO_DMA_PAGE 4096 +#define AUDIO_CH_PERIODS 4 +#define AUDIO_CH_BUF_SIZE AUDIO_DMA_PAGE * AUDIO_CH_PERIODS + +#define DMA_MODE_SG_RT 0 //Scatter Gather, Real-Time +#define DMA_MODE_SG_SWITCH 1 //Scatter Gather, Non-Real-Time +#define DMA_MODE_BLOCK 2 //Block Memory +#define DMA_MODE DMA_MODE_SG_RT + + +//#define DECIMATE_H +//#define DECIMATE_V +//#define VIDEO_MODE_PAL +//#define DRIVER_INTERLACE +//#define CUSTOM_VIDEO_SIZE (352 | (240<<16) | (1<<31)) //it overrides DECIMATE_H|DECIMATE_V +//#define CUSTOM_VIDEO_SIZE_F2 (704 | (120<<16)) //Available only for Rev.B or later +#define CUSTOM_VIDEO_SIZE (640 | (240<<16) | (1<<31)) //it overrides DECIMATE_H|DECIMATE_V + +////////////////////////////////////////////////// + + +#define MAX_SWITCH_VIDEO_PER_DMA 4 //has to be 2 or 4 +#define SWITCH_ON_FIELDS_NUM 2 //has to be 2, DO NOT CHANGE +#define SWITCH_TIMER_INTERVAL 20000L //2ms, UINT 100ns, DO NOT CHANGE, it will not be accurate if go smaller, around 156~158 Lines, +#define SWITCH_MAX_TIMER_INTERVAL 1 //2x1 -> 2ms + +#define AUDIO_DMA_LEN 4096 +#define AUDIO_GEN 1 //1=External,0=internal +#define AUDIO_GEN_PATTERN 0 //0=WAVE,1=SEQ DATA , 1-bit +#define AUDIO_GEN_MIX_SEL 0 //(0~7) + +#define VIDEO_GEN 0xFF //1=External,0=internal +#define VIDEO_GEN_PATTERNS 0x00 //0=ColorBar, 1=SEQ DATA , 8-bit +#define VIDEO_FORMAT_UYVY 0 //UYVY=Y422 +#define VIDEO_FORMAT_YUV420 1 +#define VIDEO_FORMAT_Y411 2 //Use VIDEO_FORMAT_IYU1 instead, LEAD does not accept this, even they are the same +#define VIDEO_FORMAT_Y41P 3 +#define VIDEO_FORMAT_RGB555 4 +#define VIDEO_FORMAT_RGB565 5 +#define VIDEO_FORMAT_YUYV 6 //YUYV=YUY2, only available for Rev.B or later +#define VIDEO_FORMAT_IYU1 0xA //same as VIDEO_FORMAT_Y411, m_nVideoFormat will be masked by 0x7 +#define VIDEO_FORMAT_UYVY_FRAME 0x8 //VideoInfoHeader2 +#define VIDEO_FORMAT VIDEO_FORMAT_UYVY + +#define AUDIO_DMA_LENGTH PAGE_SIZE //in bytes, should not > PAGE_SIZE(4096) +#define AUDIO_SAMPLE_RATE 8 //in KHz +#define AUDIO_SAMP_RATE_INT (125000/AUDIO_SAMPLE_RATE) +#define AUDIO_SAMP_RATE_EXT ((((ULONGLONG)125000)<<16)/AUDIO_SAMPLE_RATE) + +#define VIDEO_IN_1CH 0x0 +#define VIDEO_IN_2CH 0x1 +#define VIDEO_IN_4CH 0x2 +#define VIDEO_IN_MODE VIDEO_IN_4CH //defines incoming muxed-656 format + +////////////////////////////////////////////////// +//NO NOT CHANGE +//These 3 definitions are matched with hardware +#define MAX_NUM_SG_DMA 8 +#define MAX_NUM_DMA (MAX_NUM_SG_DMA + AUDIO_NCH) + + +////////////////////////////////////////////////// +//NO NOT CHANGE +// Register definitions +// IMPORTANT: These defines are DWORD-based. +// Part 1: DMA portion +#define DMA_INT_STATUS 0x00 //RO +#define DMA_PB_STATUS 0x01 //RO +#define DMA_CMD 0x02 +#define DMA_INT_ERROR 0x03 +#define DMA_FIFO_VLOSS 0x03 // B3 B2 B0 VLOSS +#define VIDEO_CHID 0x04 +#define VIDEO_PARSER_STATUS 0x05 +#define SYS_SOFT_RST 0x06 // 0x7 - 0XF + +#define DMA_PAGE_TABLE0_ADDR 0x08 //RW +#define DMA_PAGE_TABLE1_ADDR 0x09 +#define DMA_CHANNEL_ENABLE 0x0a +#define DMA_CONFIG 0x0b +#define DMA_INT_REF 0x0c +#define DMA_CHANNEL_TIMEOUT 0x0d + +#define DMA_CH0_CONFIG 0x10 //DMA_CH0_CONFIG ~ DMA_CH7_CONFIG are continusly +#define DMA_CH1_CONFIG 0x11 +#define DMA_CH2_CONFIG 0x12 +#define DMA_CH3_CONFIG 0x13 +#define DMA_CH4_CONFIG 0x14 +#define DMA_CH5_CONFIG 0x15 +#define DMA_CH6_CONFIG 0x16 +#define DMA_CH7_CONFIG 0x17 +#define DMA_CH8_CONFIG_P 0x18 // DMA_CH8_CONFIG_P ~ DMA_CH10_CONFIG_B are continusly +#define DMA_CH8_CONFIG_B 0x19 +#define DMA_CH9_CONFIG_P 0x1A +#define DMA_CH9_CONFIG_B 0x1B +#define DMA_CHA_CONFIG_P 0x1C +#define DMA_CHA_CONFIG_B 0x1D +#define DMA_CHB_CONFIG_P 0x1E +#define DMA_CHB_CONFIG_B 0x1F +#define DMA_CHC_CONFIG_P 0x20 +#define DMA_CHC_CONFIG_B 0x21 +#define DMA_CHD_CONFIG_P 0x22 +#define DMA_CHD_CONFIG_B 0x23 +#define DMA_CHE_CONFIG_P 0x24 +#define DMA_CHE_CONFIG_B 0x25 +#define DMA_CHF_CONFIG_P 0x26 +#define DMA_CHF_CONFIG_B 0x27 +#define DMA_CH10_CONFIG_P 0x28 +#define DMA_CH10_CONFIG_B 0x29 + +#define VIDEO_CTRL1 0x2A +#define VIDEO_CTRL2 0x2B +#define AUDIO_CTRL1 0x2C +#define AUDIO_CTRL2 0x2D +#define PHASE_REF_CONFIG 0x2E +#define GPIO_REG 0x2F + +#define INTL_HBAR0_CTRL 0x30 +#define INTL_HBAR1_CTRL 0x31 +#define INTL_HBAR2_CTRL 0x32 +#define INTL_HBAR3_CTRL 0x33 +#define INTL_HBAR4_CTRL 0x34 +#define INTL_HBAR5_CTRL 0x35 +#define INTL_HBAR6_CTRL 0x36 +#define INTL_HBAR7_CTRL 0x37 + +#define AUDIO_CTRL3 0x38 +#define DROP_FIELD_REG0 0x39 +#define DROP_FIELD_REG1 0x3A +#define DROP_FIELD_REG2 0x3B +#define DROP_FIELD_REG3 0x3C +#define DROP_FIELD_REG4 0x3D +#define DROP_FIELD_REG5 0x3E +#define DROP_FIELD_REG6 0x3F +#define DROP_FIELD_REG7 0x40 +#define VIDEO_SIZE_REG 0x41 //Rev.A only +#define SHSCALER_REG0 0x42 +#define SHSCALER_REG1 0x43 +#define SHSCALER_REG2 0x44 +#define SHSCALER_REG3 0x45 +#define SHSCALER_REG4 0x46 +#define SHSCALER_REG5 0x47 +#define SHSCALER_REG6 0x48 +#define SHSCALER_REG7 0x49 +#define VIDEO_SIZE_REG0 0x4A //Rev.B or later +#define VIDEO_SIZE_REG1 0x4B +#define VIDEO_SIZE_REG2 0x4C +#define VIDEO_SIZE_REG3 0x4D +#define VIDEO_SIZE_REG4 0x4E +#define VIDEO_SIZE_REG5 0x4F +#define VIDEO_SIZE_REG6 0x50 +#define VIDEO_SIZE_REG7 0x51 +#define VIDEO_SIZE_REG0_F2 0x52 //Rev.B or later +#define VIDEO_SIZE_REG1_F2 0x53 +#define VIDEO_SIZE_REG2_F2 0x54 +#define VIDEO_SIZE_REG3_F2 0x55 +#define VIDEO_SIZE_REG4_F2 0x56 +#define VIDEO_SIZE_REG5_F2 0x57 +#define VIDEO_SIZE_REG6_F2 0x58 +#define VIDEO_SIZE_REG7_F2 0x59 +#define VC_CTRL_REG0 0x70 +#define VC_CTRL_REG1 0x71 +#define VC_CTRL_REG2 0x72 +#define VC_CTRL_REG3 0x73 +#define VC_CTRL_REG4 0x74 +#define VC_CTRL_REG5 0x75 +#define VC_CTRL_REG6 0x76 +#define VC_CTRL_REG7 0x77 +#define BDMA_ADDR_P_0 0x80 //0x80 ~ 0xBF,Rev.B or later +#define BDMA_WHP_0 0x81 +#define BDMA_ADDR_B_0 0x82 +#define BDMA_ADDR_P_F2_0 0x84 +#define BDMA_WHP_F2_0 0x85 +#define BDMA_ADDR_B_F2_0 0x86 +#define PIN_CFG_CTRL 0xfb +#define CSR_REG 0xFD +#define EP_REG_ADDR 0xFE +#define EP_REG_DATA 0xFF + +//Part 2: Video Decoder portion - ch0 - ch3, ch4 - ch7 starts at 0x200 +#define DECODER0_STATUS 0x100 +#define DECODER1_STATUS 0x110 +#define DECODER2_STATUS 0x120 +#define DECODER3_STATUS 0x130 + +#define DECODER0_SDT 0x10E +#define DECODER1_SDT 0x11E +#define DECODER2_SDT 0x12E +#define DECODER3_SDT 0x13E + +#define DECODER0_SDTEN 0x10F +#define DECODER1_SDTEN 0x11F +#define DECODER2_SDTEN 0x12F +#define DECODER3_SDTEN 0x13F + + +#define CROP_H0 0x107 +#define CROP_H1 0x117 +#define CROP_H2 0x127 +#define CROP_H3 0x137 + +#define VDELAY0 0x108 +#define VDELAY1 0x118 +#define VDELAY2 0x128 +#define VDELAY3 0x138 + +#define VACTIVE_L0 0x109 +#define VACTIVE_L1 0x119 +#define VACTIVE_L2 0x129 +#define VACTIVE_L3 0x139 + +#define HDELAY0 0x10A +#define HDELAY1 0x11A +#define HDELAY2 0x12A +#define HDELAY3 0x13A + +#define HACTIVE_L0 0x10B +#define HACTIVE_L1 0x11B +#define HACTIVE_L2 0x12B +#define HACTIVE_L3 0x13B + + +#define VDELAY0_F2 0x148 +#define VDELAY1_F2 0x158 +#define VDELAY2_F2 0x168 +#define VDELAY3_F2 0x178 +#define HDELAY0_F2 0x14A +#define HDELAY1_F2 0x15A +#define HDELAY2_F2 0x16A +#define HDELAY3_F2 0x17A +#define VSCALE1_LO 0x144 +#define VHSCALE1_HI 0x145 +#define HSCALE1_LO 0x146 +#define VSCALE2_LO 0x154 +#define VHSCALE2_HI 0x155 +#define HSCALE2_LO 0x156 +#define VSCALE3_LO 0x164 +#define VHSCALE3_HI 0x165 +#define HSCALE3_LO 0x166 +#define VSCALE4_LO 0x174 +#define VHSCALE4_HI 0x175 +#define HSCALE4_LO 0x176 +#define VSCALE1_LO_F2 0x14C +#define VHSCALE1_HI_F2 0x14D +#define HSCALE1_LO_F2 0x14E +#define VSCALE2_LO_F2 0x15C +#define VHSCALE2_HI_F2 0x15D +#define HSCALE2_LO_F2 0x15E +#define VSCALE3_LO_F2 0x16C +#define VHSCALE3_HI_F2 0x16D +#define HSCALE3_LO_F2 0x16E +#define VSCALE4_LO_F2 0x17C +#define VHSCALE4_HI_F2 0x17D +#define HSCALE4_LO_F2 0x17E +#define F2_CNT0 0x14F +#define F2_CNT1 0x15F +#define F2_CNT2 0x16F +#define F2_CNT3 0x17F +#define AVSRST 0x180 +#define COLORKILL_HY 0x184 +#define VERTICAL_CTRL 0x18F +#define LOOP_CTRL 0x195 +#define MISC_CONTROL2 0x196 + +#define CH1_BRIGHTNESS_REG 0x101 +#define CH2_BRIGHTNESS_REG 0x111 +#define CH3_BRIGHTNESS_REG 0x121 +#define CH4_BRIGHTNESS_REG 0x131 +#define CH1_CONTRAST_REG 0x102 +#define CH2_CONTRAST_REG 0x112 +#define CH3_CONTRAST_REG 0x122 +#define CH4_CONTRAST_REG 0x132 +#define CH1_HUE_REG 0x106 +#define CH2_HUE_REG 0x116 +#define CH3_HUE_REG 0x126 +#define CH4_HUE_REG 0x136 +#define CH1_SAT_U_REG 0x104 +#define CH2_SAT_U_REG 0x114 +#define CH3_SAT_U_REG 0x124 +#define CH4_SAT_U_REG 0x134 +#define CH1_SAT_V_REG 0x105 +#define CH2_SAT_V_REG 0x115 +#define CH3_SAT_V_REG 0x125 +#define CH4_SAT_V_REG 0x135 +#define CH1_SHARPNESS_REG 0x103 +#define CH2_SHARPNESS_REG 0x113 +#define CH3_SHARPNESS_REG 0x123 +#define CH4_SHARPNESS_REG 0x133 + +#define POWER_DOWN_CTRL 0x1ce +#define AUDIO_GAIN_CH0 0x1d0 +#define AUDIO_DET_PERIOD 0x1e1 +#define AUDIO_DET_THRESHOLD1 0x1e2 +#define AUDIO_DET_THRESHOLD2 0x1e3 + +////////////////////////////////////////////////// +////////////////////////////////////////////////// +// Constantants definitions +#define DMA_STATUS_HOST_NOT_AVAIABLE 0 +#define DMA_STATUS_HOST_READY 1 +#define DMA_STATUS_HW_SUCCESS 2 +#define DMA_STATUS_HW_FAIL 3 + +////////////////////////////////////////////////////////////////////////////////// +// ******************************************************************************* +// Misc Definitions +#define ABS(x) ((x) < 0 ? (-(x)) : (x)) +#ifndef mmioFOURCC +#define mmioFOURCC( ch0, ch1, ch2, ch3 ) \ + ( (DWORD)(BYTE)(ch0) | ( (DWORD)(BYTE)(ch1) << 8 ) | \ + ( (DWORD)(BYTE)(ch2) << 16 ) | ( (DWORD)(BYTE)(ch3) << 24 ) ) +#endif +#define FOURCC_UYVY mmioFOURCC('U', 'Y', 'V', 'Y') //low -> high same as Y422 +#define FOURCC_YUYV mmioFOURCC('Y', 'U', 'Y', '2')// same as YUY2 +#define FOURCC_YUV420 mmioFOURCC('I', '4', '2', '0') +#define FOURCC_Y411 mmioFOURCC('Y', '4', '1', '1') +#define FOURCC_IYU1 mmioFOURCC('I', 'Y', 'U', '1') +#define FOURCC_Y41P mmioFOURCC('Y', '4', '1', 'P') +#define FOURCC_VCMP mmioFOURCC('V', 'C', 'M', 'P') +/* +// 30323449-0000-0010-8000-00AA00389B71 MEDIASUBTYPE_I420 +OUR_GUID_ENTRY(MEDIASUBTYPE_I420, +0x30323449, 0x0000, 0x0010, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71) +*/ + +#ifdef USE_COLORSPACE_OPTIONS +#define VIDEO_CAPTURE_PIN_DATA_RANGE_COUNT 6 //3*2 // The number of ranges supported on the video capture pin. +#else +#define VIDEO_CAPTURE_PIN_DATA_RANGE_COUNT 1 // The number of ranges supported on the video capture pin. +#endif + +#define AUDIO_CAPTURE_PIN_DATA_RANGE_COUNT 1 // The number of ranges supported on the audio capture pin. +#define CAPTURE_FILTER_CATEGORIES_COUNT 3 // The number of categories for the capture filter. + +#ifdef DROP_FIELD +#define NTSC_FRAME_TIME 667334 //unit 100ns, Dropped case +#define NTSC_FRAME_RATE 15 +#endif + +#ifdef DROP_FIELD_REG +#define NTSC_FRAME_TIME 667334 //unit 100ns, Dropped case +#define NTSC_FRAME_RATE 15 +#endif + +#ifndef NTSC_FRAME_TIME +#define NTSC_FRAME_TIME 333667 //unit 100ns,Normal case +#endif + +#ifndef NTSC_FRAME_RATE +#define NTSC_FRAME_RATE 30 //unit frames +#endif + +#define NTSC_FIELD_TIME (NTSC_FRAME_TIME>>1) +#define NTSC_FIELD_RATE (NTSC_FRAME_RATE<<1) +//#define NTSC_FIELD_TIME NTSC_FRAME_TIME +//#define NTSC_FIELD_RATE NTSC_FRAME_RATE + +#define MAX_FRAME_TIME NTSC_FIELD_TIME + + diff --git a/drivers/media/platform/mxc/capture/Kconfig b/drivers/media/platform/mxc/capture/Kconfig index cee7aa31f2d1..21b55b77d094 100644 --- a/drivers/media/platform/mxc/capture/Kconfig +++ b/drivers/media/platform/mxc/capture/Kconfig @@ -30,6 +30,14 @@ config MXC_CAMERA_OV5640_MIPI ---help--- If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here. +config MXC_HDMI_CSI2_TC358743 + tristate "Toshiba tc358743 Hdmi to CSI 2 bridge" + depends on !VIDEO_MXC_EMMA_CAMERA && I2C + select MXC_MIPI_CSI2 if ARCH_MX6Q + select MXC_CAMERA_SENSOR_CLK + ---help--- + Toshina HDMI to MIPI-CSI2 bridge + config MXC_TVIN_ADV7180 tristate "Analog Device adv7180 TV Decoder Input support" depends on !VIDEO_MXC_EMMA_CAMERA && I2C diff --git a/drivers/media/platform/mxc/capture/Makefile b/drivers/media/platform/mxc/capture/Makefile index 4303c0a2ccdf..856035777bfd 100644 --- a/drivers/media/platform/mxc/capture/Makefile +++ b/drivers/media/platform/mxc/capture/Makefile @@ -17,5 +17,8 @@ obj-$(CONFIG_MXC_CAMERA_OV5642) += ov5642_camera.o ov5640_camera_mipi-objs := ov5640_mipi.o obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi.o +tc358743_h2c_bridge-objs := tc358743_h2c.o +obj-$(CONFIG_MXC_HDMI_CSI2_TC358743) += tc358743_h2c_bridge.o + adv7180_tvin-objs := adv7180.o obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o diff --git a/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c b/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c index 4a975b54a977..7b4e3d33ae8c 100644 --- a/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c +++ b/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c @@ -129,11 +129,6 @@ static int csi_enc_setup(cam_data *cam) ipu_channel_params_t params; u32 pixel_fmt; int err = 0, sensor_protocol = 0; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif if (!cam) { printk(KERN_ERR "cam private is NULL\n"); @@ -161,36 +156,9 @@ static int csi_enc_setup(cam_data *cam) printk(KERN_ERR "sensor protocol unsupported\n"); return -EINVAL; } - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) { - params.csi_mem.mipi_en = true; - params.csi_mem.mipi_vc = - mipi_csi2_get_virtual_channel(mipi_csi2_info); - params.csi_mem.mipi_id = - mipi_csi2_get_datatype(mipi_csi2_info); - - mipi_csi2_pixelclk_enable(mipi_csi2_info); - } else { - params.csi_mem.mipi_en = false; - params.csi_mem.mipi_vc = 0; - params.csi_mem.mipi_id = 0; - } - } else { - params.csi_mem.mipi_en = false; - params.csi_mem.mipi_vc = 0; - params.csi_mem.mipi_id = 0; - } - } -#endif + err = cam_mipi_csi2_enable(cam, ¶ms.csi_mem.mipi); + if (err) + return err; if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -230,9 +198,9 @@ static int csi_enc_setup(cam_data *cam) } pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); - err = ipu_init_channel(cam->ipu, CSI_MEM, ¶ms); - if (err != 0) { - printk(KERN_ERR "ipu_init_channel %d\n", err); + err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); goto out_1; } @@ -379,37 +347,19 @@ static int bg_overlay_start(void *private) static int bg_overlay_stop(void *private) { int err = 0; + int err2 = 0; cam_data *cam = (cam_data *) private; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif if (cam->overlay_active == false) return 0; - err = ipu_disable_channel(cam->ipu, CSI_MEM, true); + err = ipu_channel_disable(cam->ipu_chan, true); - ipu_uninit_channel(cam->ipu, CSI_MEM); + ipu_channel_free(&cam->ipu_chan); csi_buffer_num = 0; -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) - mipi_csi2_pixelclk_disable(mipi_csi2_info); - } - } -#endif - + err2 = cam_mipi_csi2_disable(cam); flush_work(&cam->csi_work_struct); cancel_work_sync(&cam->csi_work_struct); @@ -441,7 +391,7 @@ static int bg_overlay_stop(void *private) } cam->overlay_active = false; - return err; + return err ? err : err2; } /*! @@ -452,9 +402,7 @@ static int bg_overlay_stop(void *private) */ static int bg_overlay_enable_csi(void *private) { - cam_data *cam = (cam_data *) private; - - return ipu_enable_csi(cam->ipu, cam->csi); + return cam_ipu_enable_csi((cam_data *)private); } /*! @@ -471,8 +419,7 @@ static int bg_overlay_disable_csi(void *private) * when disable csi, wait for idmac eof. * it requests eof irq again */ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); - - return ipu_disable_csi(cam->ipu, cam->csi); + return cam_ipu_disable_csi(cam); } /*! diff --git a/drivers/media/platform/mxc/capture/ipu_csi_enc.c b/drivers/media/platform/mxc/capture/ipu_csi_enc.c index fb3c6a24322a..eb18af86aec1 100644 --- a/drivers/media/platform/mxc/capture/ipu_csi_enc.c +++ b/drivers/media/platform/mxc/capture/ipu_csi_enc.c @@ -69,11 +69,6 @@ static int csi_enc_setup(cam_data *cam) u32 pixel_fmt; int err = 0, sensor_protocol = 0; dma_addr_t dummy = cam->dummy_frame.buffer.m.offset; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif CAMERA_TRACE("In csi_enc_setup\n"); if (!cam) { @@ -129,40 +124,13 @@ static int csi_enc_setup(cam_data *cam) printk(KERN_ERR "format not supported\n"); return -EINVAL; } + err = cam_mipi_csi2_enable(cam, ¶ms.csi_mem.mipi); + if (err) + return err; -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) { - params.csi_mem.mipi_en = true; - params.csi_mem.mipi_vc = - mipi_csi2_get_virtual_channel(mipi_csi2_info); - params.csi_mem.mipi_id = - mipi_csi2_get_datatype(mipi_csi2_info); - - mipi_csi2_pixelclk_enable(mipi_csi2_info); - } else { - params.csi_mem.mipi_en = false; - params.csi_mem.mipi_vc = 0; - params.csi_mem.mipi_id = 0; - } - } else { - params.csi_mem.mipi_en = false; - params.csi_mem.mipi_vc = 0; - params.csi_mem.mipi_id = 0; - } - } -#endif - - err = ipu_init_channel(cam->ipu, CSI_MEM, ¶ms); - if (err != 0) { - printk(KERN_ERR "ipu_init_channel %d\n", err); + err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); return err; } @@ -253,7 +221,7 @@ static int csi_enc_enabling_tasks(void *private) err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, csi_enc_callback, 0, "Mxc Camera", cam); if (err != 0) { - printk(KERN_ERR "Error registering rot irq\n"); + pr_err("%s: Error requesting IPU_IRQ_CSI0_OUT_EOF\n", __func__); return err; } @@ -276,15 +244,11 @@ static int csi_enc_disabling_tasks(void *private) { cam_data *cam = (cam_data *) private; int err = 0; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif + int err2 = 0; - err = ipu_disable_channel(cam->ipu, CSI_MEM, true); + err = ipu_channel_disable(cam->ipu_chan, true); - ipu_uninit_channel(cam->ipu, CSI_MEM); + ipu_channel_free(&cam->ipu_chan); if (cam->dummy_frame.vaddress != 0) { dma_free_coherent(0, cam->dummy_frame.buffer.length, @@ -292,23 +256,8 @@ static int csi_enc_disabling_tasks(void *private) cam->dummy_frame.paddress); cam->dummy_frame.vaddress = 0; } - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) - mipi_csi2_pixelclk_disable(mipi_csi2_info); - } - } -#endif - - return err; + err2 = cam_mipi_csi2_disable(cam); + return err ? err : err2; } /*! @@ -319,9 +268,7 @@ static int csi_enc_disabling_tasks(void *private) */ static int csi_enc_enable_csi(void *private) { - cam_data *cam = (cam_data *) private; - - return ipu_enable_csi(cam->ipu, cam->csi); + return cam_ipu_enable_csi((cam_data *)private); } /*! @@ -338,8 +285,7 @@ static int csi_enc_disable_csi(void *private) * when disable csi, wait for idmac eof. * it requests eof irq again */ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); - - return ipu_disable_csi(cam->ipu, cam->csi); + return cam_ipu_disable_csi(cam); } /*! diff --git a/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c b/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c index 80136156ceaf..54e59be281d4 100644 --- a/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c +++ b/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c @@ -134,11 +134,6 @@ static int csi_enc_setup(cam_data *cam) { ipu_channel_params_t params; int err = 0, sensor_protocol = 0; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif CAMERA_TRACE("In csi_enc_setup\n"); if (!cam) { @@ -167,36 +162,9 @@ static int csi_enc_setup(cam_data *cam) printk(KERN_ERR "sensor protocol unsupported\n"); return -EINVAL; } - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) { - params.csi_mem.mipi_en = true; - params.csi_mem.mipi_vc = - mipi_csi2_get_virtual_channel(mipi_csi2_info); - params.csi_mem.mipi_id = - mipi_csi2_get_datatype(mipi_csi2_info); - - mipi_csi2_pixelclk_enable(mipi_csi2_info); - } else { - params.csi_mem.mipi_en = false; - params.csi_mem.mipi_vc = 0; - params.csi_mem.mipi_id = 0; - } - } else { - params.csi_mem.mipi_en = false; - params.csi_mem.mipi_vc = 0; - params.csi_mem.mipi_id = 0; - } - } -#endif + err = cam_mipi_csi2_enable(cam, ¶ms.csi_mem.mipi); + if (err) + return err; if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -236,9 +204,9 @@ static int csi_enc_setup(cam_data *cam) } pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); - err = ipu_init_channel(cam->ipu, CSI_MEM, ¶ms); - if (err != 0) { - printk(KERN_ERR "ipu_init_channel %d\n", err); + err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); goto out_1; } @@ -448,21 +416,16 @@ static int foreground_stop(void *private) { cam_data *cam = (cam_data *) private; int err = 0, i = 0; + int err2 = 0; struct fb_info *fbi = NULL; struct fb_var_screeninfo fbvar; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif - if (cam->overlay_active == false) return 0; - err = ipu_disable_channel(cam->ipu, CSI_MEM, true); + err = ipu_channel_disable(cam->ipu_chan, true); - ipu_uninit_channel(cam->ipu, CSI_MEM); + ipu_channel_free(&cam->ipu_chan); csi_buffer_num = 0; buffer_num = 0; @@ -491,21 +454,7 @@ static int foreground_stop(void *private) fbvar.nonstd = cam->fb_origin_std; fbvar.activate |= FB_ACTIVATE_FORCE; fb_set_var(fbi, &fbvar); - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) - mipi_csi2_pixelclk_disable(mipi_csi2_info); - } - } -#endif + err2 = cam_mipi_csi2_disable(cam); flush_work(&cam->csi_work_struct); cancel_work_sync(&cam->csi_work_struct); @@ -526,7 +475,7 @@ static int foreground_stop(void *private) } cam->overlay_active = false; - return err; + return err ? err : err2; } /*! @@ -537,9 +486,7 @@ static int foreground_stop(void *private) */ static int foreground_enable_csi(void *private) { - cam_data *cam = (cam_data *) private; - - return ipu_enable_csi(cam->ipu, cam->csi); + return cam_ipu_enable_csi((cam_data *)private); } /*! @@ -556,8 +503,7 @@ static int foreground_disable_csi(void *private) * when disable csi, wait for idmac eof. * it requests eof irq again */ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); - - return ipu_disable_csi(cam->ipu, cam->csi); + return cam_ipu_disable_csi(cam); } /*! diff --git a/drivers/media/platform/mxc/capture/ipu_prp_enc.c b/drivers/media/platform/mxc/capture/ipu_prp_enc.c index af419e356e6d..18fe28cc7ae9 100644 --- a/drivers/media/platform/mxc/capture/ipu_prp_enc.c +++ b/drivers/media/platform/mxc/capture/ipu_prp_enc.c @@ -71,11 +71,6 @@ static int prp_enc_setup(cam_data *cam) ipu_channel_params_t enc; int err = 0; dma_addr_t dummy = cam->dummy_frame.buffer.m.offset; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif CAMERA_TRACE("In prp_enc_setup\n"); if (!cam) { @@ -133,40 +128,13 @@ static int prp_enc_setup(cam_data *cam) printk(KERN_ERR "format not supported\n"); return -EINVAL; } + err = cam_mipi_csi2_enable(cam, &enc.csi_prp_enc_mem.mipi); + if (err) + return err; -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) { - enc.csi_prp_enc_mem.mipi_en = true; - enc.csi_prp_enc_mem.mipi_vc = - mipi_csi2_get_virtual_channel(mipi_csi2_info); - enc.csi_prp_enc_mem.mipi_id = - mipi_csi2_get_datatype(mipi_csi2_info); - - mipi_csi2_pixelclk_enable(mipi_csi2_info); - } else { - enc.csi_prp_enc_mem.mipi_en = false; - enc.csi_prp_enc_mem.mipi_vc = 0; - enc.csi_prp_enc_mem.mipi_id = 0; - } - } else { - enc.csi_prp_enc_mem.mipi_en = false; - enc.csi_prp_enc_mem.mipi_vc = 0; - enc.csi_prp_enc_mem.mipi_id = 0; - } - } -#endif - - err = ipu_init_channel(cam->ipu, CSI_PRP_ENC_MEM, &enc); - if (err != 0) { - printk(KERN_ERR "ipu_init_channel %d\n", err); + err = ipu_channel_request(cam->ipu, CSI_PRP_ENC_MEM, &enc, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); return err; } @@ -222,9 +190,9 @@ static int prp_enc_setup(cam_data *cam) return err; } - err = ipu_init_channel(cam->ipu, MEM_ROT_ENC_MEM, NULL); - if (err != 0) { - printk(KERN_ERR "MEM_ROT_ENC_MEM channel err\n"); + err = ipu_channel_request(cam->ipu, MEM_ROT_ENC_MEM, NULL, &cam->ipu_chan_rot); + if (err) { + pr_err("%s:ipu_channel_request %d for rot\n", __func__, err); return err; } @@ -382,6 +350,7 @@ static int prp_enc_enabling_tasks(void *private) { cam_data *cam = (cam_data *) private; int err = 0; + int irq; CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n"); cam->dummy_frame.vaddress = dma_alloc_coherent(0, @@ -398,15 +367,12 @@ static int prp_enc_enabling_tasks(void *private) PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; - if (cam->rotation >= IPU_ROTATE_90_RIGHT) { - err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF, - prp_enc_callback, 0, "Mxc Camera", cam); - } else { - err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF, - prp_enc_callback, 0, "Mxc Camera", cam); - } - if (err != 0) { - printk(KERN_ERR "Error registering rot irq\n"); + irq = (cam->rotation >= IPU_ROTATE_90_RIGHT) ? + IPU_IRQ_PRP_ENC_ROT_OUT_EOF : IPU_IRQ_PRP_ENC_OUT_EOF; + err = ipu_request_irq(cam->ipu, irq, + prp_enc_callback, 0, "Mxc Camera", cam); + if (err) { + pr_err("%s: Error requesting irq=%d\n", __func__, irq); return err; } @@ -429,24 +395,19 @@ static int prp_enc_disabling_tasks(void *private) { cam_data *cam = (cam_data *) private; int err = 0; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif + int err2 = 0; + int err3 = 0; if (cam->rotation >= IPU_ROTATE_90_RIGHT) { ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam); ipu_unlink_channels(cam->ipu, CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); } - err = ipu_disable_channel(cam->ipu, CSI_PRP_ENC_MEM, true); - if (cam->rotation >= IPU_ROTATE_90_RIGHT) - err |= ipu_disable_channel(cam->ipu, MEM_ROT_ENC_MEM, true); + err = ipu_channel_disable(cam->ipu_chan, true); + err2 = ipu_channel_disable(cam->ipu_chan_rot, true); - ipu_uninit_channel(cam->ipu, CSI_PRP_ENC_MEM); - if (cam->rotation >= IPU_ROTATE_90_RIGHT) - ipu_uninit_channel(cam->ipu, MEM_ROT_ENC_MEM); + ipu_channel_free(&cam->ipu_chan); + ipu_channel_free(&cam->ipu_chan_rot); if (cam->dummy_frame.vaddress != 0) { dma_free_coherent(0, cam->dummy_frame.buffer.length, @@ -454,23 +415,8 @@ static int prp_enc_disabling_tasks(void *private) cam->dummy_frame.paddress); cam->dummy_frame.vaddress = 0; } - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) - mipi_csi2_pixelclk_disable(mipi_csi2_info); - } - } -#endif - - return err; + err3 = cam_mipi_csi2_disable(cam); + return err ? err : (err2 ? err2 : err3); } /*! @@ -481,9 +427,7 @@ static int prp_enc_disabling_tasks(void *private) */ static int prp_enc_enable_csi(void *private) { - cam_data *cam = (cam_data *) private; - - return ipu_enable_csi(cam->ipu, cam->csi); + return cam_ipu_enable_csi((cam_data *)private); } /*! @@ -501,8 +445,7 @@ static int prp_enc_disable_csi(void *private) * it requests eof irq again */ if (cam->rotation < IPU_ROTATE_90_RIGHT) ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF, cam); - - return ipu_disable_csi(cam->ipu, cam->csi); + return cam_ipu_disable_csi(cam); } /*! diff --git a/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c b/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c index b9610f1ed820..e2d837a30684 100644 --- a/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c +++ b/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c @@ -78,11 +78,6 @@ static int prpvf_start(void *private) u32 size = 2, temp = 0; int err = 0, i = 0; short *tmp, color; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif if (!cam) { printk(KERN_ERR "private is NULL\n"); @@ -169,39 +164,15 @@ static int prpvf_start(void *private) vf.csi_prp_vf_mem.out_pixel_fmt = vf_out_format; size = cam->win.w.width * cam->win.w.height * size; -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) { - vf.csi_prp_vf_mem.mipi_en = true; - vf.csi_prp_vf_mem.mipi_vc = - mipi_csi2_get_virtual_channel(mipi_csi2_info); - vf.csi_prp_vf_mem.mipi_id = - mipi_csi2_get_datatype(mipi_csi2_info); - - mipi_csi2_pixelclk_enable(mipi_csi2_info); - } else { - vf.csi_prp_vf_mem.mipi_en = false; - vf.csi_prp_vf_mem.mipi_vc = 0; - vf.csi_prp_vf_mem.mipi_id = 0; - } - } else { - vf.csi_prp_vf_mem.mipi_en = false; - vf.csi_prp_vf_mem.mipi_vc = 0; - vf.csi_prp_vf_mem.mipi_id = 0; - } - } -#endif + err = cam_mipi_csi2_enable(cam, &vf.csi_prp_vf_mem.mipi); + if (err) + return err; - err = ipu_init_channel(cam->ipu, CSI_PRP_VF_MEM, &vf); - if (err != 0) + err = ipu_channel_request(cam->ipu, CSI_PRP_VF_MEM, &vf, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); goto out_5; + } if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -252,9 +223,9 @@ static int prpvf_start(void *private) if (err != 0) goto out_3; - err = ipu_init_channel(cam->ipu, MEM_ROT_VF_MEM, NULL); - if (err != 0) { - printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n"); + err = ipu_channel_request(cam->ipu, MEM_ROT_VF_MEM, NULL, &cam->ipu_chan_rot); + if (err) { + pr_err("%s:ipu_channel_request %d for rot\n", __func__, err); goto out_3; } @@ -359,8 +330,7 @@ static int prpvf_start(void *private) out_1: ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL); out_2: - if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) - ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM); + ipu_channel_free(&cam->ipu_chan_rot); out_3: if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -377,7 +347,7 @@ out_3: cam->vf_bufs[1] = 0; } out_4: - ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM); + ipu_channel_free(&cam->ipu_chan); out_5: return err; } @@ -394,11 +364,6 @@ static int prpvf_stop(void *private) int err = 0, i = 0; struct fb_info *fbi = NULL; struct fb_var_screeninfo fbvar; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif if (cam->overlay_active == false) return 0; @@ -423,13 +388,10 @@ static int prpvf_stop(void *private) } buffer_num = 0; - ipu_disable_channel(cam->ipu, CSI_PRP_VF_MEM, true); - - if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { - ipu_disable_channel(cam->ipu, MEM_ROT_VF_MEM, true); - ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM); - } - ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM); + ipu_channel_disable(cam->ipu_chan, true); + ipu_channel_disable(cam->ipu_chan_rot, true); + ipu_channel_free(&cam->ipu_chan_rot); + ipu_channel_free(&cam->ipu_chan); console_lock(); fb_blank(fbi, FB_BLANK_POWERDOWN); @@ -441,21 +403,7 @@ static int prpvf_stop(void *private) fbvar.nonstd = cam->fb_origin_std; fbvar.activate |= FB_ACTIVATE_FORCE; fb_set_var(fbi, &fbvar); - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) - mipi_csi2_pixelclk_disable(mipi_csi2_info); - } - } -#endif + err2 = cam_mipi_csi2_disable(cam); if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -473,7 +421,7 @@ static int prpvf_stop(void *private) } cam->overlay_active = false; - return err; + return err ? err : err2; } /*! @@ -484,9 +432,7 @@ static int prpvf_stop(void *private) */ static int prp_vf_enable_csi(void *private) { - cam_data *cam = (cam_data *) private; - - return ipu_enable_csi(cam->ipu, cam->csi); + return cam_ipu_enable_csi((cam_data *)private); } /*! @@ -504,8 +450,7 @@ static int prp_vf_disable_csi(void *private) * it requests eof irq again */ if (cam->vf_rotation < IPU_ROTATE_VERT_FLIP) ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam); - - return ipu_disable_csi(cam->ipu, cam->csi); + return cam_ipu_disable_csi(cam); } /*! diff --git a/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c b/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c index a24d82dfca63..ff9d55262342 100644 --- a/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c +++ b/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c @@ -98,11 +98,6 @@ static int prpvf_start(void *private) u32 offset; u32 bpp, size = 3; int err = 0; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif if (!cam) { printk(KERN_ERR "private is NULL\n"); @@ -154,39 +149,15 @@ static int prpvf_start(void *private) vf.csi_prp_vf_mem.out_pixel_fmt = format; size = cam->win.w.width * cam->win.w.height * size; -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); - - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) { - vf.csi_prp_vf_mem.mipi_en = true; - vf.csi_prp_vf_mem.mipi_vc = - mipi_csi2_get_virtual_channel(mipi_csi2_info); - vf.csi_prp_vf_mem.mipi_id = - mipi_csi2_get_datatype(mipi_csi2_info); - - mipi_csi2_pixelclk_enable(mipi_csi2_info); - } else { - vf.csi_prp_vf_mem.mipi_en = false; - vf.csi_prp_vf_mem.mipi_vc = 0; - vf.csi_prp_vf_mem.mipi_id = 0; - } - } else { - vf.csi_prp_vf_mem.mipi_en = false; - vf.csi_prp_vf_mem.mipi_vc = 0; - vf.csi_prp_vf_mem.mipi_id = 0; - } - } -#endif + err = cam_mipi_csi2_enable(cam, &vf.csi_prp_vf_mem.mipi); + if (err) + return err; - err = ipu_init_channel(cam->ipu, CSI_PRP_VF_MEM, &vf); - if (err != 0) + err = ipu_channel_request(cam->ipu, CSI_PRP_VF_MEM, &vf, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); goto out_4; + } if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -232,9 +203,9 @@ static int prpvf_start(void *private) printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); goto out_3; } - err = ipu_init_channel(cam->ipu, MEM_ROT_VF_MEM, NULL); - if (err != 0) { - printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n"); + err = ipu_channel_request(cam->ipu, MEM_ROT_VF_MEM, NULL, &cam->ipu_chan_rot); + if (err) { + pr_err("%s:ipu_channel_request %d for rot\n", __func__, err); goto out_3; } @@ -313,9 +284,9 @@ static int prpvf_start(void *private) out_1: ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL); out_2: - ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM); + ipu_channel_free(&cam->ipu_chan_rot); out_3: - ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM); + ipu_channel_free(&cam->ipu_chan); out_4: if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -354,37 +325,20 @@ out_4: */ static int prpvf_stop(void *private) { + int err = 0; cam_data *cam = (cam_data *) private; -#ifdef CONFIG_MXC_MIPI_CSI2 - void *mipi_csi2_info; - int ipu_id; - int csi_id; -#endif if (cam->overlay_active == false) return 0; ipu_free_irq(disp_ipu, IPU_IRQ_BG_SF_END, cam); - ipu_disable_channel(cam->ipu, CSI_PRP_VF_MEM, true); - ipu_disable_channel(cam->ipu, MEM_ROT_VF_MEM, true); - ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM); - ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM); - -#ifdef CONFIG_MXC_MIPI_CSI2 - mipi_csi2_info = mipi_csi2_get_info(); - - if (mipi_csi2_info) { - if (mipi_csi2_get_status(mipi_csi2_info)) { - ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); - csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); + ipu_channel_disable(cam->ipu_chan, true); + ipu_channel_disable(cam->ipu_chan_rot, true); + ipu_channel_free(&cam->ipu_chan); + ipu_channel_free(&cam->ipu_chan_rot); - if (cam->ipu == ipu_get_soc(ipu_id) - && cam->csi == csi_id) - mipi_csi2_pixelclk_disable(mipi_csi2_info); - } - } -#endif + err = cam_mipi_csi2_disable(cam); if (cam->vf_bufs_vaddr[0]) { dma_free_coherent(0, cam->vf_bufs_size[0], @@ -416,7 +370,7 @@ static int prpvf_stop(void *private) buffer_num = 0; buffer_ready = 0; cam->overlay_active = false; - return 0; + return err; } /*! @@ -427,9 +381,7 @@ static int prpvf_stop(void *private) */ static int prp_vf_enable_csi(void *private) { - cam_data *cam = (cam_data *) private; - - return ipu_enable_csi(cam->ipu, cam->csi); + return cam_ipu_enable_csi((cam_data *)private); } /*! @@ -446,8 +398,7 @@ static int prp_vf_disable_csi(void *private) * when disable csi, wait for idmac eof. * it requests eof irq again */ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam); - - return ipu_disable_csi(cam->ipu, cam->csi); + return cam_ipu_disable_csi(cam); } /*! diff --git a/drivers/media/platform/mxc/capture/ipu_still.c b/drivers/media/platform/mxc/capture/ipu_still.c index b295a1850301..fd3e2210fb3a 100644 --- a/drivers/media/platform/mxc/capture/ipu_still.c +++ b/drivers/media/platform/mxc/capture/ipu_still.c @@ -123,9 +123,11 @@ static int prp_still_start(void *private) } memset(¶ms, 0, sizeof(params)); - err = ipu_init_channel(cam->ipu, CSI_MEM, ¶ms); - if (err != 0) + err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); + if (err) { + pr_err("%s:ipu_channel_request %d\n", __func__, err); return err; + } err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, pixel_fmt, cam->v2f.fmt.pix.width, @@ -168,7 +170,7 @@ static int prp_still_start(void *private) ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0); ipu_enable_channel(cam->ipu, CSI_MEM); - ipu_enable_csi(cam->ipu, cam->csi); + cam_ipu_enable_csi(cam); #endif return err; @@ -192,10 +194,9 @@ static int prp_still_stop(void *private) ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); #endif - ipu_disable_csi(cam->ipu, cam->csi); - ipu_disable_channel(cam->ipu, CSI_MEM, true); - ipu_uninit_channel(cam->ipu, CSI_MEM); - + cam_ipu_disable_csi(cam); + ipu_channel_disable(cam->ipu_chan, true); + ipu_channel_free(&cam->ipu_chan); return err; } diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c index 84b6e4e857ef..6e8683ac7142 100755..100644 --- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c +++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c @@ -34,6 +34,7 @@ #include <linux/fb.h> #include <linux/dma-mapping.h> #include <linux/delay.h> +#include <linux/mutex.h> #include <linux/mxcfb.h> #include <linux/of_device.h> #include <media/v4l2-chip-ident.h> @@ -239,7 +240,7 @@ static int mxc_free_frame_buf(cam_data *cam) { int i; - pr_debug("MVC: In mxc_free_frame_buf\n"); + pr_debug("%s\n", __func__); for (i = 0; i < FRAME_NUM; i++) { if (cam->frame[i].vaddress != 0) { @@ -265,8 +266,7 @@ static int mxc_allocate_frame_buf(cam_data *cam, int count) { int i; - pr_debug("In MVC:mxc_allocate_frame_buf - size=%d\n", - cam->v2f.fmt.pix.sizeimage); + pr_debug("%s: size=%d\n", __func__, cam->v2f.fmt.pix.sizeimage); for (i = 0; i < count; i++) { cam->frame[i].vaddress = @@ -275,8 +275,7 @@ static int mxc_allocate_frame_buf(cam_data *cam, int count) &cam->frame[i].paddress, GFP_DMA | GFP_KERNEL); if (cam->frame[i].vaddress == 0) { - pr_err("ERROR: v4l2 capture: " - "mxc_allocate_frame_buf failed.\n"); + pr_err("%s: failed.\n", __func__); mxc_free_frame_buf(cam); return -ENOBUFS; } @@ -304,7 +303,7 @@ static void mxc_free_frames(cam_data *cam) { int i; - pr_debug("In MVC:mxc_free_frames\n"); + pr_debug("%s\n", __func__); for (i = 0; i < FRAME_NUM; i++) cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; @@ -325,7 +324,7 @@ static void mxc_free_frames(cam_data *cam) */ static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) { - pr_debug("In MVC:mxc_v4l2_buffer_status\n"); + pr_debug("%s\n", __func__); if (buf->index < 0 || buf->index >= FRAME_NUM) { pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers " @@ -339,13 +338,13 @@ static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) static int mxc_v4l2_release_bufs(cam_data *cam) { - pr_debug("In MVC:mxc_v4l2_release_bufs\n"); + pr_debug("%s\n", __func__); return 0; } static int mxc_v4l2_prepare_bufs(cam_data *cam, struct v4l2_buffer *buf) { - pr_debug("In MVC:mxc_v4l2_prepare_bufs\n"); + pr_debug("%s\n", __func__); if (buf->index < 0 || buf->index >= FRAME_NUM || buf->length < PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage)) { @@ -406,7 +405,7 @@ static int mxc_streamon(cam_data *cam) unsigned long lock_flags; int err = 0; - pr_debug("In MVC:mxc_streamon\n"); + pr_debug("%s\n", __func__); if (NULL == cam) { pr_err("ERROR! cam parameter is NULL\n"); @@ -492,11 +491,11 @@ static int mxc_streamoff(cam_data *cam) { int err = 0; - pr_debug("In MVC:mxc_streamoff\n"); - + pr_debug("%s: ipu%d/csi%d capture_on=%d %s\n", __func__, cam->ipu_id, + cam->csi, cam->capture_on, + mxc_capture_inputs[cam->current_input].name); if (cam->capture_on == false) return 0; - /* For both CSI--MEM and CSI--IC--MEM * 1. wait for idmac eof * 2. disable csi first @@ -539,7 +538,7 @@ static int verify_preview(cam_data *cam, struct v4l2_window *win) bool foregound_fb = false; mm_segment_t old_fs; - pr_debug("In MVC: verify_preview\n"); + pr_debug("%s\n", __func__); do { fbi = (struct fb_info *)registered_fb[i]; @@ -767,7 +766,7 @@ static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) { int retval = 0; - pr_debug("In MVC: mxc_v4l2_g_fmt type=%d\n", f->type); + pr_debug("%s: type=%d\n", __func__, f->type); switch (f->type) { case V4L2_BUF_TYPE_VIDEO_CAPTURE: @@ -815,7 +814,7 @@ static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f) int bytesperline = 0; int *width, *height; - pr_debug("In MVC: mxc_v4l2_s_fmt\n"); + pr_debug("%s\n", __func__); switch (f->type) { case V4L2_BUF_TYPE_VIDEO_CAPTURE: @@ -978,7 +977,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) { int status = 0; - pr_debug("In MVC:mxc_v4l2_g_ctrl\n"); + pr_debug("%s\n", __func__); /* probably don't need to store the values that can be retrieved, * locally, but they are for now. */ @@ -1074,6 +1073,16 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) return status; } +static int mxc_v4l2_send_command(cam_data *cam, + struct v4l2_send_command_control *c) { + int ret =0; + + if (vidioc_int_send_command(cam->sensor, c)) { + ret = -EINVAL; + } + return ret; +} + /*! * V4L2 - set_control function * V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing. @@ -1094,7 +1103,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) int tmp_rotation = IPU_ROTATE_NONE; struct sensor_data *sensor_data; - pr_debug("In MVC:mxc_v4l2_s_ctrl\n"); + pr_debug("%s\n", __func__); switch (c->id) { case V4L2_CID_HFLIP: @@ -1236,6 +1245,19 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) ipu_csi_flash_strobe(true); #endif break; + + case V4L2_CID_AUTO_FOCUS_START: { + ret = vidioc_int_s_ctrl(cam->sensor, c); + break; + } + + case V4L2_CID_AUTO_FOCUS_STOP: { + if (vidioc_int_s_ctrl(cam->sensor, c)) { + ret = -EINVAL; + } + break; + } + case V4L2_CID_MXC_SWITCH_CAM: if (cam->sensor == cam->all_sensors[c->value]) break; @@ -1293,7 +1315,7 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) u32 current_fps, parm_fps; int err = 0; - pr_debug("In mxc_v4l2_s_param\n"); + pr_debug("%s\n", __func__); if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n"); @@ -1428,8 +1450,7 @@ exit: */ static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e) { - pr_debug("In mxc_v4l2_s_std %Lx\n", e); - + pr_debug("%s: %Lx\n", __func__, e); if (e == V4L2_STD_PAL) { pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL); cam->standard.id = V4L2_STD_PAL; @@ -1474,7 +1495,7 @@ static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e) { struct v4l2_format tv_fmt; - pr_debug("In mxc_v4l2_g_std\n"); + pr_debug("%s\n", __func__); if (cam->device_type == 1) { /* Use this function to get what the TV-In device detects the @@ -1514,7 +1535,7 @@ static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) struct mxc_v4l_frame *frame; unsigned long lock_flags; - pr_debug("In MVC:mxc_v4l_dqueue\n"); + pr_debug("%s\n", __func__); if (!wait_event_interruptible_timeout(cam->enc_queue, cam->enc_counter != 0, 10 * HZ)) { @@ -1564,6 +1585,38 @@ static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) return retval; } +static void power_down_callback(struct work_struct *work) +{ + cam_data *cam = container_of(work, struct _cam_data, power_down_work.work); + + down(&cam->busy_lock); + if (!cam->open_count) { + pr_info("%s: ipu%d/csi%d\n", __func__, cam->ipu_id, cam->csi); + vidioc_int_s_power(cam->sensor, 0); + cam->power_on = 0; + } + up(&cam->busy_lock); +} + +/* cam->busy_lock is held */ +void power_up_camera(cam_data *cam) +{ + if (cam->power_on) { + cancel_delayed_work(&cam->power_down_work); + return; + } + vidioc_int_s_power(cam->sensor, 1); + vidioc_int_init(cam->sensor); + vidioc_int_dev_init(cam->sensor); + cam->power_on = 1; +} + + +void power_off_camera(cam_data *cam) +{ + schedule_delayed_work(&cam->power_down_work, (HZ * 2)); +} + /*! * V4L interface - open function * @@ -1582,18 +1635,19 @@ static int mxc_v4l_open(struct file *file) int err = 0; struct sensor_data *sensor; - pr_debug("\nIn MVC: mxc_v4l_open\n"); - pr_debug(" device name is %s\n", dev->name); - if (!cam) { - pr_err("ERROR: v4l2 capture: Internal error, " - "cam_data not found!\n"); + pr_err("%s: %s cam_data not found!\n", __func__, dev->name); return -EBADF; } - - if (cam->sensor == NULL || - cam->sensor->type != v4l2_int_type_slave) { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + if (!cam->sensor) { + pr_err("%s: %s no sensor ipu%d/csi%d\n", + __func__, dev->name, cam->ipu_id, cam->csi); + return -EAGAIN; + } + if (cam->sensor->type != v4l2_int_type_slave) { + pr_err("%s: %s wrong type ipu%d/csi%d, type=%d/%d\n", + __func__, dev->name, cam->ipu_id, cam->csi, + cam->sensor->type, v4l2_int_type_slave); return -EAGAIN; } @@ -1602,6 +1656,8 @@ static int mxc_v4l_open(struct file *file) pr_err("%s: Internal error, sensor_data is not found!\n", __func__); return -EBADF; } + pr_debug("%s: %s ipu%d/csi%d\n", __func__, dev->name, + cam->ipu_id, cam->csi); down(&cam->busy_lock); err = 0; @@ -1706,9 +1762,7 @@ static int mxc_v4l_open(struct file *file) cam_fmt.fmt.pix.pixelformat, csi_param); clk_prepare_enable(sensor->sensor_clk); - vidioc_int_s_power(cam->sensor, 1); - vidioc_int_init(cam->sensor); - vidioc_int_dev_init(cam->sensor); + power_up_camera(cam); } file->private_data = dev; @@ -1731,11 +1785,10 @@ static int mxc_v4l_close(struct file *file) int err = 0; cam_data *cam = video_get_drvdata(dev); struct sensor_data *sensor; - pr_debug("In MVC:mxc_v4l_close\n"); + pr_debug("%s\n", __func__); if (!cam) { - pr_err("ERROR: v4l2 capture: Internal error, " - "cam_data not found!\n"); + pr_err("%s: cam_data not found!\n", __func__); return -EBADF; } @@ -1763,7 +1816,6 @@ static int mxc_v4l_close(struct file *file) } if (--cam->open_count == 0) { - vidioc_int_s_power(cam->sensor, 0); clk_disable_unprepare(sensor->sensor_clk); wait_event_interruptible(cam->power_queue, cam->low_power == false); @@ -1788,6 +1840,7 @@ static int mxc_v4l_close(struct file *file) wake_up_interruptible(&cam->enc_queue); mxc_free_frames(cam); cam->enc_counter++; + power_off_camera(cam); } up(&cam->busy_lock); @@ -1905,7 +1958,7 @@ static long mxc_v4l_do_ioctl(struct file *file, int retval = 0; unsigned long lock_flags; - pr_debug("In MVC: mxc_v4l_do_ioctl %x\n", ioctlnr); + pr_debug("%s: %x ipu%d/csi%d\n", __func__, ioctlnr, cam->ipu_id, cam->csi); wait_event_interruptible(cam->power_queue, cam->low_power == false); /* make this _really_ smp-safe */ if (ioctlnr != VIDIOC_DQBUF) @@ -2245,6 +2298,10 @@ static long mxc_v4l_do_ioctl(struct file *file, case VIDIOC_ENUMSTD: { struct v4l2_standard *e = arg; pr_debug(" case VIDIOC_ENUMSTD\n"); + if (e->index > 0) { + retval = -EINVAL; + break; + } *e = cam->standard; break; } @@ -2387,6 +2444,12 @@ static long mxc_v4l_do_ioctl(struct file *file, } break; } + + case VIDIOC_SEND_COMMAND: { + retval = mxc_v4l2_send_command(cam, arg); + break; + } + case VIDIOC_TRY_FMT: case VIDIOC_QUERYCTRL: case VIDIOC_G_TUNER: @@ -2412,7 +2475,7 @@ static long mxc_v4l_do_ioctl(struct file *file, static long mxc_v4l_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - pr_debug("In MVC:mxc_v4l_ioctl\n"); + pr_debug("%s\n", __func__); return video_usercopy(file, cmd, arg, mxc_v4l_do_ioctl); } @@ -2432,8 +2495,7 @@ static int mxc_mmap(struct file *file, struct vm_area_struct *vma) int res = 0; cam_data *cam = video_get_drvdata(dev); - pr_debug("In MVC:mxc_mmap\n"); - pr_debug(" pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + pr_debug("%s:pgoff=0x%lx, start=0x%lx, end=0x%lx\n", __func__, vma->vm_pgoff, vma->vm_start, vma->vm_end); /* make this _really_ smp-safe */ @@ -2474,7 +2536,7 @@ static unsigned int mxc_poll(struct file *file, struct poll_table_struct *wait) wait_queue_head_t *queue = NULL; int res = POLLIN | POLLRDNORM; - pr_debug("In MVC:mxc_poll\n"); + pr_debug("%s\n", __func__); if (down_interruptible(&cam->busy_lock)) return -EINTR; @@ -2532,7 +2594,7 @@ static void camera_callback(u32 mask, void *dev) if (cam == NULL) return; - pr_debug("In MVC:camera_callback\n"); + pr_debug("%s\n", __func__); spin_lock(&cam->queue_int_lock); spin_lock(&cam->dqueue_int_lock); @@ -2611,8 +2673,9 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; int ipu_id, csi_id, mclk_source; int ret = 0; + static int camera_id; - pr_debug("In MVC: init_camera_struct\n"); + pr_debug("%s\n", __func__); ret = of_property_read_u32(np, "ipu_id", &ipu_id); if (ret) { @@ -2654,6 +2717,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) init_MUTEX(&cam->param_lock); init_MUTEX(&cam->busy_lock); + INIT_DELAYED_WORK(&cam->power_down_work, power_down_callback); cam->video_dev = video_device_alloc(); if (cam->video_dev == NULL) @@ -2715,7 +2779,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL); cam->self->module = THIS_MODULE; - sprintf(cam->self->name, "mxc_v4l2_cap%d", cam->csi); + sprintf(cam->self->name, "mxc_v4l2_cap%d", camera_id++); cam->self->type = v4l2_int_type_master; cam->self->u.master = &mxc_v4l2_master; @@ -2864,7 +2928,7 @@ static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state) { cam_data *cam = platform_get_drvdata(pdev); - pr_debug("In MVC:mxc_v4l2_suspend\n"); + pr_debug("%s\n", __func__); if (cam == NULL) return -1; @@ -2906,7 +2970,7 @@ static int mxc_v4l2_resume(struct platform_device *pdev) { cam_data *cam = platform_get_drvdata(pdev); - pr_debug("In MVC:mxc_v4l2_resume\n"); + pr_debug("%s\n", __func__); if (cam == NULL) return -1; @@ -2917,7 +2981,8 @@ static int mxc_v4l2_resume(struct platform_device *pdev) wake_up_interruptible(&cam->power_queue); if (cam->sensor && cam->open_count) { - vidioc_int_s_power(cam->sensor, 1); + if ((cam->overlay_on == true) || (cam->capture_on == true)) + vidioc_int_s_power(cam->sensor, 1); if (!cam->mclk_on[cam->mclk_source]) { ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, @@ -2964,17 +3029,17 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) int i; struct sensor_data *sdata = slave->priv; - pr_debug("In MVC: mxc_v4l2_master_attach\n"); - pr_debug(" slave.name = %s\n", slave->name); - pr_debug(" master.name = %s\n", slave->u.slave->master->name); + pr_debug("%s:slave.name = %s, master.name = %s\n", __func__, + slave->name, slave->u.slave->master->name); if (slave == NULL) { pr_err("ERROR: v4l2 capture: slave parameter not valid.\n"); return -1; } - if (sdata->csi != cam->csi) { - pr_debug("%s: csi doesn't match\n", __func__); + if ((sdata->ipu_id != cam->ipu_id) || (sdata->csi != cam->csi)) { + pr_debug("%s: ipu(%d:%d)/csi(%d:%d) doesn't match\n", __func__, + sdata->ipu_id, cam->ipu_id, sdata->csi, cam->csi); return -1; } @@ -2989,6 +3054,7 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) } for (i = 0; i < cam->sensor_index; i++) { + pr_err("%s: %x\n", __func__, i); vidioc_int_dev_exit(cam->all_sensors[i]); vidioc_int_s_power(cam->all_sensors[i], 0); } @@ -3027,6 +3093,8 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) __func__, cam->crop_current.width, cam->crop_current.height); + pr_info("%s: ipu%d:/csi%d attached %s:%s\n", __func__, cam->ipu_id, cam->csi, + slave->name, slave->u.slave->master->name); return 0; } @@ -3038,7 +3106,7 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) unsigned int i; cam_data *cam = slave->u.slave->master->priv; - pr_debug("In MVC:mxc_v4l2_master_detach\n"); + pr_debug("%s\n", __func__); if (cam->sensor_index > 1) { for (i = 0; i < cam->sensor_index; i++) { @@ -3060,6 +3128,20 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) vidioc_int_dev_exit(slave); } +DEFINE_MUTEX(camera_common_mutex); + +void mxc_camera_common_lock(void) +{ + mutex_lock(&camera_common_mutex); +} +EXPORT_SYMBOL(mxc_camera_common_lock); + +void mxc_camera_common_unlock(void) +{ + mutex_unlock(&camera_common_mutex); +} +EXPORT_SYMBOL(mxc_camera_common_unlock); + /*! * Entry point for the V4L2 * @@ -3069,7 +3151,7 @@ static __init int camera_init(void) { u8 err = 0; - pr_debug("In MVC:camera_init\n"); + pr_debug("%s\n", __func__); /* Register the device driver structure. */ err = platform_driver_register(&mxc_v4l2_driver); @@ -3087,7 +3169,7 @@ static __init int camera_init(void) */ static void __exit camera_exit(void) { - pr_debug("In MVC: camera_exit\n"); + pr_debug("%s\n", __func__); platform_driver_unregister(&mxc_v4l2_driver); } diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h index 09a421f20f7e..0abecbc788e1 100644 --- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h +++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h @@ -35,6 +35,7 @@ #include <linux/pxp_dma.h> #include <linux/ipu-v3.h> #include <linux/platform_data/dma-imx.h> +#include <linux/mipi_csi2.h> #include <media/v4l2-dev.h> #include <media/v4l2-int-device.h> @@ -114,6 +115,8 @@ typedef struct _cam_data { struct semaphore busy_lock; int open_count; + struct delayed_work power_down_work; + int power_on; /* params lock for this camera */ struct semaphore param_lock; @@ -200,6 +203,10 @@ typedef struct _cam_data { /* misc status flag */ bool overlay_on; bool capture_on; + bool ipu_enable_csi_called; + bool mipi_pixelclk_enabled; + struct ipu_chan *ipu_chan; + struct ipu_chan *ipu_chan_rot; int overlay_pid; int capture_pid; bool low_power; @@ -251,10 +258,95 @@ struct sensor_data { u32 mclk; u8 mclk_source; struct clk *sensor_clk; + int ipu_id; int csi; void (*io_init)(void); }; void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi); +void mxc_camera_common_lock(void); +void mxc_camera_common_unlock(void); + +static inline int cam_ipu_enable_csi(cam_data *cam) +{ + int ret = ipu_enable_csi(cam->ipu, cam->csi); + if (!ret) + cam->ipu_enable_csi_called = 1; + return ret; +} + +static inline int cam_ipu_disable_csi(cam_data *cam) +{ + if (!cam->ipu_enable_csi_called) + return 0; + cam->ipu_enable_csi_called = 0; + return ipu_disable_csi(cam->ipu, cam->csi); +} + +static inline int cam_mipi_csi2_enable(cam_data *cam, struct mipi_fields *mf) +{ +#ifdef CONFIG_MXC_MIPI_CSI2 + void *mipi_csi2_info; + int ipu_id; + int csi_id; + + mipi_csi2_info = mipi_csi2_get_info(); + + if (!mipi_csi2_info) { +// printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", +// __func__, __FILE__); +// return -EPERM; + return 0; + } + if (mipi_csi2_get_status(mipi_csi2_info)) { + ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); + csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); + + if (cam->ipu == ipu_get_soc(ipu_id) + && cam->csi == csi_id) { + mf->en = true; + mf->vc = mipi_csi2_get_virtual_channel(mipi_csi2_info); + mf->id = mipi_csi2_get_datatype(mipi_csi2_info); + if (!mipi_csi2_pixelclk_enable(mipi_csi2_info)) + cam->mipi_pixelclk_enabled = 1; + return 0; + } + } + mf->en = false; + mf->vc = 0; + mf->id = 0; +#endif + return 0; +} + +static inline int cam_mipi_csi2_disable(cam_data *cam) +{ +#ifdef CONFIG_MXC_MIPI_CSI2 + void *mipi_csi2_info; + int ipu_id; + int csi_id; + + if (!cam->mipi_pixelclk_enabled) + return 0; + cam->mipi_pixelclk_enabled = 0; + + mipi_csi2_info = mipi_csi2_get_info(); + + if (!mipi_csi2_info) { +// printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", +// __func__, __FILE__); +// return -EPERM; + return 0; + } + if (mipi_csi2_get_status(mipi_csi2_info)) { + ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info); + csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info); + + if ((cam->ipu == ipu_get_soc(ipu_id)) && (cam->csi == csi_id)) + mipi_csi2_pixelclk_disable(mipi_csi2_info); + } +#endif + return 0; +} #endif /* __MXC_V4L2_CAPTURE_H__ */ diff --git a/drivers/media/platform/mxc/capture/ov5640.c b/drivers/media/platform/mxc/capture/ov5640.c index 4759b9a478ce..f77c0d07b175 100644 --- a/drivers/media/platform/mxc/capture/ov5640.c +++ b/drivers/media/platform/mxc/capture/ov5640.c @@ -22,11 +22,14 @@ #include <linux/delay.h> #include <linux/device.h> #include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/init.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <media/v4l2-chip-ident.h> #include <media/v4l2-int-device.h> @@ -1818,6 +1821,8 @@ static int ov5640_probe(struct i2c_client *client, struct device *dev = &client->dev; int retval; u8 chip_id_high, chip_id_low; + struct regmap *gpr; + struct sensor_data *sensor = &ov5640_data; /* ov5640 pinctrl */ pinctrl = devm_pinctrl_get_select_default(dev); @@ -1870,6 +1875,13 @@ static int ov5640_probe(struct i2c_client *client, return retval; } + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + retval = of_property_read_u32(dev->of_node, "csi_id", &(ov5640_data.csi)); if (retval) { @@ -1911,6 +1923,26 @@ static int ov5640_probe(struct i2c_client *client, ov5640_power_down(1); + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + int mask = sensor->csi ? (1 << 20) : (1 << 19); + + if (sensor->csi != sensor->ipu_id) { + pr_warning("%s: csi_id != ipu_id\n", __func__); + return -ENODEV; + } + regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask); + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = sensor->csi ? (7 << 3) : (7 << 0); + int val = sensor->csi ? (4 << 3) : (4 << 0); + + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } clk_disable_unprepare(ov5640_data.sensor_clk); ov5640_int_device.priv = &ov5640_data; diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi.c b/drivers/media/platform/mxc/capture/ov5640_mipi.c index 79264bc63796..f91ee983c196 100644 --- a/drivers/media/platform/mxc/capture/ov5640_mipi.c +++ b/drivers/media/platform/mxc/capture/ov5640_mipi.c @@ -27,8 +27,13 @@ #include <linux/clk.h> #include <linux/of_device.h> #include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> +#include <linux/proc_fs.h> +#include <linux/pwm.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/fsl_devices.h> #include <linux/mipi_csi2.h> @@ -94,12 +99,1271 @@ struct ov5640_mode_info { u32 init_data_size; }; +#define CMD_MAIN 0x3022 +#define CMD_ACK 0x3023 +#define CMD_PARA0 0x3024 +#define CMD_PARA1 0x3025 +#define CMD_PARA2 0x3026 +#define CMD_PARA3 0x3027 +#define CMD_PARA4 0x3028 +#define FW_STATUS 0x3029 + /*! * Maintains the information on the current state of the sesor. */ static struct sensor_data ov5640_data; static int pwn_gpio, rst_gpio; +static struct reg_value ov5640_af_firmware[] = { + {0x8000, 0x02, 0, 0}, {0x8001, 0x0b, 0, 0}, {0x8002,0x03, 0, 0}, + {0x8003, 0x02, 0, 0}, {0x8004, 0x07, 0, 0}, {0x8005,0x5d, 0, 0}, + {0x8006, 0xc2, 0, 0}, {0x8007, 0x01, 0, 0}, {0x8008,0x22, 0, 0}, + {0x8009, 0x22, 0, 0}, {0x800a, 0x00, 0, 0}, {0x800b,0x02, 0, 0}, + {0x800c, 0x0a, 0, 0}, {0x800d, 0xed, 0, 0}, {0x800e,0xe5, 0, 0}, + {0x800f, 0x40, 0, 0}, {0x8010, 0x60, 0, 0}, {0x8011,0x03, 0, 0}, + {0x8012, 0x02, 0, 0}, {0x8013, 0x00, 0, 0}, {0x8014,0x97, 0, 0}, + {0x8015, 0xf5, 0, 0}, {0x8016, 0x3f, 0, 0}, {0x8017,0xd2, 0, 0}, + {0x8018, 0x34, 0, 0}, {0x8019, 0x75, 0, 0}, {0x801a,0x29, 0, 0}, + {0x801b, 0xff, 0, 0}, {0x801c, 0x75, 0, 0}, {0x801d,0x2a, 0, 0}, + {0x801e, 0x0e, 0, 0}, {0x801f, 0x75, 0, 0}, {0x8020,0x2b, 0, 0}, + {0x8021, 0x55, 0, 0}, {0x8022, 0x75, 0, 0}, {0x8023,0x2c, 0, 0}, + {0x8024, 0x01, 0, 0}, {0x8025, 0x12, 0, 0}, {0x8026,0x09, 0, 0}, + {0x8027, 0xe0, 0, 0}, {0x8028, 0xe4, 0, 0}, {0x8029,0xff, 0, 0}, + {0x802a, 0xef, 0, 0}, {0x802b, 0x25, 0, 0}, {0x802c,0xe0, 0, 0}, + {0x802d, 0x24, 0, 0}, {0x802e, 0x41, 0, 0}, {0x802f,0xf8, 0, 0}, + {0x8030, 0xe4, 0, 0}, {0x8031, 0xf6, 0, 0}, {0x8032,0x08, 0, 0}, + {0x8033, 0xf6, 0, 0}, {0x8034, 0x0f, 0, 0}, {0x8035,0xbf, 0, 0}, + {0x8036, 0x34, 0, 0}, {0x8037, 0xf2, 0, 0}, {0x8038,0x90, 0, 0}, + {0x8039, 0x0e, 0, 0}, {0x803a, 0x88, 0, 0}, {0x803b,0xe4, 0, 0}, + {0x803c, 0x93, 0, 0}, {0x803d, 0xff, 0, 0}, {0x803e,0xe5, 0, 0}, + {0x803f, 0x3e, 0, 0}, {0x8040, 0xc3, 0, 0}, {0x8041,0x9f, 0, 0}, + {0x8042, 0x50, 0, 0}, {0x8043, 0x04, 0, 0}, {0x8044,0x7f, 0, 0}, + {0x8045, 0x05, 0, 0}, {0x8046, 0x80, 0, 0}, {0x8047,0x02, 0, 0}, + {0x8048, 0x7f, 0, 0}, {0x8049, 0xfb, 0, 0}, {0x804a,0x78, 0, 0}, + {0x804b, 0xb0, 0, 0}, {0x804c, 0xa6, 0, 0}, {0x804d,0x07, 0, 0}, + {0x804e, 0x12, 0, 0}, {0x804f, 0x0a, 0, 0}, {0x8050,0x4a, 0, 0}, + {0x8051, 0x40, 0, 0}, {0x8052, 0x04, 0, 0}, {0x8053,0x7f, 0, 0}, + {0x8054, 0x03, 0, 0}, {0x8055, 0x80, 0, 0}, {0x8056,0x02, 0, 0}, + {0x8057, 0x7f, 0, 0}, {0x8058, 0x30, 0, 0}, {0x8059,0x78, 0, 0}, + {0x805a, 0xaf, 0, 0}, {0x805b, 0xa6, 0, 0}, {0x805c,0x07, 0, 0}, + {0x805d, 0xe6, 0, 0}, {0x805e, 0x18, 0, 0}, {0x805f,0xf6, 0, 0}, + {0x8060, 0x08, 0, 0}, {0x8061, 0xe6, 0, 0}, {0x8062,0x78, 0, 0}, + {0x8063, 0xac, 0, 0}, {0x8064, 0xf6, 0, 0}, {0x8065,0x78, 0, 0}, + {0x8066, 0xaf, 0, 0}, {0x8067, 0xe6, 0, 0}, {0x8068,0x78, 0, 0}, + {0x8069, 0xad, 0, 0}, {0x806a, 0xf6, 0, 0}, {0x806b,0x78, 0, 0}, + {0x806c, 0xb2, 0, 0}, {0x806d, 0x76, 0, 0}, {0x806e,0x33, 0, 0}, + {0x806f, 0xe4, 0, 0}, {0x8070, 0x08, 0, 0}, {0x8071,0xf6, 0, 0}, + {0x8072, 0x78, 0, 0}, {0x8073, 0xab, 0, 0}, {0x8074,0x76, 0, 0}, + {0x8075, 0x01, 0, 0}, {0x8076, 0x75, 0, 0}, {0x8077,0x3d, 0, 0}, + {0x8078, 0x02, 0, 0}, {0x8079, 0x78, 0, 0}, {0x807a,0xa9, 0, 0}, + {0x807b, 0xf6, 0, 0}, {0x807c, 0x08, 0, 0}, {0x807d,0xf6, 0, 0}, + {0x807e, 0x74, 0, 0}, {0x807f, 0xff, 0, 0}, {0x8080,0x78, 0, 0}, + {0x8081, 0xb4, 0, 0}, {0x8082, 0xf6, 0, 0}, {0x8083,0x08, 0, 0}, + {0x8084, 0xf6, 0, 0}, {0x8085, 0x75, 0, 0}, {0x8086,0x40, 0, 0}, + {0x8087, 0x01, 0, 0}, {0x8088, 0x78, 0, 0}, {0x8089,0xaf, 0, 0}, + {0x808a, 0xe6, 0, 0}, {0x808b, 0x75, 0, 0}, {0x808c,0xf0, 0, 0}, + {0x808d, 0x05, 0, 0}, {0x808e, 0xa4, 0, 0}, {0x808f,0xf5, 0, 0}, + {0x8090, 0x3e, 0, 0}, {0x8091, 0x12, 0, 0}, {0x8092,0x07, 0, 0}, + {0x8093, 0xf1, 0, 0}, {0x8094, 0xc2, 0, 0}, {0x8095,0x36, 0, 0}, + {0x8096, 0x22, 0, 0}, {0x8097, 0x78, 0, 0}, {0x8098,0xab, 0, 0}, + {0x8099, 0xe6, 0, 0}, {0x809a, 0xd3, 0, 0}, {0x809b,0x94, 0, 0}, + {0x809c, 0x00, 0, 0}, {0x809d, 0x40, 0, 0}, {0x809e,0x02, 0, 0}, + {0x809f, 0x16, 0, 0}, {0x80a0, 0x22, 0, 0}, {0x80a1,0xe5, 0, 0}, + {0x80a2, 0x40, 0, 0}, {0x80a3, 0x64, 0, 0}, {0x80a4,0x05, 0, 0}, + {0x80a5, 0x70, 0, 0}, {0x80a6, 0x28, 0, 0}, {0x80a7,0xf5, 0, 0}, + {0x80a8, 0x40, 0, 0}, {0x80a9, 0xc2, 0, 0}, {0x80aa,0x01, 0, 0}, + {0x80ab, 0x78, 0, 0}, {0x80ac, 0xac, 0, 0}, {0x80ad,0xe6, 0, 0}, + {0x80ae, 0x25, 0, 0}, {0x80af, 0xe0, 0, 0}, {0x80b0,0x24, 0, 0}, + {0x80b1, 0x41, 0, 0}, {0x80b2, 0xf8, 0, 0}, {0x80b3,0xe6, 0, 0}, + {0x80b4, 0xfe, 0, 0}, {0x80b5, 0x08, 0, 0}, {0x80b6,0xe6, 0, 0}, + {0x80b7, 0xff, 0, 0}, {0x80b8, 0x78, 0, 0}, {0x80b9,0x41, 0, 0}, + {0x80ba, 0xa6, 0, 0}, {0x80bb, 0x06, 0, 0}, {0x80bc,0x08, 0, 0}, + {0x80bd, 0xa6, 0, 0}, {0x80be, 0x07, 0, 0}, {0x80bf,0xa2, 0, 0}, + {0x80c0, 0x36, 0, 0}, {0x80c1, 0xe4, 0, 0}, {0x80c2,0x33, 0, 0}, + {0x80c3, 0xf5, 0, 0}, {0x80c4, 0x31, 0, 0}, {0x80c5,0x90, 0, 0}, + {0x80c6, 0x30, 0, 0}, {0x80c7, 0x28, 0, 0}, {0x80c8,0xf0, 0, 0}, + {0x80c9, 0x75, 0, 0}, {0x80ca, 0x3f, 0, 0}, {0x80cb,0x10, 0, 0}, + {0x80cc, 0xd2, 0, 0}, {0x80cd, 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{0x8d01,0x00, 0, 0}, + {0x8d02, 0x00, 0, 0}, {0x8d03, 0x00, 0, 0}, {0x8d04,0x00, 0, 0}, + {0x8d05, 0x00, 0, 0}, {0x8d06, 0x00, 0, 0}, {0x8d07,0x00, 0, 0}, + {0x8d08, 0x00, 0, 0}, {0x8d09, 0x00, 0, 0}, {0x8d0a,0x00, 0, 0}, + {0x8d0b, 0x00, 0, 0}, {0x8d0c, 0x00, 0, 0}, {0x8d0d,0x00, 0, 0}, + {0x8d0e, 0x00, 0, 0}, {0x8d0f, 0x00, 0, 0}, {0x8d10,0x00, 0, 0}, + {0x8d11, 0x00, 0, 0}, {0x8d12, 0x00, 0, 0}, {0x8d13,0x00, 0, 0}, + {0x8d14, 0x00, 0, 0}, {0x8d15, 0x00, 0, 0}, {0x8d16,0x00, 0, 0}, + {0x8d17, 0x00, 0, 0}, {0x8d18, 0x00, 0, 0}, {0x8d19,0x00, 0, 0}, + {0x8d1a, 0x00, 0, 0}, {0x8d1b, 0x00, 0, 0}, {0x8d1c,0x00, 0, 0}, + {0x8d1d, 0x00, 0, 0}, {0x8d1e, 0x00, 0, 0}, {0x8d1f,0x00, 0, 0}, + {0x8d20, 0x00, 0, 0}, {0x8d21, 0x00, 0, 0}, {0x8d22,0x00, 0, 0}, + {0x8d23, 0x00, 0, 0}, {0x8d24, 0x00, 0, 0}, {0x8d25,0x00, 0, 0}, + {0x8d26, 0x00, 0, 0}, {0x8d27, 0x00, 0, 0}, {0x8d28,0x00, 0, 0}, + {0x8d29, 0x00, 0, 0}, {0x8d2a, 0x00, 0, 0}, {0x8d2b,0x00, 0, 0}, + {0x8d2c, 0x00, 0, 0}, {0x8d2d, 0x00, 0, 0}, {0x8d2e,0x00, 0, 0}, + {0x8d2f, 0x00, 0, 0}, {0x8d30, 0x00, 0, 0}, {0x8d31,0x00, 0, 0}, + {0x8d32, 0x00, 0, 0}, {0x8d33, 0x00, 0, 0}, {0x8d34,0x00, 0, 0}, + {0x8d35, 0x00, 0, 0}, {0x8d36, 0x00, 0, 0}, {0x8d37,0x00, 0, 0}, + {0x8d38, 0x00, 0, 0}, {0x8d39, 0x00, 0, 0}, {0x8d3a,0x00, 0, 0}, + {0x8d3b, 0x00, 0, 0}, {0x8d3c, 0x00, 0, 0}, {0x8d3d,0x00, 0, 0}, + {0x8d3e, 0x00, 0, 0}, {0x8d3f, 0x00, 0, 0}, {0x8d40,0x00, 0, 0}, + {0x8d41, 0x00, 0, 0}, {0x8d42, 0x00, 0, 0}, {0x8d43,0x00, 0, 0}, + {0x8d44, 0x00, 0, 0}, {0x8d45, 0x00, 0, 0}, {0x8d46,0x00, 0, 0}, + {0x8d47, 0x00, 0, 0}, {0x8d48, 0x00, 0, 0}, {0x8d49,0x00, 0, 0}, + {0x8d4a, 0x00, 0, 0}, {0x8d4b, 0x00, 0, 0}, {0x8d4c,0x00, 0, 0}, + {0x8d4d, 0x00, 0, 0}, {0x8d4e, 0x00, 0, 0}, {0x8d4f,0x00, 0, 0}, + {0x8d50, 0x00, 0, 0}, {0x8d51, 0x00, 0, 0}, {0x8d52,0x00, 0, 0}, + {0x8d53, 0x00, 0, 0}, {0x8d54, 0x00, 0, 0}, {0x8d55,0x00, 0, 0}, + {0x8d56, 0x00, 0, 0}, {0x8d57, 0x00, 0, 0}, {0x8d58,0x00, 0, 0}, + {0x8d59, 0x00, 0, 0}, {0x8d5a, 0x00, 0, 0}, {0x8d5b,0x00, 0, 0}, + {0x8d5c, 0x00, 0, 0}, {0x8d5d, 0x00, 0, 0}, {0x8d5e,0x00, 0, 0}, + {0x8d5f, 0x00, 0, 0}, {0x8d60, 0x00, 0, 0}, {0x8d61,0x00, 0, 0}, + {0x8d62, 0x00, 0, 0}, {0x8d63, 0x00, 0, 0}, {0x8d64,0x00, 0, 0}, + {0x8d65, 0x00, 0, 0}, {0x8d66, 0x00, 0, 0}, {0x8d67,0x00, 0, 0}, + {0x8d68, 0x00, 0, 0}, {0x8d69, 0x00, 0, 0}, {0x8d6a,0x00, 0, 0}, + {0x8d6b, 0x00, 0, 0}, {0x8d6c, 0x00, 0, 0}, {0x8d6d,0x00, 0, 0}, + {0x8d6e, 0x00, 0, 0}, {0x8d6f, 0x00, 0, 0}, {0x8d70,0x00, 0, 0}, + {0x8d71, 0x00, 0, 0}, {0x8d72, 0x00, 0, 0}, {0x8d73,0x00, 0, 0}, + {0x8d74, 0x00, 0, 0}, {0x8d75, 0x00, 0, 0}, {0x8d76,0x00, 0, 0}, + {0x8d77, 0x00, 0, 0}, {0x8d78, 0x00, 0, 0}, {0x8d79,0x00, 0, 0}, + {0x8d7a, 0x00, 0, 0}, {0x8d7b, 0x00, 0, 0}, {0x8d7c,0x00, 0, 0}, + {0x8d7d, 0x00, 0, 0}, {0x8d7e, 0x00, 0, 0}, {0x8d7f,0x00, 0, 0}, + {0x8d80, 0x00, 0, 0}, {0x8d81, 0x00, 0, 0}, {0x8d82,0x00, 0, 0}, + {0x8d83, 0x00, 0, 0}, {0x8d84, 0x00, 0, 0}, {0x8d85,0x00, 0, 0}, + {0x8d86, 0x00, 0, 0}, {0x8d87, 0x00, 0, 0}, {0x8d88,0x00, 0, 0}, + {0x8d89, 0x00, 0, 0}, {0x8d8a, 0x00, 0, 0}, {0x8d8b,0x00, 0, 0}, + {0x8d8c, 0x00, 0, 0}, {0x8d8d, 0x00, 0, 0}, {0x8d8e,0x00, 0, 0}, + {0x8d8f, 0x00, 0, 0}, {0x8d90, 0x00, 0, 0}, {0x8d91,0x00, 0, 0}, + {0x8d92, 0x00, 0, 0}, {0x8d93, 0x00, 0, 0}, {0x8d94,0x00, 0, 0}, + {0x8d95, 0x00, 0, 0}, {0x8d96, 0x00, 0, 0}, {0x8d97,0x00, 0, 0}, + {0x8d98, 0x00, 0, 0}, {0x8d99, 0x00, 0, 0}, {0x8d9a,0x00, 0, 0}, + {0x8d9b, 0x00, 0, 0}, {0x8d9c, 0x00, 0, 0}, {0x8d9d,0x00, 0, 0}, + {0x8d9e, 0x00, 0, 0}, {0x8d9f, 0x00, 0, 0}, {0x8da0,0x00, 0, 0}, + {0x8da1, 0x00, 0, 0}, {0x8da2, 0x00, 0, 0}, {0x8da3,0x00, 0, 0}, + {0x8da4, 0x00, 0, 0}, {0x8da5, 0x00, 0, 0}, {0x8da6,0x00, 0, 0}, + {0x8da7, 0x00, 0, 0}, {0x8da8, 0x00, 0, 0}, {0x8da9,0x00, 0, 0}, + {0x8daa, 0x00, 0, 0}, {0x8dab, 0x00, 0, 0}, {0x8dac,0x00, 0, 0}, + {0x8dad, 0x00, 0, 0}, {0x8dae, 0x00, 0, 0}, {0x8daf,0x00, 0, 0}, + {0x8db0, 0x00, 0, 0}, {0x8db1, 0x00, 0, 0}, {0x8db2,0x00, 0, 0}, + {0x8db3, 0x00, 0, 0}, {0x8db4, 0x00, 0, 0}, {0x8db5,0x00, 0, 0}, + {0x8db6, 0x00, 0, 0}, {0x8db7, 0x00, 0, 0}, {0x8db8,0x00, 0, 0}, + {0x8db9, 0x00, 0, 0}, {0x8dba, 0x00, 0, 0}, {0x8dbb,0x00, 0, 0}, + {0x8dbc, 0x00, 0, 0}, {0x8dbd, 0x00, 0, 0}, {0x8dbe,0x00, 0, 0}, + {0x8dbf, 0x00, 0, 0}, {0x8dc0, 0x00, 0, 0}, {0x8dc1,0x00, 0, 0}, + {0x8dc2, 0x00, 0, 0}, {0x8dc3, 0x00, 0, 0}, {0x8dc4,0x00, 0, 0}, + {0x8dc5, 0x00, 0, 0}, {0x8dc6, 0x00, 0, 0}, {0x8dc7,0x00, 0, 0}, + {0x8dc8, 0x00, 0, 0}, {0x8dc9, 0x00, 0, 0}, {0x8dca,0x00, 0, 0}, + {0x8dcb, 0x00, 0, 0}, {0x8dcc, 0x00, 0, 0}, {0x8dcd,0x00, 0, 0}, + {0x8dce, 0x00, 0, 0}, {0x8dcf, 0x00, 0, 0}, {0x8dd0,0x00, 0, 0}, + {0x8dd1, 0x00, 0, 0}, {0x8dd2, 0x00, 0, 0}, {0x8dd3,0x00, 0, 0}, + {0x8dd4, 0x00, 0, 0}, {0x8dd5, 0x00, 0, 0}, {0x8dd6,0x00, 0, 0}, + {0x8dd7, 0x00, 0, 0}, {0x8dd8, 0x00, 0, 0}, {0x8dd9,0x00, 0, 0}, + {0x8dda, 0x00, 0, 0}, {0x8ddb, 0x00, 0, 0}, {0x8ddc,0x00, 0, 0}, + {0x8ddd, 0x00, 0, 0}, {0x8dde, 0x00, 0, 0}, {0x8ddf,0x00, 0, 0}, + {0x8de0, 0x00, 0, 0}, {0x8de1, 0x00, 0, 0}, {0x8de2,0x00, 0, 0}, + {0x8de3, 0x00, 0, 0}, {0x8de4, 0x00, 0, 0}, {0x8de5,0x00, 0, 0}, + {0x8de6, 0x00, 0, 0}, {0x8de7, 0x00, 0, 0}, {0x8de8,0x00, 0, 0}, + {0x8de9, 0x00, 0, 0}, {0x8dea, 0x00, 0, 0}, {0x8deb,0x00, 0, 0}, + {0x8dec, 0x00, 0, 0}, {0x8ded, 0x00, 0, 0}, {0x8dee,0x00, 0, 0}, + {0x8def, 0x00, 0, 0}, {0x8df0, 0x00, 0, 0}, {0x8df1,0x00, 0, 0}, + {0x8df2, 0x00, 0, 0}, {0x8df3, 0x00, 0, 0}, {0x8df4,0x00, 0, 0}, + {0x8df5, 0x00, 0, 0}, {0x8df6, 0x00, 0, 0}, {0x8df7,0x00, 0, 0}, + {0x8df8, 0x00, 0, 0}, {0x8df9, 0x00, 0, 0}, {0x8dfa,0x00, 0, 0}, + {0x8dfb, 0x00, 0, 0}, {0x8dfc, 0x00, 0, 0}, {0x8dfd,0x00, 0, 0}, + {0x8dfe, 0x00, 0, 0}, {0x8dff, 0x00, 0, 0}, {0x8e00,0x11, 0, 0}, + {0x8e01, 0x03, 0, 0}, {0x8e02, 0x21, 0, 0}, {0x8e03,0x14, 0, 0}, + {0x8e04, 0x31, 0, 0}, {0x8e05, 0x31, 0, 0}, {0x8e06,0x4f, 0, 0}, + {0x8e07, 0x56, 0, 0}, {0x8e08, 0x54, 0, 0}, {0x8e09,0x20, 0, 0}, + {0x8e0a, 0x20, 0, 0}, {0x8e0b, 0x20, 0, 0}, {0x8e0c,0x20, 0, 0}, + {0x8e0d, 0x20, 0, 0}, {0x8e0e, 0x20, 0, 0}, {0x8e0f,0x00, 0, 0}, + {0x8e10, 0x10, 0, 0}, {0x8e11, 0x00, 0, 0}, {0x8e12,0x56, 0, 0}, + {0x8e13, 0x40, 0, 0}, {0x8e14, 0x1a, 0, 0}, {0x8e15,0x30, 0, 0}, + {0x8e16, 0x29, 0, 0}, {0x8e17, 0x7e, 0, 0}, {0x8e18,0x00, 0, 0}, + {0x8e19, 0x30, 0, 0}, {0x8e1a, 0x04, 0, 0}, {0x8e1b,0x20, 0, 0}, + {0x8e1c, 0xdf, 0, 0}, {0x8e1d, 0x30, 0, 0}, {0x8e1e,0x05, 0, 0}, + {0x8e1f, 0x40, 0, 0}, {0x8e20, 0xbf, 0, 0}, {0x8e21,0x50, 0, 0}, + {0x8e22, 0x25, 0, 0}, {0x8e23, 0x04, 0, 0}, {0x8e24,0xfb, 0, 0}, + {0x8e25, 0x50, 0, 0}, {0x8e26, 0x03, 0, 0}, {0x8e27,0x00, 0, 0}, + {0x8e28, 0xfd, 0, 0}, {0x8e29, 0x50, 0, 0}, {0x8e2a,0x27, 0, 0}, + {0x8e2b, 0x01, 0, 0}, {0x8e2c, 0xfe, 0, 0}, {0x8e2d,0x60, 0, 0}, + {0x8e2e, 0x00, 0, 0}, {0x8e2f, 0x11, 0, 0}, {0x8e30,0x00, 0, 0}, + {0x8e31, 0x3f, 0, 0}, {0x8e32, 0x05, 0, 0}, {0x8e33,0x30, 0, 0}, + {0x8e34, 0x00, 0, 0}, {0x8e35, 0x3f, 0, 0}, {0x8e36,0x06, 0, 0}, + {0x8e37, 0x22, 0, 0}, {0x8e38, 0x00, 0, 0}, {0x8e39,0x3f, 0, 0}, + {0x8e3a, 0x01, 0, 0}, {0x8e3b, 0x29, 0, 0}, {0x8e3c,0x00, 0, 0}, + {0x8e3d, 0x3f, 0, 0}, {0x8e3e, 0x02, 0, 0}, {0x8e3f,0x00, 0, 0}, + {0x8e40, 0x00, 0, 0}, {0x8e41, 0x36, 0, 0}, {0x8e42,0x06, 0, 0}, + {0x8e43, 0x07, 0, 0}, {0x8e44, 0x00, 0, 0}, {0x8e45,0x3f, 0, 0}, + {0x8e46, 0x0b, 0, 0}, {0x8e47, 0x0f, 0, 0}, {0x8e48,0xf0, 0, 0}, + {0x8e49, 0x30, 0, 0}, {0x8e4a, 0x01, 0, 0}, {0x8e4b,0x40, 0, 0}, + {0x8e4c, 0xbf, 0, 0}, {0x8e4d, 0x30, 0, 0}, {0x8e4e,0x01, 0, 0}, + {0x8e4f, 0x00, 0, 0}, {0x8e50, 0xbf, 0, 0}, {0x8e51,0x30, 0, 0}, + {0x8e52, 0x29, 0, 0}, {0x8e53, 0x70, 0, 0}, {0x8e54,0x00, 0, 0}, + {0x8e55, 0x3a, 0, 0}, {0x8e56, 0x00, 0, 0}, {0x8e57,0x01, 0, 0}, + {0x8e58, 0xfe, 0, 0}, {0x8e59, 0x3a, 0, 0}, {0x8e5a,0x00, 0, 0}, + {0x8e5b, 0x00, 0, 0}, {0x8e5c, 0xfe, 0, 0}, {0x8e5d,0x36, 0, 0}, + {0x8e5e, 0x03, 0, 0}, {0x8e5f, 0x36, 0, 0}, {0x8e60,0x02, 0, 0}, + {0x8e61, 0x41, 0, 0}, {0x8e62, 0x44, 0, 0}, {0x8e63,0x58, 0, 0}, + {0x8e64, 0x20, 0, 0}, {0x8e65, 0x18, 0, 0}, {0x8e66,0x10, 0, 0}, + {0x8e67, 0x0a, 0, 0}, {0x8e68, 0x04, 0, 0}, {0x8e69,0x04, 0, 0}, + {0x8e6a, 0x00, 0, 0}, {0x8e6b, 0x03, 0, 0}, {0x8e6c,0xff, 0, 0}, + {0x8e6d, 0x64, 0, 0}, {0x8e6e, 0x00, 0, 0}, {0x8e6f,0x00, 0, 0}, + {0x8e70, 0x80, 0, 0}, {0x8e71, 0x00, 0, 0}, {0x8e72,0x00, 0, 0}, + {0x8e73, 0x00, 0, 0}, {0x8e74, 0x00, 0, 0}, {0x8e75,0x00, 0, 0}, + {0x8e76, 0x00, 0, 0}, {0x8e77, 0x02, 0, 0}, {0x8e78,0x04, 0, 0}, + {0x8e79, 0x06, 0, 0}, {0x8e7a, 0x00, 0, 0}, {0x8e7b,0x03, 0, 0}, + {0x8e7c, 0x98, 0, 0}, {0x8e7d, 0x00, 0, 0}, {0x8e7e,0xcc, 0, 0}, + {0x8e7f, 0x50, 0, 0}, {0x8e80, 0x3c, 0, 0}, {0x8e81,0x28, 0, 0}, + {0x8e82, 0x1e, 0, 0}, {0x8e83, 0x10, 0, 0}, {0x8e84,0x10, 0, 0}, + {0x8e85, 0x00, 0, 0}, {0x8e86, 0x00, 0, 0}, {0x8e87,0x00, 0, 0}, + {0x8e88, 0x6e, 0, 0}, {0x8e89, 0x05, 0, 0}, {0x8e8a,0x05, 0, 0}, + {0x8e8b, 0x00, 0, 0}, {0x8e8c, 0xa5, 0, 0}, {0x8e8d,0x5a, 0, 0}, + + /* un-documented registers */ + {0x3022, 0x00, 0, 0}, {0x3023, 0x00, 0, 0}, {0x3024,0x00, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x00, 0, 0}, {0x3027,0x00, 0, 0}, + {0x3028, 0x00, 0, 0}, {0x3029, 0xff, 0, 0} +}; + static struct reg_value ov5640_init_setting_30fps_VGA[] = { {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0}, @@ -680,12 +1944,40 @@ static void ov5640_standby(s32 enable) gpio_set_value(pwn_gpio, 1); else gpio_set_value(pwn_gpio, 0); - + pr_debug("ov5640_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio); msleep(2); } +static s32 update_device_addr(struct sensor_data *sensor) +{ + int ret; + u8 buf[4]; + unsigned reg = 0x3100; + unsigned default_addr = 0x3c; + struct i2c_msg msg; + + if (sensor->i2c_client->addr == default_addr) + return 0; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + buf[2] = sensor->i2c_client->addr << 1; + msg.addr = default_addr; + msg.flags = 0; + msg.len = 3; + msg.buf = buf; + + + ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1); + if (ret < 0) + pr_err("%s: ov5640_mipi ret=%d\n", __func__, ret); + return ret; +} + static void ov5640_reset(void) { + mxc_camera_common_lock(); + /* camera reset */ gpio_set_value(rst_gpio, 1); @@ -700,7 +1992,10 @@ static void ov5640_reset(void) msleep(1); gpio_set_value(rst_gpio, 1); - msleep(5); + msleep(20); + pr_debug("%s(mipi): reset released\n", __func__); + update_device_addr(&ov5640_data); + mxc_camera_common_unlock(); gpio_set_value(pwn_gpio, 1); } @@ -769,44 +2064,65 @@ static int ov5640_power_on(struct device *dev) static s32 ov5640_write_reg(u16 reg, u8 val) { + int ret; u8 au8Buf[3] = {0}; au8Buf[0] = reg >> 8; au8Buf[1] = reg & 0xff; au8Buf[2] = val; - if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) { - pr_err("%s:write reg error:reg=%x,val=%x\n", - __func__, reg, val); - return -1; +#if 0 /* Software reset does not affect the i2c address register like it does on ov5642 */ + if ((reg == 0x3008) && (val & 0x80)) { + mxc_camera_common_lock(); + + ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3); + pr_debug("%s(mipi): software reset %d\n", __func__, ret); + update_device_addr(&ov5640_data); + + mxc_camera_common_unlock(); + } else +#endif + { + ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3); } + if (ret < 0) { + pr_err("%s(mipi):reg=%x,val=%x error=%d\n", + __func__, reg, val, ret); + return ret; + } + pr_debug("%s(mipi):reg=%x,val=%x\n", __func__, reg, val); return 0; } static s32 ov5640_read_reg(u16 reg, u8 *val) { - u8 au8RegBuf[2] = {0}; - u8 u8RdVal = 0; - - au8RegBuf[0] = reg >> 8; - au8RegBuf[1] = reg & 0xff; - - if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) { - pr_err("%s:write reg error:reg=%x\n", - __func__, reg); - return -1; - } + struct sensor_data *sensor = &ov5640_data; + struct i2c_client *client = sensor->i2c_client; + struct i2c_msg msgs[2]; + u8 buf[2]; + int ret; - if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) { - pr_err("%s:read reg error:reg=%x,val=%x\n", - __func__, reg, u8RdVal); - return -1; + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = buf; + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = 1; + msgs[1].buf = buf; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret < 0) { + pr_err("%s(mipi):reg=%x ret=%d\n", __func__, reg, ret); + return ret; } - - *val = u8RdVal; - - return u8RdVal; + *val = buf[0]; + pr_debug("%s(mipi):reg=%x,val=%x\n", __func__, reg, buf[0]); + return buf[0]; } static int prev_sysclk, prev_HTS; @@ -822,43 +2138,62 @@ void OV5640_stream_off(void) ov5640_write_reg(0x4202, 0x0f); } +static const int sclk_rdiv_map[] = {1, 2, 4, 8}; int OV5640_get_sysclk(void) { /* calculate sysclk */ - int xvclk = ov5640_data.mclk / 10000; - int temp1, temp2; - int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv; - int Bit_div2x = 1, sclk_rdiv, sysclk; + int tmp; + unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1; + unsigned div, sclk_rdiv, sysclk; u8 temp; - int sclk_rdiv_map[] = {1, 2, 4, 8}; - - temp1 = ov5640_read_reg(0x3034, &temp); - temp2 = temp1 & 0x0f; - if (temp2 == 8 || temp2 == 10) - Bit_div2x = temp2 / 2; - - temp1 = ov5640_read_reg(0x3035, &temp); - SysDiv = temp1>>4; + tmp = ov5640_read_reg(0x3034, &temp); + if (tmp < 0) + return tmp; + tmp &= 0x0f; + if (tmp == 8 || tmp == 10) + Bit_div2x = tmp / 2; + + tmp = ov5640_read_reg(0x3035, &temp); + if (tmp < 0) + return tmp; + SysDiv = tmp >> 4; if (SysDiv == 0) - SysDiv = 16; - - temp1 = ov5640_read_reg(0x3036, &temp); - Multiplier = temp1; - - temp1 = ov5640_read_reg(0x3037, &temp); - PreDiv = temp1 & 0x0f; - Pll_rdiv = ((temp1 >> 4) & 0x01) + 1; - - temp1 = ov5640_read_reg(0x3108, &temp); - temp2 = temp1 & 0x03; - sclk_rdiv = sclk_rdiv_map[temp2]; - - VCO = xvclk * Multiplier / PreDiv; - - sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv; - + SysDiv = 16; + + tmp = ov5640_read_reg(0x3036, &temp); + if (tmp < 0) + return tmp; + Multiplier = tmp; + + tmp = ov5640_read_reg(0x3037, &temp); + if (tmp < 0) + return tmp; + PreDiv = tmp & 0x0f; + Pll_rdiv = ((tmp >> 4) & 0x01) + 1; + + tmp = ov5640_read_reg(0x3108, &temp); + if (tmp < 0) + return tmp; + sclk_rdiv = sclk_rdiv_map[tmp & 0x03]; + + sysclk = ov5640_data.mclk / 10000 * Multiplier; + div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv; + if (!div) { + pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n", + __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); + return -EINVAL; + } + if (!sysclk) { + pr_err("%s:Error 0 clk, ov5640_data.mclk=%d, Multiplier=%d\n", + __func__, ov5640_data.mclk, Multiplier); + return -EINVAL; + } + sysclk /= div; + pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n", + __func__, sysclk, ov5640_data.mclk, Multiplier, + PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); return sysclk; } @@ -999,6 +2334,7 @@ int OV5640_get_light_freq(void) light_freq = 50; } else { /* 60Hz */ + light_freq = 60; } } return light_freq; @@ -1091,6 +2427,7 @@ static void ov5640_set_virtual_channel(int channel) ov5640_read_reg(0x4814, &channel_id); channel_id &= ~(3 << 6); ov5640_write_reg(0x4814, channel_id | (channel << 6)); + pr_info("%s: virtual channel=%d\n", __func__, channel); } /* download ov5640 settings to sensor through i2c */ @@ -1304,6 +2641,72 @@ err: return retval; } +static int ov5640_download_autofocus(void) +{ + u8 r; + int sval = ov5640_read_reg(0x3000, &r); + if (0 > sval) { + pr_err("%s(mipi):Error reading control reg\n", + __func__); + return sval; + } + r |= 0x20; + ov5640_write_reg(0x3000,r); + sval = ov5640_download_firmware( + ov5640_af_firmware, + ARRAY_SIZE(ov5640_af_firmware)); + if (0 > sval) { + pr_err("%s(mipi): Error downloading firmware\n", + __func__); + } else + pr_info("%s(mipi): Downloaded firmware successfully: %d\n", + __func__,sval); + r &= ~0x20; + ov5640_write_reg(0x3000,r); + + /* VCM control4 */ + ov5640_write_reg(0x3606,0x07); + return sval; +} + +static int trigger_auto_focus(void){ + ov5640_write_reg(CMD_ACK, 0x01); + ov5640_write_reg(CMD_MAIN, 0x03); + return 0; +} + +static int ioctl_send_command(struct v4l2_int_device *s, struct v4l2_send_command_control *vc) { + int ret = -1; + int retval1,retval2; + u8 loca_val=0; + + switch (vc->id) { + case 105: //step to specified position + pr_debug("Stepping to position: %d\n", vc->value0); + if(vc->value0 < 0 || vc->value0 > 255) + return ret; + loca_val = vc->value0; + ov5640_write_reg(CMD_PARA3, 0); + ov5640_write_reg(CMD_PARA4, loca_val); + retval1=ov5640_write_reg(CMD_ACK, 0x01); + retval2=ov5640_write_reg(CMD_MAIN, 0x1a); + if(retval1 != 0 || retval2 != 0) { + pr_err("%s:error stepping to 0x%02x: %d/%d\n", + __func__, vc->value0, retval1,retval2); + ret = -1; + } else { + pr_debug("step successful\n"); + ret = 0; + } + break; + default: + pr_err("%s:Unknown ctrl 0x%x\n", __func__, vc->id); + break; + } + + return ret; +} + static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, enum ov5640_mode mode, enum ov5640_mode orig_mode) { @@ -1362,6 +2765,15 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, if (retval < 0) goto err; + retval = ov5640_download_autofocus(); + if (retval < 0) { + pr_err("%s: error downloading autofocus firmware\n", + __func__); + goto err; + } + + trigger_auto_focus(); + pModeSetting = ov5640_setting_30fps_VGA_640_480; ArySize = ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480); retval = ov5640_download_firmware(pModeSetting, ArySize); @@ -1382,7 +2794,7 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, OV5640_set_AE_target(AE_Target); OV5640_get_light_freq(); OV5640_set_bandingfilter(); - ov5640_set_virtual_channel(ov5640_data.csi); + ov5640_set_virtual_channel(ov5640_data.csi | (ov5640_data.ipu_id << 1)); /* add delay to wait for sensor stable */ if (mode == ov5640_mode_QSXGA_2592_1944) { @@ -1399,37 +2811,33 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, msleep(msec_wait4stable); if (mipi_csi2_info) { - unsigned int i; - - i = 0; + unsigned int i = 0; /* wait for mipi sensor ready */ - mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); - while ((mipi_reg == 0x200) && (i < 10)) { + while (1) { mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); - i++; + if (mipi_reg != 0x200) + break; + if (i++ >= 20) { + pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg); + return -1; + } msleep(10); } - if (i >= 10) { - pr_err("mipi csi2 can not receive sensor clk!\n"); - return -1; - } - i = 0; - /* wait for mipi stable */ - mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); - while ((mipi_reg != 0x0) && (i < 10)) { + while (1) { mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); - i++; + if (!mipi_reg) + break; + if (i++ >= 20) { + pr_err("mipi csi2 can not receive data correctly!\n"); + return -1; + } msleep(10); } - if (i >= 10) { - pr_err("mipi csi2 can not reveive data correctly!\n"); - return -1; - } } err: return retval; @@ -1711,6 +3119,9 @@ static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) switch (vc->id) { case V4L2_CID_BRIGHTNESS: break; + case V4L2_CID_AUTO_FOCUS_START: + retval = trigger_auto_focus(); + break; case V4L2_CID_CONTRAST: break; case V4L2_CID_SATURATION: @@ -1915,6 +3326,8 @@ static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = { (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, {vidioc_int_g_chip_ident_num, (v4l2_int_ioctl_func *) ioctl_g_chip_ident}, + {vidioc_int_send_command_num, + (v4l2_int_ioctl_func *) ioctl_send_command}, }; static struct v4l2_int_slave ov5640_slave = { @@ -1924,7 +3337,7 @@ static struct v4l2_int_slave ov5640_slave = { static struct v4l2_int_device ov5640_int_device = { .module = THIS_MODULE, - .name = "ov5640", + .name = "ov5640_mipi", .type = v4l2_int_type_slave, .u = { .slave = &ov5640_slave, @@ -1940,9 +3353,12 @@ static struct v4l2_int_device ov5640_int_device = { static int ov5640_probe(struct i2c_client *client, const struct i2c_device_id *id) { + struct pwm_device *pwm; struct device *dev = &client->dev; int retval; u8 chip_id_high, chip_id_low; + struct regmap *gpr; + struct sensor_data *sensor = &ov5640_data; /* request power down pin */ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); @@ -1952,8 +3368,10 @@ static int ov5640_probe(struct i2c_client *client, } retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, "ov5640_mipi_pwdn"); - if (retval < 0) + if (retval < 0) { + dev_warn(dev, "request of pwn_gpio failed"); return retval; + } /* request reset pin */ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); @@ -1963,8 +3381,10 @@ static int ov5640_probe(struct i2c_client *client, } retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, "ov5640_mipi_reset"); - if (retval < 0) + if (retval < 0) { + dev_warn(dev, "request of ov5640_mipi_reset failed"); return retval; + } /* Set initial values for the sensor struct. */ memset(&ov5640_data, 0, sizeof(ov5640_data)); @@ -1990,6 +3410,13 @@ static int ov5640_probe(struct i2c_client *client, return retval; } + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + retval = of_property_read_u32(dev->of_node, "csi_id", &(ov5640_data.csi)); if (retval) { @@ -2010,6 +3437,13 @@ static int ov5640_probe(struct i2c_client *client, ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; ov5640_data.streamcap.timeperframe.numerator = 1; + pwm = pwm_get(dev, NULL); + if (!IS_ERR(pwm)) { + dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->period); + pwm_config(pwm, pwm->period >> 1, pwm->period); + pwm_enable(pwm); + } + ov5640_power_on(dev); ov5640_reset(); @@ -2029,12 +3463,31 @@ static int ov5640_probe(struct i2c_client *client, return -ENODEV; } + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + if (sensor->csi == sensor->ipu_id) { + int mask = sensor->csi ? (1 << 20) : (1 << 19); + + regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0); + } + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = sensor->csi ? (7 << 3) : (7 << 0); + int val = sensor->csi ? (3 << 3) : (0 << 0); + + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + ov5640_standby(1); ov5640_int_device.priv = &ov5640_data; retval = v4l2_int_device_register(&ov5640_int_device); - clk_disable_unprepare(ov5640_data.sensor_clk); +// clk_disable_unprepare(ov5640_data.sensor_clk); pr_info("camera ov5640_mipi is found\n"); return retval; diff --git a/drivers/media/platform/mxc/capture/ov5642.c b/drivers/media/platform/mxc/capture/ov5642.c index 04228655712a..8a5b688c47a0 100755..100644 --- a/drivers/media/platform/mxc/capture/ov5642.c +++ b/drivers/media/platform/mxc/capture/ov5642.c @@ -27,8 +27,11 @@ #include <linux/clk.h> #include <linux/of_device.h> #include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/fsl_devices.h> #include <media/v4l2-chip-ident.h> @@ -46,6 +49,50 @@ #define OV5642_XCLK_MIN 6000000 #define OV5642_XCLK_MAX 24000000 +/* OV5642 Camera Auto Focus Registers */ +#define REG_CMD_MAIN 0x3024 +#define REG_STA_FOCUS 0x3027 +#define REG_STA_ZONE 0x3026 +#define REG_CMD_TAG 0x3025 +#define REG_CMD_PARA3 0x5082 +#define REG_CMD_PARA2 0x5083 +#define REG_CMD_PARA1 0x5084 +#define REG_CMD_PARA0 0x5085 + + +/* OV5642 Auto Focus Commands and Responses */ +#define S_STARTUP 0xFA +#define S_FIRWARE 0xFF +#define S_STARTUP 0xFA +#define S_ERROR 0xFE +#define S_DRVICERR 0xEE +#define S_IDLE 0x00 +#define S_FOCUSING 0x01 +#define S_FOCUSED 0x02 +#define S_CAPTURE 0x12 +#define S_STEP 0x20 + +/*OV5642 AWB Registers*/ +#define REG_AWB_MANUAL 0x3406 +#define REG_AWB_R_GAIN_HIGH 0x3400 +#define REG_AWB_R_GAIN_LOW 0x3401 +#define REG_AWB_G_GAIN_HIGH 0x3402 +#define REG_AWB_G_GAIN_LOW 0x3403 +#define REG_AWB_B_GAIN_HIGH 0x3404 +#define REG_AWB_B_GAIN_LOW 0x3405 + +#define CMD_ENABLE_OVERLAY 0x01 +#define CMD_DISABLE_OVERLAY 0x02 +#define CMD_SINGLE_FOCUS_MODE 0x03 +#define CMD_CONST_FOCUS_MODE 0x04 +#define CMD_STEP_FOCUS_MODE 0x05 +#define CMD_PAUSE 0x06 +#define CMD_IDLE_MODE 0x08 +#define CMD_SET_ZONE_MODE 0x10 +#define CMD_UPDATE_ZONE_MODE 0x12 +#define CMD_MOTOR_MODE 0x20 +#define CMD_SCAN_MODE 0x30 + #define OV5642_CHIP_ID_HIGH_BYTE 0x300A #define OV5642_CHIP_ID_LOW_BYTE 0x300B @@ -295,6 +342,1848 @@ static struct reg_value ov5642_initial_setting[] = { {0x302b, 0x00, 0, 300}, }; +static struct reg_value ov5642_af_firmware[] = { + {0x3000, 0x20, 0, 0},{0x8000, 0x02, 0, 0},{0x8001, 0x00, 0, 0}, + {0x8002, 0x06, 0, 0},{0x8003, 0x02, 0, 0},{0x8004, 0x0b, 0, 0}, + {0x8005, 0x44, 0, 0},{0x8006, 0x78, 0, 0},{0x8007, 0x7f, 0, 0}, + {0x8008, 0xe4, 0, 0},{0x8009, 0xf6, 0, 0},{0x800a, 0xd8, 0, 0}, + {0x800b, 0xfd, 0, 0},{0x800c, 0x75, 0, 0},{0x800d, 0x81, 0, 0}, + {0x800e, 0x7d, 0, 0},{0x800f, 0x02, 0, 0},{0x8010, 0x13, 0, 0}, + {0x8011, 0xb6, 0, 0},{0x8012, 0x00, 0, 0},{0x8013, 0x02, 0, 0}, + {0x8014, 0x12, 0, 0},{0x8015, 0xe1, 0, 0},{0x8016, 0xe0, 0, 0}, + {0x8017, 0xf5, 0, 0},{0x8018, 0x71, 0, 0},{0x8019, 0xa3, 0, 0}, + {0x801a, 0xe0, 0, 0},{0x801b, 0xf5, 0, 0},{0x801c, 0x72, 0, 0}, + {0x801d, 0xae, 0, 0},{0x801e, 0x69, 0, 0},{0x801f, 0xe4, 0, 0}, + {0x8020, 0x85, 0, 0},{0x8021, 0x6a, 0, 0},{0x8022, 0x55, 0, 0}, + {0x8023, 0x8e, 0, 0},{0x8024, 0x54, 0, 0},{0x8025, 0xf5, 0, 0}, + {0x8026, 0x53, 0, 0},{0x8027, 0xf5, 0, 0},{0x8028, 0x52, 0, 0}, + {0x8029, 0xab, 0, 0},{0x802a, 0x55, 0, 0},{0x802b, 0xaa, 0, 0}, + {0x802c, 0x54, 0, 0},{0x802d, 0xa9, 0, 0},{0x802e, 0x53, 0, 0}, + {0x802f, 0xa8, 0, 0},{0x8030, 0x52, 0, 0},{0x8031, 0xaf, 0, 0}, + {0x8032, 0x2c, 0, 0},{0x8033, 0xfc, 0, 0},{0x8034, 0xfd, 0, 0}, + {0x8035, 0xfe, 0, 0},{0x8036, 0x12, 0, 0},{0x8037, 0x08, 0, 0}, + {0x8038, 0x7f, 0, 0},{0x8039, 0x8f, 0, 0},{0x803a, 0x55, 0, 0}, + {0x803b, 0x8e, 0, 0},{0x803c, 0x54, 0, 0},{0x803d, 0x8d, 0, 0}, + {0x803e, 0x53, 0, 0},{0x803f, 0x8c, 0, 0},{0x8040, 0x52, 0, 0}, + {0x8041, 0xaf, 0, 0},{0x8042, 0x55, 0, 0},{0x8043, 0xae, 0, 0}, + {0x8044, 0x54, 0, 0},{0x8045, 0xad, 0, 0},{0x8046, 0x53, 0, 0}, + {0x8047, 0xac, 0, 0},{0x8048, 0x52, 0, 0},{0x8049, 0x8f, 0, 0}, + {0x804a, 0x2b, 0, 0},{0x804b, 0x8e, 0, 0},{0x804c, 0x2a, 0, 0}, + {0x804d, 0x8d, 0, 0},{0x804e, 0x29, 0, 0},{0x804f, 0x8c, 0, 0}, + {0x8050, 0x28, 0, 0},{0x8051, 0xae, 0, 0},{0x8052, 0x6b, 0, 0}, + {0x8053, 0xe4, 0, 0},{0x8054, 0x85, 0, 0},{0x8055, 0x6c, 0, 0}, + {0x8056, 0x55, 0, 0},{0x8057, 0x8e, 0, 0},{0x8058, 0x54, 0, 0}, + {0x8059, 0xf5, 0, 0},{0x805a, 0x53, 0, 0},{0x805b, 0xf5, 0, 0}, + {0x805c, 0x52, 0, 0},{0x805d, 0xab, 0, 0},{0x805e, 0x55, 0, 0}, + {0x805f, 0xaa, 0, 0},{0x8060, 0x54, 0, 0},{0x8061, 0xa9, 0, 0}, + {0x8062, 0x53, 0, 0},{0x8063, 0xa8, 0, 0},{0x8064, 0x52, 0, 0}, + {0x8065, 0xaf, 0, 0},{0x8066, 0x2d, 0, 0},{0x8067, 0xfc, 0, 0}, + {0x8068, 0xfd, 0, 0},{0x8069, 0xfe, 0, 0},{0x806a, 0x12, 0, 0}, + {0x806b, 0x08, 0, 0},{0x806c, 0x7f, 0, 0},{0x806d, 0x8f, 0, 0}, + {0x806e, 0x55, 0, 0},{0x806f, 0x8e, 0, 0},{0x8070, 0x54, 0, 0}, + {0x8071, 0x8d, 0, 0},{0x8072, 0x53, 0, 0},{0x8073, 0x8c, 0, 0}, + {0x8074, 0x52, 0, 0},{0x8075, 0xe5, 0, 0},{0x8076, 0x2b, 0, 0}, + {0x8077, 0x25, 0, 0},{0x8078, 0x55, 0, 0},{0x8079, 0xf5, 0, 0}, + {0x807a, 0x2b, 0, 0},{0x807b, 0xe5, 0, 0},{0x807c, 0x2a, 0, 0}, + {0x807d, 0x35, 0, 0},{0x807e, 0x54, 0, 0},{0x807f, 0xf5, 0, 0}, + {0x8080, 0x2a, 0, 0},{0x8081, 0xe5, 0, 0},{0x8082, 0x29, 0, 0}, + {0x8083, 0x35, 0, 0},{0x8084, 0x53, 0, 0},{0x8085, 0xf5, 0, 0}, + {0x8086, 0x29, 0, 0},{0x8087, 0xe5, 0, 0},{0x8088, 0x28, 0, 0}, + {0x8089, 0x35, 0, 0},{0x808a, 0x52, 0, 0},{0x808b, 0xf5, 0, 0}, + {0x808c, 0x28, 0, 0},{0x808d, 0xae, 0, 0},{0x808e, 0x6d, 0, 0}, + {0x808f, 0xe4, 0, 0},{0x8090, 0x85, 0, 0},{0x8091, 0x6e, 0, 0}, + {0x8092, 0x55, 0, 0},{0x8093, 0x8e, 0, 0},{0x8094, 0x54, 0, 0}, + {0x8095, 0xf5, 0, 0},{0x8096, 0x53, 0, 0},{0x8097, 0xf5, 0, 0}, + {0x8098, 0x52, 0, 0},{0x8099, 0xab, 0, 0},{0x809a, 0x55, 0, 0}, + {0x809b, 0xaa, 0, 0},{0x809c, 0x54, 0, 0},{0x809d, 0xa9, 0, 0}, + {0x809e, 0x53, 0, 0},{0x809f, 0xa8, 0, 0},{0x80a0, 0x52, 0, 0}, + {0x80a1, 0xaf, 0, 0},{0x80a2, 0x2e, 0, 0},{0x80a3, 0xfc, 0, 0}, + {0x80a4, 0xfd, 0, 0},{0x80a5, 0xfe, 0, 0},{0x80a6, 0x12, 0, 0}, + {0x80a7, 0x08, 0, 0},{0x80a8, 0x7f, 0, 0},{0x80a9, 0x8f, 0, 0}, + {0x80aa, 0x55, 0, 0},{0x80ab, 0x8e, 0, 0},{0x80ac, 0x54, 0, 0}, + {0x80ad, 0x8d, 0, 0},{0x80ae, 0x53, 0, 0},{0x80af, 0x8c, 0, 0}, + {0x80b0, 0x52, 0, 0},{0x80b1, 0xe5, 0, 0},{0x80b2, 0x2b, 0, 0}, + {0x80b3, 0x25, 0, 0},{0x80b4, 0x55, 0, 0},{0x80b5, 0xf5, 0, 0}, + {0x80b6, 0x2b, 0, 0},{0x80b7, 0xe5, 0, 0},{0x80b8, 0x2a, 0, 0}, + {0x80b9, 0x35, 0, 0},{0x80ba, 0x54, 0, 0},{0x80bb, 0xf5, 0, 0}, + {0x80bc, 0x2a, 0, 0},{0x80bd, 0xe5, 0, 0},{0x80be, 0x29, 0, 0}, + {0x80bf, 0x35, 0, 0},{0x80c0, 0x53, 0, 0},{0x80c1, 0xf5, 0, 0}, + {0x80c2, 0x29, 0, 0},{0x80c3, 0xe5, 0, 0},{0x80c4, 0x28, 0, 0}, + {0x80c5, 0x35, 0, 0},{0x80c6, 0x52, 0, 0},{0x80c7, 0xf5, 0, 0}, + {0x80c8, 0x28, 0, 0},{0x80c9, 0xae, 0, 0},{0x80ca, 0x6f, 0, 0}, + {0x80cb, 0xe4, 0, 0},{0x80cc, 0x85, 0, 0},{0x80cd, 0x70, 0, 0}, + {0x80ce, 0x55, 0, 0},{0x80cf, 0x8e, 0, 0},{0x80d0, 0x54, 0, 0}, + {0x80d1, 0xf5, 0, 0},{0x80d2, 0x53, 0, 0},{0x80d3, 0xf5, 0, 0}, + {0x80d4, 0x52, 0, 0},{0x80d5, 0xab, 0, 0},{0x80d6, 0x55, 0, 0}, + {0x80d7, 0xaa, 0, 0},{0x80d8, 0x54, 0, 0},{0x80d9, 0xa9, 0, 0}, + {0x80da, 0x53, 0, 0},{0x80db, 0xa8, 0, 0},{0x80dc, 0x52, 0, 0}, + {0x80dd, 0xaf, 0, 0},{0x80de, 0x2f, 0, 0},{0x80df, 0xfc, 0, 0}, + {0x80e0, 0xfd, 0, 0},{0x80e1, 0xfe, 0, 0},{0x80e2, 0x12, 0, 0}, + {0x80e3, 0x08, 0, 0},{0x80e4, 0x7f, 0, 0},{0x80e5, 0x8f, 0, 0}, + {0x80e6, 0x55, 0, 0},{0x80e7, 0x8e, 0, 0},{0x80e8, 0x54, 0, 0}, + {0x80e9, 0x8d, 0, 0},{0x80ea, 0x53, 0, 0},{0x80eb, 0x8c, 0, 0}, + {0x80ec, 0x52, 0, 0},{0x80ed, 0xe5, 0, 0},{0x80ee, 0x2b, 0, 0}, + {0x80ef, 0x25, 0, 0},{0x80f0, 0x55, 0, 0},{0x80f1, 0xf5, 0, 0}, + {0x80f2, 0x2b, 0, 0},{0x80f3, 0xe5, 0, 0},{0x80f4, 0x2a, 0, 0}, + {0x80f5, 0x35, 0, 0},{0x80f6, 0x54, 0, 0},{0x80f7, 0xf5, 0, 0}, + {0x80f8, 0x2a, 0, 0},{0x80f9, 0xe5, 0, 0},{0x80fa, 0x29, 0, 0}, + {0x80fb, 0x35, 0, 0},{0x80fc, 0x53, 0, 0},{0x80fd, 0xf5, 0, 0}, + {0x80fe, 0x29, 0, 0},{0x80ff, 0xe5, 0, 0},{0x8100, 0x28, 0, 0}, + {0x8101, 0x35, 0, 0},{0x8102, 0x52, 0, 0},{0x8103, 0xf5, 0, 0}, + {0x8104, 0x28, 0, 0},{0x8105, 0xae, 0, 0},{0x8106, 0x71, 0, 0}, + {0x8107, 0xe4, 0, 0},{0x8108, 0x85, 0, 0},{0x8109, 0x72, 0, 0}, + {0x810a, 0x55, 0, 0},{0x810b, 0x8e, 0, 0},{0x810c, 0x54, 0, 0}, + {0x810d, 0xf5, 0, 0},{0x810e, 0x53, 0, 0},{0x810f, 0xf5, 0, 0}, + {0x8110, 0x52, 0, 0},{0x8111, 0xab, 0, 0},{0x8112, 0x55, 0, 0}, + {0x8113, 0xaa, 0, 0},{0x8114, 0x54, 0, 0},{0x8115, 0xa9, 0, 0}, + {0x8116, 0x53, 0, 0},{0x8117, 0xa8, 0, 0},{0x8118, 0x52, 0, 0}, + {0x8119, 0xaf, 0, 0},{0x811a, 0x30, 0, 0},{0x811b, 0xfc, 0, 0}, + {0x811c, 0xfd, 0, 0},{0x811d, 0xfe, 0, 0},{0x811e, 0x12, 0, 0}, + {0x811f, 0x08, 0, 0},{0x8120, 0x7f, 0, 0},{0x8121, 0x8f, 0, 0}, + {0x8122, 0x55, 0, 0},{0x8123, 0x8e, 0, 0},{0x8124, 0x54, 0, 0}, + {0x8125, 0x8d, 0, 0},{0x8126, 0x53, 0, 0},{0x8127, 0x8c, 0, 0}, + {0x8128, 0x52, 0, 0},{0x8129, 0xe5, 0, 0},{0x812a, 0x2b, 0, 0}, + {0x812b, 0x25, 0, 0},{0x812c, 0x55, 0, 0},{0x812d, 0xf5, 0, 0}, + {0x812e, 0x2b, 0, 0},{0x812f, 0xe5, 0, 0},{0x8130, 0x2a, 0, 0}, + {0x8131, 0x35, 0, 0},{0x8132, 0x54, 0, 0},{0x8133, 0xf5, 0, 0}, + {0x8134, 0x2a, 0, 0},{0x8135, 0xe5, 0, 0},{0x8136, 0x29, 0, 0}, + {0x8137, 0x35, 0, 0},{0x8138, 0x53, 0, 0},{0x8139, 0xf5, 0, 0}, + {0x813a, 0x29, 0, 0},{0x813b, 0xe5, 0, 0},{0x813c, 0x28, 0, 0}, + {0x813d, 0x35, 0, 0},{0x813e, 0x52, 0, 0},{0x813f, 0xf5, 0, 0}, + {0x8140, 0x28, 0, 0},{0x8141, 0x22, 0, 0},{0x8142, 0xab, 0, 0}, + {0x8143, 0x0d, 0, 0},{0x8144, 0xaa, 0, 0},{0x8145, 0x0c, 0, 0}, + {0x8146, 0xa9, 0, 0},{0x8147, 0x0b, 0, 0},{0x8148, 0xa8, 0, 0}, + {0x8149, 0x0a, 0, 0},{0x814a, 0xfc, 0, 0},{0x814b, 0xfd, 0, 0}, + {0x814c, 0xfe, 0, 0},{0x814d, 0x12, 0, 0},{0x814e, 0x08, 0, 0}, + {0x814f, 0x7f, 0, 0},{0x8150, 0x8f, 0, 0},{0x8151, 0x0d, 0, 0}, + {0x8152, 0x8e, 0, 0},{0x8153, 0x0c, 0, 0},{0x8154, 0x8d, 0, 0}, + {0x8155, 0x0b, 0, 0},{0x8156, 0x8c, 0, 0},{0x8157, 0x0a, 0, 0}, + {0x8158, 0x7b, 0, 0},{0x8159, 0x40, 0, 0},{0x815a, 0xe4, 0, 0}, + {0x815b, 0xfa, 0, 0},{0x815c, 0xf9, 0, 0},{0x815d, 0xf8, 0, 0}, + {0x815e, 0x12, 0, 0},{0x815f, 0x09, 0, 0},{0x8160, 0x0a, 0, 0}, + {0x8161, 0x8f, 0, 0},{0x8162, 0x0d, 0, 0},{0x8163, 0x8e, 0, 0}, + {0x8164, 0x0c, 0, 0},{0x8165, 0x8d, 0, 0},{0x8166, 0x0b, 0, 0}, + {0x8167, 0x8c, 0, 0},{0x8168, 0x0a, 0, 0},{0x8169, 0x22, 0, 0}, + {0x816a, 0xd2, 0, 0},{0x816b, 0x29, 0, 0},{0x816c, 0x90, 0, 0}, + {0x816d, 0x30, 0, 0},{0x816e, 0x1b, 0, 0},{0x816f, 0xe5, 0, 0}, + {0x8170, 0x25, 0, 0},{0x8171, 0xf0, 0, 0},{0x8172, 0x22, 0, 0}, + {0x8173, 0xfe, 0, 0},{0x8174, 0xe4, 0, 0},{0x8175, 0xfc, 0, 0}, + {0x8176, 0xfd, 0, 0},{0x8177, 0xe5, 0, 0},{0x8178, 0x3f, 0, 0}, + {0x8179, 0x2f, 0, 0},{0x817a, 0xf5, 0, 0},{0x817b, 0x3f, 0, 0}, + {0x817c, 0xe5, 0, 0},{0x817d, 0x3e, 0, 0},{0x817e, 0x3e, 0, 0}, + {0x817f, 0xf5, 0, 0},{0x8180, 0x3e, 0, 0},{0x8181, 0xed, 0, 0}, + {0x8182, 0x35, 0, 0},{0x8183, 0x3d, 0, 0},{0x8184, 0xf5, 0, 0}, + {0x8185, 0x3d, 0, 0},{0x8186, 0xec, 0, 0},{0x8187, 0x35, 0, 0}, + {0x8188, 0x3c, 0, 0},{0x8189, 0xf5, 0, 0},{0x818a, 0x3c, 0, 0}, + {0x818b, 0xaf, 0, 0},{0x818c, 0x3f, 0, 0},{0x818d, 0xae, 0, 0}, + {0x818e, 0x3e, 0, 0},{0x818f, 0xfc, 0, 0},{0x8190, 0xad, 0, 0}, + {0x8191, 0x3d, 0, 0},{0x8192, 0x78, 0, 0},{0x8193, 0x08, 0, 0}, + {0x8194, 0x12, 0, 0},{0x8195, 0x09, 0, 0},{0x8196, 0xaf, 0, 0}, + {0x8197, 0x8f, 0, 0},{0x8198, 0x3f, 0, 0},{0x8199, 0x8e, 0, 0}, + {0x819a, 0x3e, 0, 0},{0x819b, 0x8d, 0, 0},{0x819c, 0x3d, 0, 0}, + {0x819d, 0x8c, 0, 0},{0x819e, 0x3c, 0, 0},{0x819f, 0x22, 0, 0}, + {0x81a0, 0xe5, 0, 0},{0x81a1, 0x49, 0, 0},{0x81a2, 0x25, 0, 0}, + {0x81a3, 0x7b, 0, 0},{0x81a4, 0xf5, 0, 0},{0x81a5, 0x82, 0, 0}, + {0x81a6, 0xe4, 0, 0},{0x81a7, 0x35, 0, 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0},{0x94fe, 0x93, 0, 0}, + {0x94ff, 0xf5, 0, 0},{0x9500, 0x32, 0, 0},{0x9501, 0xc2, 0, 0}, + {0x9502, 0x38, 0, 0},{0x9503, 0x22, 0, 0},{0x9504, 0xe4, 0, 0}, + {0x9505, 0xff, 0, 0},{0x9506, 0xef, 0, 0},{0x9507, 0x25, 0, 0}, + {0x9508, 0xe0, 0, 0},{0x9509, 0x24, 0, 0},{0x950a, 0x56, 0, 0}, + {0x950b, 0xf8, 0, 0},{0x950c, 0xe4, 0, 0},{0x950d, 0xf6, 0, 0}, + {0x950e, 0x08, 0, 0},{0x950f, 0xf6, 0, 0},{0x9510, 0x0f, 0, 0}, + {0x9511, 0xbf, 0, 0},{0x9512, 0x07, 0, 0},{0x9513, 0xf2, 0, 0}, + {0x9514, 0x53, 0, 0},{0x9515, 0x24, 0, 0},{0x9516, 0x80, 0, 0}, + {0x9517, 0x22, 0, 0},{0x9518, 0xc2, 0, 0},{0x9519, 0x03, 0, 0}, + {0x951a, 0xd2, 0, 0},{0x951b, 0x04, 0, 0},{0x951c, 0x12, 0, 0}, + {0x951d, 0x02, 0, 0},{0x951e, 0xa5, 0, 0},{0x951f, 0xc2, 0, 0}, + {0x9520, 0x3c, 0, 0},{0x9521, 0x12, 0, 0},{0x9522, 0x0f, 0, 0}, + {0x9523, 0xb0, 0, 0},{0x9524, 0xc2, 0, 0},{0x9525, 0x3c, 0, 0}, + {0x9526, 0x12, 0, 0},{0x9527, 0x11, 0, 0},{0x9528, 0x1a, 0, 0}, + {0x9529, 0xd2, 0, 0},{0x952a, 0x34, 0, 0},{0x952b, 0x22, 0, 0}, + {0x952c, 0xe5, 0, 0},{0x952d, 0x7c, 0, 0},{0x952e, 0xc3, 0, 0}, + {0x952f, 0x95, 0, 0},{0x9530, 0x7b, 0, 0},{0x9531, 0x40, 0, 0}, + {0x9532, 0x01, 0, 0},{0x9533, 0x22, 0, 0},{0x9534, 0xe5, 0, 0}, + {0x9535, 0x7c, 0, 0},{0x9536, 0x04, 0, 0},{0x9537, 0xf5, 0, 0}, + {0x9538, 0x0c, 0, 0},{0x9539, 0x12, 0, 0},{0x953a, 0x0f, 0, 0}, + {0x953b, 0x11, 0, 0},{0x953c, 0x22, 0, 0},{0x953d, 0xe5, 0, 0}, + {0x953e, 0x7c, 0, 0},{0x953f, 0x70, 0, 0},{0x9540, 0x02, 0, 0}, + {0x9541, 0xc3, 0, 0},{0x9542, 0x22, 0, 0},{0x9543, 0xe5, 0, 0}, + {0x9544, 0x7c, 0, 0},{0x9545, 0x14, 0, 0},{0x9546, 0xf5, 0, 0}, + {0x9547, 0x0c, 0, 0},{0x9548, 0x12, 0, 0},{0x9549, 0x0f, 0, 0}, + {0x954a, 0x11, 0, 0},{0x954b, 0x22, 0, 0},{0x954c, 0xe5, 0, 0}, + {0x954d, 0x7d, 0, 0},{0x954e, 0xb4, 0, 0},{0x954f, 0x01, 0, 0}, + {0x9550, 0x09, 0, 0},{0x9551, 0x12, 0, 0},{0x9552, 0x14, 0, 0}, + {0x9553, 0xef, 0, 0},{0x9554, 0xe4, 0, 0},{0x9555, 0xf5, 0, 0}, + {0x9556, 0x0c, 0, 0},{0x9557, 0x12, 0, 0},{0x9558, 0x0f, 0, 0}, + {0x9559, 0x11, 0, 0},{0x955a, 0x22, 0, 0},{0x955b, 0xe5, 0, 0}, + {0x955c, 0x7d, 0, 0},{0x955d, 0x24, 0, 0},{0x955e, 0xfe, 0, 0}, + {0x955f, 0x60, 0, 0},{0x9560, 0x06, 0, 0},{0x9561, 0x04, 0, 0}, + {0x9562, 0x70, 0, 0},{0x9563, 0x05, 0, 0},{0x9564, 0xd2, 0, 0}, + {0x9565, 0x37, 0, 0},{0x9566, 0x22, 0, 0},{0x9567, 0xc2, 0, 0}, + {0x9568, 0x37, 0, 0},{0x9569, 0x22, 0, 0},{0x956a, 0xe5, 0, 0}, + {0x956b, 0x31, 0, 0},{0x956c, 0xd3, 0, 0},{0x956d, 0x94, 0, 0}, + {0x956e, 0x00, 0, 0},{0x956f, 0x40, 0, 0},{0x9570, 0x03, 0, 0}, + {0x9571, 0x15, 0, 0},{0x9572, 0x31, 0, 0},{0x9573, 0x22, 0, 0}, + {0x9574, 0x12, 0, 0},{0x9575, 0x15, 0, 0},{0x9576, 0x18, 0, 0}, + {0x9577, 0x22, 0, 0},{0x9578, 0x12, 0, 0},{0x9579, 0x14, 0, 0}, + {0x957a, 0xef, 0, 0},{0x957b, 0xe4, 0, 0},{0x957c, 0xf5, 0, 0}, + {0x957d, 0x0c, 0, 0},{0x957e, 0x12, 0, 0},{0x957f, 0x0f, 0, 0}, + {0x9580, 0x11, 0, 0},{0x9581, 0x22, 0, 0},{0x3024, 0x00, 0, 0}, + {0x3025, 0x00, 0, 0},{0x5082, 0x00, 0, 0},{0x5083, 0x00, 0, 0}, + {0x5084, 0x00, 0, 0},{0x5085, 0x00, 0, 0},{0x3026, 0x00, 0, 0}, + {0x3027, 0xFF, 0, 0},{0x3000, 0x00, 0, 0}, +}; + static struct reg_value ov5642_setting_15fps_QCIF_176_144[] = { {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, @@ -3028,8 +4917,36 @@ static void ov5642_standby(s32 enable) msleep(2); } +static s32 update_device_addr(struct sensor_data *sensor) +{ + int ret; + u8 buf[4]; + unsigned reg = 0x3100; + unsigned default_addr = 0x3c; + struct i2c_msg msg; + + if (sensor->i2c_client->addr == default_addr) + return 0; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + buf[2] = sensor->i2c_client->addr << 1; + msg.addr = default_addr; + msg.flags = 0; + msg.len = 3; + msg.buf = buf; + + + ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1); + if (ret < 0) + pr_err("%s: ov5642 ret=%d\n", __func__, ret); + return ret; +} + static void ov5642_reset(void) { + mxc_camera_common_lock(); + /* camera reset */ gpio_set_value(rst_gpio, 1); @@ -3044,7 +4961,9 @@ static void ov5642_reset(void) msleep(1); gpio_set_value(rst_gpio, 1); - msleep(5); + msleep(20); + update_device_addr(&ov5642_data); + mxc_camera_common_unlock(); gpio_set_value(pwn_gpio, 1); } @@ -3113,18 +5032,29 @@ static int ov5642_power_on(struct device *dev) static s32 ov5642_write_reg(u16 reg, u8 val) { + int ret; u8 au8Buf[3] = {0}; au8Buf[0] = reg >> 8; au8Buf[1] = reg & 0xff; au8Buf[2] = val; - if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) { - pr_err("%s:write reg error:reg=%x,val=%x\n", - __func__, reg, val); - return -1; + if ((reg == 0x3008) && (val & 0x80)) { + mxc_camera_common_lock(); + + ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3); + update_device_addr(&ov5642_data); + + mxc_camera_common_unlock(); + } else { + ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3); } + if (ret < 0) { + pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n", + __func__, reg, val, ret); + return ret; + } return 0; } @@ -3153,6 +5083,51 @@ static s32 ov5642_read_reg(u16 reg, u8 *val) return u8RdVal; } +static int ov5642_set_idle_mode(void) { + register u16 RegAddr = 0; + u8 ReadVal = 0; + u8 WriteVal = 0; + int retval = 0; + int lc = 0; + + ReadVal = -1; + RegAddr = REG_STA_FOCUS; + retval = ov5642_read_reg(RegAddr, &ReadVal); + if (retval < 0) { + pr_err("%s, read reg 0x%x failed\n", __FUNCTION__, RegAddr); + } + + for (lc = 0; (lc < 100) && (ReadVal != S_IDLE); ++lc) { + WriteVal = CMD_IDLE_MODE; + RegAddr = REG_CMD_MAIN; + retval = ov5642_write_reg(RegAddr, WriteVal); + if (retval < 0) { + pr_err("%s, write reg 0x%x failed\n", __FUNCTION__, RegAddr); + } + + mdelay(1); + + ReadVal = -1; + RegAddr = REG_STA_FOCUS; + retval = ov5642_read_reg(RegAddr, &ReadVal); + if (retval < 0) { + pr_err("%s, read reg 0x%x failed\n", __FUNCTION__, RegAddr); + } + } + + if (ReadVal != S_IDLE) + retval = -1; + else + retval = 0; + return retval; +} + +static int ov5642_config_auto_focus(void){ + ov5642_write_reg(REG_CMD_TAG, 0x01); + ov5642_write_reg(REG_CMD_MAIN, 0x10); + return 0; +} + static int ov5642_set_rot_mode(struct reg_value *rot_mode) { s32 i = 0; @@ -3194,6 +5169,29 @@ static int ov5642_set_rot_mode(struct reg_value *rot_mode) err: return retval; } + +static int ov5642_auto_focus_start(void) { + register u16 RegAddr = 0; + u8 RegVal = 0; + int retval = 0; + + retval = ov5642_set_idle_mode(); + ov5642_config_auto_focus(); + + if (retval > -1) { + RegVal = CMD_SINGLE_FOCUS_MODE; + RegAddr = REG_CMD_MAIN; + retval = ov5642_write_reg(RegAddr, RegVal); + if (retval < 0) { + pr_err("%s, write reg 0x%x failed\n", __FUNCTION__, RegAddr); + } + } else { + pr_err("Could not get camera into idle mode. Abandoning focus attempt"); + } + + return retval; +} + static int ov5642_init_mode(enum ov5642_frame_rate frame_rate, enum ov5642_mode mode); static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate, @@ -3737,6 +5735,12 @@ static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) switch (vc->id) { case V4L2_CID_BRIGHTNESS: break; + case V4L2_CID_AUTO_FOCUS_START: + retval = ov5642_auto_focus_start(); + break; + case V4L2_CID_AUTO_FOCUS_STOP: + retval = ov5642_set_idle_mode(); + break; case V4L2_CID_CONTRAST: break; case V4L2_CID_SATURATION: @@ -3815,6 +5819,66 @@ static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) return retval; } +static int ioctl_send_command(struct v4l2_int_device *s, struct v4l2_send_command_control *vc) { + int ret = -1; + int retval1,retval2; + u8 loca_val=0; + + ret = ov5642_set_idle_mode(); + if (0 != ret) + pr_err("error %d setting idle mode\n", ret); + ov5642_config_auto_focus(); + switch (vc->id) { + case 101: //step to near + pr_debug("Stepping to near object\n"); + retval1=ov5642_write_reg(REG_CMD_TAG, 0x01); + retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); + if(retval1 == 0 && retval2 == 0) + ret = 0; + break; + case 102: //step to far + pr_debug("Stepping to far object\n"); + retval1=ov5642_write_reg(REG_CMD_TAG, 0x02); + retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); + if(retval1 == 0 && retval2 == 0) + ret = 0; + break; + + case 103: //step to furthest + pr_debug("Stepping to furthest object\n"); + retval1=ov5642_write_reg(REG_CMD_TAG, 0x03); + retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); + if(retval1 == 0 && retval2 == 0) + ret = 0; + break; + + case 104: //step to nearest + pr_debug("Stepping to nearest object\n"); + retval1=ov5642_write_reg(REG_CMD_TAG, 0x04); + retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); + if(retval1 == 0 && retval2 == 0) + ret = 0; + break; + + + case 105: //step to specified position + pr_debug("Stepping to position: %d\n", vc->value0); + if(vc->value0 < 0 || vc->value0 > 255) + return ret; + loca_val = vc->value0; + retval1=ov5642_write_reg(REG_CMD_TAG, 0x10); + retval2=ov5642_write_reg(REG_CMD_PARA0, loca_val); + ret=ov5642_write_reg(REG_CMD_MAIN, 0x05); + if(retval1 != 0 && retval2 != 0 && ret != 0) + ret = -1; + break; + default: + break; + } + + return ret; +} + /*! * ioctl_enum_framesizes - V4L2 sensor interface handler for * VIDIOC_ENUM_FRAMESIZES ioctl @@ -4055,6 +6119,8 @@ static struct v4l2_int_ioctl_desc ov5642_ioctl_desc[] = { (v4l2_int_ioctl_func *)ioctl_enum_frameintervals }, { vidioc_int_g_chip_ident_num, (v4l2_int_ioctl_func *)ioctl_g_chip_ident }, + {vidioc_int_send_command_num, + (v4l2_int_ioctl_func *) ioctl_send_command}, }; static struct v4l2_int_slave ov5642_slave = { @@ -4084,6 +6150,10 @@ static int ov5642_probe(struct i2c_client *client, struct device *dev = &client->dev; int retval; u8 chip_id_high, chip_id_low; + struct regmap *gpr; + struct reg_value *firmware_regs; + int i; + struct sensor_data *sensor = &ov5642_data; /* ov5642 pinctrl */ pinctrl = devm_pinctrl_get_select_default(dev); @@ -4138,6 +6208,13 @@ static int ov5642_probe(struct i2c_client *client, return retval; } + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + retval = of_property_read_u32(dev->of_node, "csi_id", &(ov5642_data.csi)); if (retval) { @@ -4177,9 +6254,40 @@ static int ov5642_probe(struct i2c_client *client, return -ENODEV; } + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + int mask = ov5642_data.csi ? (1 << 20) : (1 << 19); + + if (sensor->csi != sensor->ipu_id) { + pr_warning("%s: csi_id != ipu_id\n", __func__); + return -ENODEV; + } + regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask); + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = ov5642_data.csi ? (7 << 3) : (7 << 0); + int val = ov5642_data.csi ? (4 << 3) : (4 << 0); + + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + ov5642_standby(1); ov5642_int_device.priv = &ov5642_data; + + pr_info("Upload Auto-focus firmware"); + firmware_regs = ov5642_af_firmware; + for (i = 0; i < ARRAY_SIZE(ov5642_af_firmware); ++i, ++firmware_regs) { + retval = ov5642_write_reg(firmware_regs->u16RegAddr, + firmware_regs->u8Val); + if (retval < 0) + break; + } + retval = v4l2_int_device_register(&ov5642_int_device); clk_disable_unprepare(ov5642_data.sensor_clk); diff --git a/drivers/media/platform/mxc/capture/tc358743_h2c.c b/drivers/media/platform/mxc/capture/tc358743_h2c.c new file mode 100644 index 000000000000..8d2e8f7f1ab8 --- /dev/null +++ b/drivers/media/platform/mxc/capture/tc358743_h2c.c @@ -0,0 +1,3401 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * Modifyed by: Edison Fernández <edison.fernandez@ridgerun.com> + * Added support to use it with Nitrogen6x + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/ctype.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/clk.h> +#include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/of_gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/fsl_devices.h> +#include <linux/mutex.h> +#include <linux/mipi_csi2.h> +#include <linux/pwm.h> +#include <media/v4l2-chip-ident.h> +#include <media/v4l2-int-device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/jack.h> +#include <sound/soc-dapm.h> +#include <asm/mach-types.h> +//#include <mach/audmux.h> +#include <linux/slab.h> +#include "mxc_v4l2_capture.h" + +#define CODEC_CLOCK 16500000 +/* SSI clock sources */ +#define IMX_SSP_SYS_CLK 0 + + +#define TC358743_VOLTAGE_ANALOG 2800000 +#define TC358743_VOLTAGE_DIGITAL_CORE 1500000 +#define TC358743_VOLTAGE_DIGITAL_IO 1800000 + +#define MIN_FPS 30 +#define MAX_FPS 60 +#define DEFAULT_FPS 60 + +#define TC358743_XCLK_MIN 27000000 +#define TC358743_XCLK_MAX 42000000 + +#define TC358743_CHIP_ID_HIGH_BYTE 0x0 +#define TC358743_CHIP_ID_LOW_BYTE 0x0 +#define TC3587430_HDMI_DETECT 0x0f //0x10 + +#define TC_VOLTAGE_ANALOG 2800000 +#define TC_VOLTAGE_DIGITAL_CORE 1500000 +#define TC_VOLTAGE_DIGITAL_IO 1800000 + +enum tc358743_mode { + tc358743_mode_INIT, /*only for sensor init*/ + tc358743_mode_INIT1, /*only for sensor init*/ + tc358743_mode_480P_720_480, + tc358743_mode_720P_60_1280_720, + tc358743_mode_480P_640_480, + tc358743_mode_1080P_1920_1080, + tc358743_mode_INIT2, /*only for sensor init*/ + tc358743_mode_INIT3, /*only for sensor init*/ + tc358743_mode_INIT4, /*only for sensor init*/ + tc358743_mode_INIT5, /*only for sensor init*/ + tc358743_mode_INIT6, /*only for sensor init*/ + tc358743_mode_720P_1280_720, + tc358743_mode_MAX , +}; + +enum tc358743_frame_rate { + tc358743_60_fps, + tc358743_30_fps, + tc358743_max_fps +}; + +struct reg_value { + u16 u16RegAddr; + u32 u32Val; + u32 u32Mask; + u8 u8Length; + u32 u32Delay_ms; +}; + +struct tc358743_mode_info { + enum tc358743_mode mode; + u32 width; + u32 height; + u32 vformat; + u32 fps; + u32 lanes; + u32 freq; + struct reg_value *init_data_ptr; + u32 init_data_size; + __u32 flags; +}; + +static struct delayed_work det_work; +static struct sensor_data tc358743_data; +static int pwn_gpio, rst_gpio; +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; + +static u16 hpd_active = 1; + +#define DET_WORK_TIMEOUT_DEFAULT 100 +#define DET_WORK_TIMEOUT_DEFERRED 2000 +#define MAX_BOUNCE 5 + +static DEFINE_MUTEX(access_lock); +static int det_work_disable = 0; +static int det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; +static u32 hdmi_mode = 0, lock = 0, bounce = 0, fps = 0, audio = 2; + +static int tc358743_init_mode(enum tc358743_frame_rate frame_rate, + enum tc358743_mode mode); + +static int tc358743_toggle_hpd(int active); + +static void tc_standby(s32 enable) +{ + if (gpio_is_valid(pwn_gpio)) + gpio_set_value(pwn_gpio, enable ? 1 : 0); + pr_debug("tc_standby: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio); + msleep(2); +} + +static void tc_reset(void) +{ + /* camera reset */ + gpio_set_value(rst_gpio, 1); + + /* camera power dowmn */ + if (gpio_is_valid(pwn_gpio)) { + gpio_set_value(pwn_gpio, 1); + msleep(5); + + gpio_set_value(pwn_gpio, 0); + } + msleep(5); + + gpio_set_value(rst_gpio, 0); + msleep(1); + + gpio_set_value(rst_gpio, 1); + msleep(20); + + if (gpio_is_valid(pwn_gpio)) + gpio_set_value(pwn_gpio, 1); +} + +static int tc_power_on(struct device *dev) +{ + int ret = 0; + + io_regulator = devm_regulator_get(dev, "DOVDD"); + if (!IS_ERR(io_regulator)) { + regulator_set_voltage(io_regulator, + TC_VOLTAGE_DIGITAL_IO, + TC_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(io_regulator); + if (ret) { + pr_err("%s:io set voltage error\n", __func__); + return ret; + } else { + dev_dbg(dev, + "%s:io set voltage ok\n", __func__); + } + } else { + pr_err("%s: cannot get io voltage error\n", __func__); + io_regulator = NULL; + } + + core_regulator = devm_regulator_get(dev, "DVDD"); + if (!IS_ERR(core_regulator)) { + regulator_set_voltage(core_regulator, + TC_VOLTAGE_DIGITAL_CORE, + TC_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(core_regulator); + if (ret) { + pr_err("%s:core set voltage error\n", __func__); + return ret; + } else { + dev_dbg(dev, + "%s:core set voltage ok\n", __func__); + } + } else { + core_regulator = NULL; + pr_err("%s: cannot get core voltage error\n", __func__); + } + + analog_regulator = devm_regulator_get(dev, "AVDD"); + if (!IS_ERR(analog_regulator)) { + regulator_set_voltage(analog_regulator, + TC_VOLTAGE_ANALOG, + TC_VOLTAGE_ANALOG); + ret = regulator_enable(analog_regulator); + if (ret) { + pr_err("%s:analog set voltage error\n", + __func__); + return ret; + } else { + dev_dbg(dev, + "%s:analog set voltage ok\n", __func__); + } + } else { + analog_regulator = NULL; + pr_err("%s: cannot get analog voltage error\n", __func__); + } + + return ret; +} + +static void det_work_enable(int i) +{ + mutex_lock(&access_lock); + if (i) { + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); + det_work_disable = 0; + } else { + det_work_disable = 1; + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + } + mutex_unlock(&access_lock); + pr_debug("%s: %d %d\n", __func__, det_work_disable, det_work_timeout); +} + +static u8 cHDMIEDID[256] = { + /* FIXME! This is the edid that my ASUS HDMI monitor returns */ + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x69, 0xf3, 0x24, 0xd6, 0x12, 0x00, 0x00, + 0x16, 0x16, 0x01, 0x03, 0x80, 0x34, 0x1d, 0x78, 0x2a, 0xc7, 0x20, 0xa4, 0x55, 0x49, 0x99, 0x27, + 0x13, 0x50, 0x54, 0xbf, 0xef, 0x00, 0x71, 0x4f, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, + 0xd1, 0xc0, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a, 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c, + 0x45, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x36, 0x4c, + 0x4d, 0x54, 0x46, 0x30, 0x30, 0x34, 0x38, 0x32, 0x32, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x37, + 0x4b, 0x1e, 0x55, 0x10, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, + 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x48, 0x32, 0x34, 0x32, 0x48, 0x0a, 0x20, 0x01, 0x78, + 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, + 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00, + 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0x09, 0x25, + 0x21, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00, + 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x01, 0x1d, 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28, + 0x55, 0x40, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20, + 0x0c, 0x40, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, +}; + +/*! + * Maintains the information on the current state of the sesor. + */ + +static struct reg_value tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000040, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000402d, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000e00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000801, 0x00000000, 4, 0}, + {0x021c, 0x00000001, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004800, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa300be82, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (26 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x0000008c, 0x00000000, 1, 0}, + {0x8541, 0x0000000a, 0x00000000, 1, 0}, + {0x8630, 0x000000b0, 0x00000000, 1, 0}, + {0x8631, 0x0000001e, 0x00000000, 1, 0}, + {0x8632, 0x00000004, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, +// {0x8544, 0x00000000, 0x00000000, 1, 1000}, +// {0x8544, 0x00000001, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// Video settings + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, +// {0x8651, 0x00000003, 0x00000000, 1, 0}, // Inverted LRCK polarity - (Sony) format + {0x8652, 0x00000002, 0x00000000, 1, 0}, // Left-justified I2S (Phillips) format +// {0x8652, 0x00000000, 0x00000000, 1, 0}, // Right-justified (Sony) format + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, + }; + +static struct reg_value tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0014, 0x0000ffff, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x00004062, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000d00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000701, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa300be86, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (26 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000000, 0x00000000, 1, 0}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion +// {0x8574, 0x00000000, 0x00000000, 1, 0}, + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405c, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000e00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000801, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000006, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x00000007, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a2, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000a00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x00000580, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405c, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000e00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000801, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000006, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001F, 0x00000000, 4, 0}, //{0x0234, 0x00000007, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, //{0x0500, 0xa30080a2, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000a00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x00000300, 0x00000000, 2, 0}, //{0x7092, 0x00000580, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x00004050, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001800, 0x00000000, 4, 0}, + {0x0214, 0x00000002, 0x00000000, 4, 0}, + {0x0218, 0x00001102, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000007, 0x00000000, 4, 0}, + {0x022c, 0x00000001, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000800, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x0020, 0x0000406f, 0x00000000, 2, 100}, + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x00000540, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x000080c7, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, + {0x0214, 0x00000003, 0x00000000, 4, 0}, + {0x0218, 0x00001402, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004a00, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000a00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x000006b8, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x000080c7, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, + {0x0214, 0x00000003, 0x00000000, 4, 0}, + {0x0218, 0x00001402, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004a00, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// 1920x1023 colorbar + {0x000a, 0x00000f00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 1023 lines + {0x7090, 0x000003fe, 0x00000000, 2, 0}, + {0x7092, 0x000004d8, 0x00000000, 2, 0}, + {0x7094, 0x0000002d, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x00008073, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, +// {0x014c, 0x00000000, 0x00000000, 4, 0}, +// {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001200, 0x00000000, 4, 0}, + {0x0214, 0x00000002, 0x00000000, 4, 0}, + {0x0218, 0x00000b02, 0x00000000, 4, 0}, + {0x021c, 0x00000001, 0x00000000, 4, 0}, + {0x0220, 0x00000103, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000000, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA3008082, 0x00000000, 4, 0}, +// 640x480 colorbar + {0x000a, 0x00000500, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 80 pixel black - repeate 80 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)}, +// 80 pixel blue - repeate 40 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel red - repeate 40 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel pink - repeate 40 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel green - repeate 40 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel light blue - repeate 40 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel yellow - repeate 40 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel white - repeate 40 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)}, +// 480 lines + {0x7090, 0x000001df, 0x00000000, 2, 0}, + {0x7092, 0x00000898, 0x00000000, 2, 0}, + {0x7094, 0x00000285, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000404F, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001800, 0x00000000, 4, 0}, + {0x0214, 0x00000002, 0x00000000, 4, 0}, + {0x0218, 0x00001102, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000007, 0x00000000, 4, 0}, + {0x022c, 0x00000001, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA30080A2, 0x00000000, 4, 0}, +// 640x480 colorbar + {0x000a, 0x00000500, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 80 pixel black - repeate 80 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)}, +// 80 pixel blue - repeate 40 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel red - repeate 40 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel pink - repeate 40 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel green - repeate 40 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel light blue - repeate 40 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel yellow - repeate 40 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel white - repeate 40 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)}, +// 480 lines + {0x7090, 0x000001df, 0x00000000, 2, 0}, + {0x7092, 0x00000700, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +//480p RGB2YUV442 +static struct reg_value tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000040, 0x00000000, 2, 0}, +// {0x000a, 0x000005a0, 0x00000000, 2, 0}, +// {0x0010, 0x0000001e, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405c, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000d00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000701, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA30080A2, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (26 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000000, 0x00000000, 1, 100}, +// {0x8544, 0x00000001, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, + }; + +//480p RGB2YUV442 +static struct reg_value tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000040, 0x00000000, 2, 0}, + {0x000a, 0x000005a0, 0x00000000, 2, 0}, +// {0x0010, 0x0000001e, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405b, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000d00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000701, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA30080A2, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (27 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000000, 0x00000000, 1, 100}, +// {0x8544, 0x00000001, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, + }; + +static struct reg_value tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100},//0}, + {0x0002, 0x00000000, 0x00000000, 2, 1000},//0}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x000080c7, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, + {0x0214, 0x00000003, 0x00000000, 4, 0}, + {0x0218, 0x00001402, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004a00, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (27 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000010, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion + {0x8571, 0x00000002, 0x00000000, 1, 0}, + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8576, 0x00000060, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, // IR control resister + {0x0004, 0x00000084, 0x00000000, 2, 0}, // Internal Generated output pattern,Do not send InfoFrame data out to CSI2,Audio output to CSI2-TX i/f,I2C address index increments on every data byte transfer, disable audio and video TX buffers + {0x0002, 0x00000f00, 0x00000000, 2, 100},//0}, // Reset devices and set normal operatio (not sleep) + {0x0002, 0x00000000, 0x00000000, 2, 1000},//0}, // Clear reset bits + {0x0006, 0x000001f8, 0x00000000, 2, 0}, // FIFO level = 1f8 = 504 + {0x0014, 0x00000000, 0x00000000, 2, 0}, // Clear interrupt status bits + {0x0016, 0x000005ff, 0x00000000, 2, 0}, // Mask audio mute, CSI-TX, and the other interrups +// Program CSI Tx PLL + //{0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200 + {0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200 + {0x0022, 0x00000213, 0x00000000, 2, 0}, // HSCK frequency = 500MHz – 1GHz HSCK frequency, Loop bandwidth setting = 50% of maximum loop bandwidth (default), REFCLK toggling –> normal operation, REFCLK stops -> no oscillation, Bypass clock = normal operation, clocks switched off (output LOW), PLL Reset normal operation, PLL Enable = PLL on +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, // Clock Lane DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x0144, 0x00000000, 0x00000000, 4, 0}, // Data Lane 0 DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x0148, 0x00000000, 0x00000000, 4, 0}, // Data Lane 1 DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x014c, 0x00000000, 0x00000000, 4, 0}, // Data Lane 2 DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x0150, 0x00000000, 0x00000000, 4, 0}, // Data Lane 3 DPHY Control: Bypass Lane Enable from PPI Layer enable. +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, // LINEINITCNT: Line Initialization Wait Counter = 0x1e00 = 7680 + {0x0214, 0x00000003, 0x00000000, 4, 0}, // LPTXTIMECNT: SYSLPTX Timing Generation Counter = 3 + {0x0218, 0x00001402, 0x00000000, 4, 0}, // TCLK_HEADERCNT: TCLK_ZERO Counter = 0x14 = 20, TCLK_PREPARE Counter = 0x02 = 2 + {0x021c, 0x00000000, 0x00000000, 4, 0}, // TCLK_TRAILCNT: TCLK_TRAIL Counter = 0 + {0x0220, 0x00000003, 0x00000000, 4, 0}, // THS_HEADERCNT: THS_ZERO Counter = 0, THS_PREPARE Counter = 3 + {0x0224, 0x00004a00, 0x00000000, 4, 0}, // TWAKEUP: TWAKEUP Counter = 0x4a00 = 18944 + {0x0228, 0x00000008, 0x00000000, 4, 0}, // TCLK_POSTCNT: TCLK_POST Counter = 8 + {0x022c, 0x00000002, 0x00000000, 4, 0}, // THS_TRAILCNT: THS_TRAIL Counter = 2 + {0x0234, 0x0000001f, 0x00000000, 4, 0}, // HSTXVREGEN: Enable voltage regulators for lanes and clk + {0x0238, 0x00000001, 0x00000000, 4, 0}, // TXOPTIONCNTRL: Set Continuous Clock Mode + {0x0204, 0x00000001, 0x00000000, 4, 0}, // PPI STARTCNTRL: start PPI function + {0x0518, 0x00000001, 0x00000000, 4, 0}, // CSI_START: start + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, // CSI Configuration Register: set register 0x040C with data 0x80a6 (CSI MOde, Disables the HTX_TO timer, High-Speed data transfer is performed to Tx, DSCClk Stays in HS mode when Data Lane goes to LP, 4 Data Lanes,The EOT packet is automatically granted at the end of HS transfer then is transmitted) +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, // SYSTEM INTERRUPT: clear DDC power change detection interrupt + {0x8512, 0x000000fe, 0x00000000, 1, 0}, // SYS INTERRUPT MASK: DDC power change detection interrupt not masked + {0x8514, 0x00000000, 0x00000000, 1, 0}, // PACKET INTERRUPT MASK: unmask all + {0x8515, 0x00000000, 0x00000000, 1, 0}, // CBIT INTERRUPT MASK: unmask all + {0x8516, 0x00000000, 0x00000000, 1, 0}, // AUDIO INTERRUPT MASK: unmask all +// HDMI Audio RefClk (27 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, // PHY CONTROL0: 27MHz, DDC5V detection operation. + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, // SYS FREQ0 Register: 27MHz + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, // Audio FS Lock Detect Control: for 27MHz + {0x8670, 0x00000001, 0x00000000, 1, 0}, // AUDIO PLL Setting: For REFCLK = 27MHz +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, // + {0x8536, 0x00000040, 0x00000000, 1, 0}, // + {0x853f, 0x0000000a, 0x00000000, 1, 0}, // +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, // DDC CONTROL: DDC_ACK output terminal H active, DDC5V_active detect delay 200ms + {0x8544, 0x00000010, 0x00000000, 1, 100}, // HPD Control Register: HOTPLUG output ON/OFF control mode = DDC5V detection interlock + {0x8545, 0x00000031, 0x00000000, 1, 0}, // ANA CONTROL: PLL charge pump setting for Audio = normal, DAC/PLL power ON/OFF setting for Audio = ON + {0x8546, 0x0000002d, 0x00000000, 1, 0}, // AVMUTE CONTROL: AVM_CTL = 0x2d +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, // EDID MODE REGISTER: nternal EDID-RAM & DDC2B mode + {0x85cb, 0x00000001, 0x00000000, 1, 0}, // EDID Length REGISTER 2: EDID data size stored in RAM (upper address bits) = 0x1 (Size = 0x100 = 256) +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, // + {0x8560, 0x00000024, 0x00000000, 1, 0}, // HDCP MODE: HDCP automatic reset when DVI⇔HDMI switched = on, HDCP Line Rekey timing switch = 7clk mode (Data island delay ON), Bcaps[5] KSVINFO_READY(0x8840[5]) auto clear mode = Auto clear using AKSV write + {0x8563, 0x00000011, 0x00000000, 1, 0}, // + {0x8564, 0x0000000f, 0x00000000, 1, 0}, // +// RGB --> YUV Conversion + {0x8571, 0x00000002, 0x00000000, 1, 0}, // + {0x8573, 0x000000c1, 0x00000000, 1, 0}, // VOUT SET2 REGISTER: 422 fixed output, Video Output 422 conversion mode selection 000: During 444 input, 3tap filter; during 422 input, simple decimation, Enable RGB888 to YUV422 Conversion (Fixed Color output) + {0x8574, 0x00000008, 0x00000000, 1, 0}, // VOUT SET3 REGISTER (VOUT_SET3): Follow register bit 0x8573[7] setting + {0x8576, 0x00000060, 0x00000000, 1, 0}, // VOUT_COLOR: Output Color = 601 YCbCr Limited, Input Pixel Repetition judgment = automatic, Input Pixel Repetition HOST setting = no repetition +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, // PACKET INTERRUPT MODE: all enable + {0x870b, 0x0000002c, 0x00000000, 1, 0}, // NO PACKET LIMIT: NO_ACP_LIMIT = 0x2, NO_AVI_LIMIT = 0xC + {0x870c, 0x00000053, 0x00000000, 1, 0}, // When VS receive interrupt is detected, VS storage register automatic clear, When ACP receive interrupt is detected, ACP storage register automatic clear, When AVI receive interrupt occurs, judge input video signal with RGB and no Repetition, When AVI receive interrupt is detected, AVI storage register automatic clear. + {0x870d, 0x00000001, 0x00000000, 1, 0}, // ERROR PACKET LIMIT: Packet continuing receive error occurrence detection threshold = 1 + {0x870e, 0x00000030, 0x00000000, 1, 0}, // NO PACKET LIMIT: + {0x9007, 0x00000010, 0x00000000, 1, 0}, // + {0x854a, 0x00000001, 0x00000000, 1, 0}, // Initialization completed flag +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, // Configuration Control Register: Power Island Normal, I2S/TDM clock are free running, Enable 2 Audio channels, Audio channel number Auto detect by HW, I2S/TDM Data no delay, Select YCbCr422 8-bit (HDMI YCbCr422 12-bit data format), Send InfoFrame data out to CSI2, Audio output to I2S i/f (valid for 2 channel only), I2C address index increments on every data byte transfer, Audio and Video tx buffres enable. +}; + +/* list of image formats supported by TCM825X sensor */ +static const struct v4l2_fmtdesc tc358743_formats[] = { + { + .description = "RGB888 (RGB24)", + .pixelformat = V4L2_PIX_FMT_RGB24, /* 24 RGB-8-8-8 */ + .flags = MIPI_DT_RGB888 // 0x24 + }, + { + .description = "RAW12 (Y/CbCr 4:2:0)", + .pixelformat = V4L2_PIX_FMT_UYVY, /* 12 Y/CbCr 4:2:0 */ + .flags = MIPI_DT_RAW12 // 0x2c + }, + { + .description = "YUV 4:2:2 8-bit", + .pixelformat = V4L2_PIX_FMT_YUYV, /* 8 8-bit color */ + .flags = MIPI_DT_YUV422 // 0x1e /* UYVY... */ + }, +}; + + +static struct tc358743_mode_info tc358743_mode_info_data[2][tc358743_mode_MAX] = { + [0][tc358743_mode_720P_60_1280_720] = + {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133, + tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_1080P_1920_1080] = + {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0x0b, 4, 300, + tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT1] = + {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125, + tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT2] = + {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125, + tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT] = + {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108, + tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT4] = + {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174, + tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT3] = + {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_720P_1280_720] = + {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125, + tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_480P_720_480] = + {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_480P_640_480] = + {tc358743_mode_480P_640_480, 640, 480, 6, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_INIT5] = + {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT6] = + {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_720P_60_1280_720] = + {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133, + tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_1080P_1920_1080] = + {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0xa, 4, 300, + tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT1] = + {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125, + tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT2] = + {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125, + tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + + [1][tc358743_mode_INIT] = + {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108, + tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT4] = + {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174, + tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT3] = + {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_720P_1280_720] = + {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125, + tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz), + MIPI_DT_YUV422, + }, + [1][tc358743_mode_480P_720_480] = + {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_480P_640_480] = + {tc358743_mode_480P_640_480, 640, 480, 1, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz), + MIPI_DT_YUV422, + }, + [1][tc358743_mode_INIT5] = + {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT6] = + {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz), + MIPI_DT_YUV422 + }, +}; + +static int tc358743_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int tc358743_remove(struct i2c_client *client); + +static s32 tc358743_read_reg(u16 reg, u32 *val); +static s32 tc358743_write_reg(u16 reg, u32 val, int len); + +static const struct i2c_device_id tc358743_id[] = { + {"tc358743_mipi", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, tc358743_id); + +static struct i2c_driver tc358743_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "tc358743_mipi", + }, + .probe = tc358743_probe, + .remove = tc358743_remove, + .id_table = tc358743_id, +}; + +struct _reg_size +{ + u16 startaddr, endaddr; + int size; +} +tc358743_read_reg_size [] = +{ + {0x0000, 0x005a, 2}, + {0x0140, 0x0150, 4}, + {0x0204, 0x0238, 4}, + {0x040c, 0x0418, 4}, + {0x044c, 0x0454, 4}, + {0x0500, 0x0518, 4}, + {0x0600, 0x06cc, 4}, + {0x7000, 0x7100, 2}, + {0x8500, 0x8bff, 1}, + {0x8c00, 0x8fff, 4}, + {0x9000, 0x90ff, 1}, + {0x9100, 0x92ff, 1}, + {0, 0, 0}, +}; + +static s32 tc358743_write_reg(u16 reg, u32 val, int len) +{ + int i = 0; + u32 data = val; + u8 au8Buf[6] = {0}; + int size = 0; + + while (0 != tc358743_read_reg_size[i].startaddr || + 0 != tc358743_read_reg_size[i].endaddr || + 0 != tc358743_read_reg_size[i].size) { + if (tc358743_read_reg_size[i].startaddr <= reg + && tc358743_read_reg_size[i].endaddr >= reg) { + size = tc358743_read_reg_size[i].size; + break; + } + i++; + } + if (!size) { + pr_err("%s:write reg error:reg=%x is not found\n",__func__, reg); + return -1; + } + if (size == 3) { + size = 2; + } else if (size != len) { + pr_err("%s:write reg len error:reg=%x %d instead of %d\n", + __func__, reg, len, size); + return 0; + } + + while (len > 0) { + i = 0; + au8Buf[i++] = (reg >> 8) & 0xff; + au8Buf[i++] = reg & 0xff; + while (size-- > 0) + { + au8Buf[i++] = (u8)data; + data >>= 8; + } + + if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, val); + return -1; + } + len -= (u8)size; + reg += (u16)size; + } + + return 0; +} + +static s32 tc358743_read_reg(u16 reg, u32 *val) +{ + u8 au8RegBuf[2] = {0}; + u32 u32RdVal = 0; + int i=0; + int size = 0; + + while (0 != tc358743_read_reg_size[i].startaddr || + 0 != tc358743_read_reg_size[i].endaddr || + 0 != tc358743_read_reg_size[i].size) { + if (tc358743_read_reg_size[i].startaddr <= reg && + tc358743_read_reg_size[i].endaddr >= reg) { + size = tc358743_read_reg_size[i].size; + break; + } + i++; + } + if (!size) + return -1; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (2 != i2c_master_send(tc358743_data.i2c_client, au8RegBuf, 2)) { + pr_err("%s:read reg error:reg=%x\n", + __func__, reg); + return -1; + } + + if (size /*of(u32RdVal)*/ != i2c_master_recv(tc358743_data.i2c_client, (char *)&u32RdVal, size /*of(u32RdVal)*/)) { + pr_err("%s:read reg error:reg=%x,val=%x\n", + __func__, reg, u32RdVal); + return -1; + } + *val = u32RdVal; + return size; +} + +static int tc358743_write_edid(u8 *edid, int len) +{ + int i = 0, off = 0; + u8 au8Buf[8+2] = {0}; + int size = 0; + u16 reg; + + reg = 0x8C00; + off = 0; + size = ARRAY_SIZE(au8Buf)-2; + pr_debug("Write EDID: %d (%d)\n", len, size); + while (len > 0) { + i = 0; + au8Buf[i++] = (reg >> 8) & 0xff; + au8Buf[i++] = reg & 0xff; + while (i < ARRAY_SIZE(au8Buf)) { + au8Buf[i++] = edid[off++]; + } + + if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, off); + return -1; + } + len -= (u8)size; + reg += (u16)size; + } + pr_debug("Activate EDID\n"); + tc358743_write_reg(0x85c7, 0x01, 1); + tc358743_write_reg(0x85ca, 0x00, 1); + tc358743_write_reg(0x85cb, 0x01, 1); + return 0; +} + +static int tc358743_reset(struct sensor_data *sensor) +{ + u32 tgt_fps; /* target frames per secound */ + enum tc358743_frame_rate frame_rate = tc358743_60_fps; + int ret = -1; + + det_work_enable(0); + while (ret) { + tc_standby(1); + mdelay(100); + tc_standby(0); + mdelay(1000); + + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) + frame_rate = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate = tc358743_30_fps; + + pr_debug("%s: capture mode: %d extended mode: %d fps: %d\n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode, tgt_fps); + + ret = tc358743_init_mode(frame_rate, + sensor->streamcap.capturemode); + if (ret) + pr_err("%s: Fail to init tc35874! - retry\n", __func__); + } + det_work_enable(1); + return ret; +} + +void mipi_csi2_swreset(struct mipi_csi2_info *info); +#include "../../../../mxc/mipi/mxc_mipi_csi2.h" +static int tc358743_init_mode(enum tc358743_frame_rate frame_rate, + enum tc358743_mode mode) +{ + + struct reg_value *pModeSetting = NULL; + s32 i = 0; + s32 iModeSettingArySize = 0; + register u32 RepeateLines = 0; + register int RepeateTimes = 0; + register u32 Delay_ms = 0; + register u16 RegAddr = 0; + register u32 Mask = 0; + register u32 Val = 0; + u8 Length; + u32 RegVal = 0; + int retval = 0; + void *mipi_csi2_info; + u32 mipi_reg; + u32 mipi_reg_test[10]; + + pr_debug("%s rate: %d mode: %d\n", __func__, frame_rate, mode); + if ((mode > tc358743_mode_MAX || mode < 0) + && (mode != tc358743_mode_INIT)) { + pr_debug("%s Wrong tc358743 mode detected! %d. Set mode 0\n", __func__, mode); + mode = 0; + } + + mipi_csi2_info = mipi_csi2_get_info(); + pr_debug("%s rate: %d mode: %d, info %p\n", __func__, frame_rate, mode, mipi_csi2_info); + + /* initial mipi dphy */ + tc358743_toggle_hpd(!hpd_active); + if (mipi_csi2_info) { + pr_debug("%s: mipi_csi2_info:\n" + "mipi_en: %d\n" + "ipu_id: %d\n" + "csi_id: %d\n" + "v_channel: %d\n" + "lanes: %d\n" + "datatype: %d\n" + "dphy_clk: %p\n" + "pixel_clk: %p\n" + "mipi_csi2_base:%p\n" + "pdev: %p\n" + , __func__, + ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_en, + ((struct mipi_csi2_info *)mipi_csi2_info)->ipu_id, + ((struct mipi_csi2_info *)mipi_csi2_info)->csi_id, + ((struct mipi_csi2_info *)mipi_csi2_info)->v_channel, + ((struct mipi_csi2_info *)mipi_csi2_info)->lanes, + ((struct mipi_csi2_info *)mipi_csi2_info)->datatype, + ((struct mipi_csi2_info *)mipi_csi2_info)->dphy_clk, + ((struct mipi_csi2_info *)mipi_csi2_info)->pixel_clk, + ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_csi2_base, + ((struct mipi_csi2_info *)mipi_csi2_info)->pdev + ); + if (!mipi_csi2_get_status(mipi_csi2_info)) + mipi_csi2_enable(mipi_csi2_info); + + if (mipi_csi2_get_status(mipi_csi2_info)) { + int ifmt; + if (tc358743_mode_info_data[frame_rate][mode].lanes != 0) { + pr_debug("%s Change lanes: from %d to %d\n", __func__, ((struct mipi_csi2_info *)mipi_csi2_info)->lanes, tc358743_mode_info_data[frame_rate][mode].lanes); + ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes; + ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes; + } + pr_debug("Now Using %d lanes\n",mipi_csi2_set_lanes(mipi_csi2_info)); + + /*Only reset MIPI CSI2 HW at sensor initialize*/ + if (!hdmi_mode) // is this during reset + mipi_csi2_reset(mipi_csi2_info); + + + pr_debug("%s format: %x\n", __func__, tc358743_data.pix.pixelformat); + for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) + if (tc358743_mode_info_data[frame_rate][mode].flags == tc358743_formats[ifmt].flags) { + tc358743_data.pix.pixelformat = tc358743_formats[ifmt].pixelformat; + pr_debug("%s: %s (%x, %x)\n", __func__, tc358743_formats[ifmt].description, tc358743_data.pix.pixelformat, tc358743_formats[ifmt].flags); + mipi_csi2_set_datatype(mipi_csi2_info, tc358743_formats[ifmt].flags); + break; + } + if (ifmt >= ARRAY_SIZE(tc358743_formats)) { + pr_err("currently this sensor format (0x%x) can not be supported!\n", tc358743_data.pix.pixelformat); + return -1; + } + } else { + pr_err("Can not enable mipi csi2 driver!\n"); + return -1; + } + } else { + pr_err("Fail to get mipi_csi2_info!\n"); + return -1; + } + + { + pModeSetting = + tc358743_mode_info_data[frame_rate][mode].init_data_ptr; + iModeSettingArySize = + tc358743_mode_info_data[frame_rate][mode].init_data_size; + + tc358743_data.pix.width = + tc358743_mode_info_data[frame_rate][mode].width; + tc358743_data.pix.height = + tc358743_mode_info_data[frame_rate][mode].height; + pr_debug("%s: Set %d regs from %p for frs %d mode %d with width %d height %d\n", __func__, + iModeSettingArySize, + pModeSetting, + frame_rate, + mode, + tc358743_data.pix.width, + tc358743_data.pix.height); + for (i = 0; i < iModeSettingArySize; ++i) { + pModeSetting = tc358743_mode_info_data[frame_rate][mode].init_data_ptr + i; + + Delay_ms = pModeSetting->u32Delay_ms & (0xffff); + RegAddr = pModeSetting->u16RegAddr; + Val = pModeSetting->u32Val; + Mask = pModeSetting->u32Mask; + Length = pModeSetting->u8Length; + if (Mask) { + retval = tc358743_read_reg(RegAddr, &RegVal); + if (retval < 0) + break; + + RegVal &= ~(u8)Mask; + Val &= Mask; + Val |= RegVal; + } + + retval = tc358743_write_reg(RegAddr, Val, Length); + if (retval < 0) + break; + + if (Delay_ms) + msleep(Delay_ms); + + if (0 != ((pModeSetting->u32Delay_ms>>16) & (0xff))) { + if (!RepeateTimes) { + RepeateTimes = (pModeSetting->u32Delay_ms>>16) & (0xff); + RepeateLines = (pModeSetting->u32Delay_ms>>24) & (0xff); + } + if (--RepeateTimes > 0) { + i -= RepeateLines; + } + } + } + if (retval < 0) { + pr_err("%s: Fail to write REGS to tc35874!\n", __func__); + goto err; + } + } + if (!hdmi_mode) // is this during reset + if ((retval = tc358743_write_edid(cHDMIEDID, ARRAY_SIZE(cHDMIEDID)))) + pr_err("%s: Fail to write EDID to tc35874!\n", __func__); + + tc358743_toggle_hpd(hpd_active); + if (mipi_csi2_info) { + unsigned int i = 0; + + /* wait for mipi sensor ready */ + mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); + while ((mipi_reg == 0x200) && (i < 10)) { + mipi_reg_test[i] = mipi_reg; + mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); + i++; + msleep(10); + } + + if (i >= 10) { + pr_err("mipi csi2 can not receive sensor clk!\n"); + return -1; + } + + { + int j; + for (j = 0; j < i; j++) + { + pr_debug("%d mipi csi2 dphy status %x\n", j, mipi_reg_test[j]); + } + } + + i = 0; + + /* wait for mipi stable */ + mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); + while ((mipi_reg != 0x0) && (i < 10)) { + mipi_reg_test[i] = mipi_reg; + mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); + i++; + msleep(10); + } + + if (i >= 10) { + pr_err("mipi csi2 can not reveive data correctly!\n"); + return -1; + } + + { + int j; + for (j = 0; j < i; j++) { + pr_debug("%d mipi csi2 err1 %x\n", j, mipi_reg_test[j]); + } + } + } +err: + return (retval>0)?0:retval; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("%s\n", __func__); + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = TC358743_XCLK_MIN; //tc358743_data.mclk; + pr_debug("%s: clock_curr=mclk=%d\n", __func__, tc358743_data.mclk); + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = TC358743_XCLK_MIN; + p->u.bt656.clock_max = TC358743_XCLK_MAX; + p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ + + return 0; +} + +/*! + * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor_data *sensor = s->priv; + + pr_debug("%s: %d\n", __func__, on); + if (on && !sensor->on) { + if (io_regulator) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (core_regulator) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (gpo_regulator) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (analog_regulator) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + /* Make sure power on */ + tc_standby(0); + + } else if (!on && sensor->on) { + if (analog_regulator) + regulator_disable(analog_regulator); + if (core_regulator) + regulator_disable(core_regulator); + if (io_regulator) + regulator_disable(io_regulator); + if (gpo_regulator) + regulator_disable(gpo_regulator); + if (!hdmi_mode) + tc358743_reset(sensor); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor_data *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("%s type: %x\n", __func__, a->type); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + cparm->extendedmode = sensor->streamcap.extendedmode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + det_work_enable(1); + pr_debug("%s done %d\n", __func__, ret); + return ret; +} + +static int tc358743_toggle_hpd(int active) +{ + int ret = 0; + if (active) { + ret += tc358743_write_reg(0x8544, 0x00, 1); + mdelay(500); + ret += tc358743_write_reg(0x8544, 0x10, 1); + } else { + ret += tc358743_write_reg(0x8544, 0x10, 1); + mdelay(500); + ret += tc358743_write_reg(0x8544, 0x00, 1); + } + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor_data *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum tc358743_frame_rate frame_rate = tc358743_60_fps, frame_rate_now = tc358743_60_fps; + int ret = 0; + + pr_debug("%s\n", __func__); + det_work_enable(0); + /* Make sure power on */ + tc_standby(0); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + /* Actual frame rate we use */ + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps == 60) + frame_rate = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate = tc358743_30_fps; + else { + pr_err(" The camera frame rate is not supported!\n"); + ret = -EINVAL; + break; + } + + if ((u32)a->parm.capture.capturemode > tc358743_mode_MAX) { + a->parm.capture.capturemode = 0; + pr_debug("%s: Forse extended mode: %d \n", __func__,(u32)a->parm.capture.capturemode); + } + + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) + frame_rate_now = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate_now = tc358743_30_fps; + + if (frame_rate_now != frame_rate || + sensor->streamcap.capturemode != (u32)a->parm.capture.capturemode || + sensor->streamcap.extendedmode != (u32)a->parm.capture.extendedmode) { + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + sensor->streamcap.extendedmode = + (u32)a->parm.capture.extendedmode; + + pr_debug("%s: capture mode: %d extended mode: %d \n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode); + + ret = tc358743_init_mode(frame_rate, + sensor->streamcap.capturemode); + } else { + pr_debug("%s: Keep current settings\n", __func__); + } + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + if (ret) + det_work_enable(1); + return ret; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + pr_debug("%s\n", __func__); + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = tc358743_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = tc358743_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = tc358743_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = tc358743_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = tc358743_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = tc358743_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = tc358743_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In tc358743:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + break; + case V4L2_CID_CONTRAST: + break; + case V4L2_CID_SATURATION: + break; + case V4L2_CID_HUE: + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + break; + case V4L2_CID_DO_WHITE_BALANCE: + break; + case V4L2_CID_RED_BALANCE: + break; + case V4L2_CID_BLUE_BALANCE: + break; + case V4L2_CID_GAMMA: + break; + case V4L2_CID_EXPOSURE: + break; + case V4L2_CID_AUTOGAIN: + break; + case V4L2_CID_GAIN: + break; + case V4L2_CID_HFLIP: + break; + case V4L2_CID_VFLIP: + break; + default: + retval = -EPERM; + break; + } + + return retval; +} + +int get_pixelformat(int index) +{ + int ifmt; + + for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) + if (tc358743_mode_info_data[0][index].flags == tc358743_formats[ifmt].flags) + break; + + if (ifmt == ARRAY_SIZE(tc358743_formats)) + ifmt = 0; /* Default = RBG888 */ + return ifmt; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + pr_debug("%s, INDEX: %d\n", __func__,fsize->index); + if (fsize->index > tc358743_mode_MAX) + return -EINVAL; + + fsize->pixel_format = tc358743_formats[get_pixelformat(fsize->index)].pixelformat; + fsize->discrete.width = + tc358743_mode_info_data[0][fsize->index].width; + fsize->discrete.height = + tc358743_mode_info_data[0][fsize->index].height; + pr_debug("%s %d:%d format: %x\n", __func__, fsize->discrete.width, fsize->discrete.height, fsize->pixel_format); + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, + "tc358743_mipi"); + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + pr_debug("%s\n", __func__); + return 0; +} + +/*! + * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT + * @s: pointer to standard V4L2 device structure + * @fmt: pointer to standard V4L2 fmt description structure + * + * Return 0. + */ +static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, + struct v4l2_fmtdesc *fmt) +{ + pr_debug("%s\n", __func__); + if (fmt->index > tc358743_mode_MAX) + return -EINVAL; + + fmt->pixelformat = tc358743_formats[get_pixelformat(fmt->index)].pixelformat; + + pr_debug("%s: format: %x\n", __func__, fmt->pixelformat); + return 0; +} + +static int ioctl_try_fmt_cap(struct v4l2_int_device *s, + struct v4l2_format *f) +{ + struct sensor_data *sensor = s->priv; + u32 tgt_fps; /* target frames per secound */ + enum tc358743_frame_rate frame_rate; +// enum image_size isize; + int ifmt; + struct v4l2_pix_format *pix = &f->fmt.pix; + pr_debug("%s\n", __func__); + + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) { + frame_rate = tc358743_60_fps; + } else if (tgt_fps == 30) { + frame_rate = tc358743_30_fps; + } else { + pr_debug("%s: %d fps (%d,%d) is not supported\n", __func__, tgt_fps, sensor->streamcap.timeperframe.denominator,sensor->streamcap.timeperframe.numerator); + return -EINVAL; + } + + tc358743_data.pix.width = pix->width = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].width; + tc358743_data.pix.height = pix->height = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].height; + + for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) + if (tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].flags == tc358743_formats[ifmt].flags) + break; + + if (ifmt == ARRAY_SIZE(tc358743_formats)) + ifmt = 0; /* Default = RBG888 */ + + tc358743_data.pix.pixelformat = pix->pixelformat = tc358743_formats[ifmt].pixelformat; + pix->field = V4L2_FIELD_NONE; + pix->bytesperline = pix->width * 4; + pix->sizeimage = pix->bytesperline * pix->height; + pix->priv = 0; + + switch (pix->pixelformat) { + case V4L2_PIX_FMT_UYVY: + default: + pix->colorspace = V4L2_COLORSPACE_SRGB; + break; + } + + { + u32 u32val; + int ret = tc358743_read_reg(0x8520,&u32val); + pr_debug("SYS_STATUS: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8521,&u32val); + pr_debug("VI_STATUS0: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8522,&u32val); + pr_debug("VI_STATUS1: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8525,&u32val); + pr_debug("VI_STATUS2: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8528,&u32val); + pr_debug("VI_STATUS3: 0x%x, ret val: %d \n",u32val,ret); + pr_debug("%s %d:%d format: %x\n", __func__, pix->width, pix->height, pix->pixelformat); + } + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + + pr_debug("%s\n", __func__); + return ioctl_try_fmt_cap(s, f); +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor_data *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + u32 tgt_fps; /* target frames per secound */ + int ret = 0; + enum tc358743_frame_rate frame_rate; + void *mipi_csi2_info; + + pr_debug("%s\n", __func__); + tc358743_data.on = true; + + /* mclk */ + tgt_xclk = tc358743_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)TC358743_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)TC358743_XCLK_MIN); + tc358743_data.mclk = tgt_xclk; + + pr_debug("%s: Setting mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000); +// set_mclk_rate(&tc358743_data.mclk, tc358743_data.mclk_source); +// pr_debug("%s: After mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000); + + /* Default camera frame rate is set in probe */ + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) + frame_rate = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate = tc358743_30_fps; + else + return -EINVAL; + + mipi_csi2_info = mipi_csi2_get_info(); + + /* enable mipi csi2 */ + if (mipi_csi2_info) { + mipi_csi2_enable(mipi_csi2_info); + } else { + pr_err("Fail to get mipi_csi2_info!\n"); + return -EPERM; + } + + pr_debug("%s done\n", __func__); + return ret; +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + void *mipi_csi2_info; + + mipi_csi2_info = mipi_csi2_get_info(); + + /* disable mipi csi2 */ + if (mipi_csi2_info) + if (mipi_csi2_get_status(mipi_csi2_info)) + mipi_csi2_disable(mipi_csi2_info); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc tc358743_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init}, + {vidioc_int_dev_exit_num, ioctl_dev_exit}, + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm}, + {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init}, + {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, + {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *) ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave tc358743_slave = { + .ioctls = tc358743_ioctl_desc, + .num_ioctls = ARRAY_SIZE(tc358743_ioctl_desc), +}; + +static struct v4l2_int_device tc358743_int_device = { + .module = THIS_MODULE, + .name = "tc358743", + .type = v4l2_int_type_slave, + .u = { + .slave = &tc358743_slave, + }, +}; + + +#ifdef AUDIO_ENABLE +struct imx_ssi { + struct platform_device *ac97_dev; + + struct snd_soc_dai *imx_ac97; + struct clk *clk; + void __iomem *base; + int irq; + int fiq_enable; + unsigned int offset; + + unsigned int flags; + + void (*ac97_reset) (struct snd_ac97 *ac97); + void (*ac97_warm_reset)(struct snd_ac97 *ac97); + + struct imx_pcm_dma_params dma_params_rx; + struct imx_pcm_dma_params dma_params_tx; + + int enabled; + + struct platform_device *soc_platform_pdev; + struct platform_device *soc_platform_pdev_fiq; +}; +#define SSI_SCR 0x10 +#define SSI_SRCR 0x20 +#define SSI_STCCR 0x24 +#define SSI_SRCCR 0x28 +#define SSI_SCR_I2S_MODE_NORM (0 << 5) +#define SSI_SCR_I2S_MODE_MSTR (1 << 5) +#define SSI_SCR_I2S_MODE_SLAVE (2 << 5) +#define SSI_I2S_MODE_MASK (3 << 5) +#define SSI_SCR_SYN (1 << 4) +#define SSI_SRCR_RSHFD (1 << 4) +#define SSI_SRCR_RSCKP (1 << 3) +#define SSI_SRCR_RFSI (1 << 2) +#define SSI_SRCR_REFS (1 << 0) +#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_STCCR_WL_MASK (0xf << 13) +#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_SRCCR_WL_MASK (0xf << 13) +/* Audio setup */ + +static int imxpac_tc358743_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret; + + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_IF | + SND_SOC_DAIFMT_CBM_CFM); + if (ret) { + pr_err("%s: failed set cpu dai format\n", __func__); + return ret; + } + + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + if (ret) { + pr_err("%s: failed set codec dai format\n", __func__); + return ret; + } + + ret = snd_soc_dai_set_sysclk(codec_dai, 0, + CODEC_CLOCK, SND_SOC_CLOCK_OUT); + if (ret) { + pr_err("%s: failed setting codec sysclk\n", __func__); + return ret; + } + snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0); + + ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, + SND_SOC_CLOCK_IN); + if (ret) { + pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n"); + return ret; + } +#if 1 +// clear SSI_SRCR_RXBIT0 and SSI_SRCR_RSHFD in order to push Right-justified MSB data fro + { + struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); + u32 scr = 0, srcr = 0, stccr = 0, srccr = 0; + + pr_debug("%s: base %p\n", __func__, (void *)ssi->base); + scr = readl(ssi->base + SSI_SCR); + pr_debug("%s: SSI_SCR before: %p\n", __func__, (void *)scr); + writel(scr, ssi->base + SSI_SCR); + pr_debug("%s: SSI_SCR after: %p\n", __func__, (void *)scr); + + srcr = readl(ssi->base + SSI_SRCR); + pr_debug("%s: SSI_SRCR before: %p\n", __func__, (void *)srcr); + writel(srcr, ssi->base + SSI_SRCR); + pr_debug("%s: SSI_SRCR after: %p\n", __func__, (void *)srcr); + + stccr = readl(ssi->base + SSI_STCCR); + pr_debug("%s: SSI_STCCR before: %p\n", __func__, (void *)stccr); + stccr &= ~SSI_STCCR_WL_MASK; + stccr |= SSI_STCCR_WL(16); + writel(stccr, ssi->base + SSI_STCCR); + pr_debug("%s: SSI_STCCR after: %p\n", __func__, (void *)stccr); + + srccr = readl(ssi->base + SSI_SRCCR); + pr_debug("%s: SSI_SRCCR before: %p\n", __func__, (void *)srccr); + srccr &= ~SSI_SRCCR_WL_MASK; + srccr |= SSI_SRCCR_WL(16); + writel(srccr, ssi->base + SSI_SRCCR); + pr_debug("%s: SSI_SRCCR after: %p\n", __func__, (void *)srccr); + } +#endif + return 0; +} + + + +/* Headphones jack detection DAPM pins */ +static struct snd_soc_jack_pin hs_jack_pins_a[] = { +}; + +/* imx_3stack card dapm widgets */ +static struct snd_soc_dapm_widget imx_3stack_dapm_widgets_a[] = { +}; + + + +static struct snd_kcontrol_new tc358743_machine_controls_a[] = { +}; + +/* imx_3stack machine connections to the codec pins */ +static struct snd_soc_dapm_route audio_map_a[] = { +}; + +static int imx_3stack_tc358743_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_codec *codec = rtd->codec; + int ret; + struct snd_soc_jack *hs_jack; + + struct snd_soc_jack_pin *hs_jack_pins; + int hs_jack_pins_size; + struct snd_soc_dapm_widget *imx_3stack_dapm_widgets; + int imx_3stack_dapm_widgets_size; + struct snd_kcontrol_new *tc358743_machine_controls; + int tc358743_machine_controls_size; + struct snd_soc_dapm_route *audio_map; + int audio_map_size; + int gpio_num = -1; + char *gpio_name; + + pr_debug("%s started\n", __func__); + + hs_jack_pins = hs_jack_pins_a; + hs_jack_pins_size = ARRAY_SIZE(hs_jack_pins_a); + imx_3stack_dapm_widgets = imx_3stack_dapm_widgets_a; + imx_3stack_dapm_widgets_size = ARRAY_SIZE(imx_3stack_dapm_widgets_a); + tc358743_machine_controls = tc358743_machine_controls_a; + tc358743_machine_controls_size = ARRAY_SIZE(tc358743_machine_controls_a); + audio_map = audio_map_a; + audio_map_size = ARRAY_SIZE(audio_map_a); + gpio_num = -1; //card_a_gpio_num; + gpio_name = NULL; + + ret = snd_soc_add_controls(codec, tc358743_machine_controls, + tc358743_machine_controls_size); + if (ret) { + pr_err("%s: snd_soc_add_controls failed. err = %d\n", __func__, ret); + return ret; + } + /* Add imx_3stack specific widgets */ + snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets, + imx_3stack_dapm_widgets_size); + + /* Set up imx_3stack specific audio path audio_map */ + snd_soc_dapm_add_routes(&codec->dapm, audio_map, audio_map_size); + + snd_soc_dapm_enable_pin(&codec->dapm, hs_jack_pins->pin); + snd_soc_dapm_sync(&codec->dapm); + + hs_jack = kzalloc(sizeof(struct snd_soc_jack), GFP_KERNEL); + + + ret = snd_soc_jack_new(codec, hs_jack_pins->pin, + SND_JACK_HEADPHONE, hs_jack); + if (ret) { + pr_err("%s: snd_soc_jack_new failed. err = %d\n", __func__, ret); + return ret; + } + + ret = snd_soc_jack_add_pins(hs_jack,hs_jack_pins_size, + hs_jack_pins); + if (ret) { + pr_err("%s: snd_soc_jack_add_pinsfailed. err = %d\n", __func__, ret); + return ret; + } + return 0; +} + + +static struct snd_soc_ops imxpac_tc358743_snd_ops = { + .hw_params = imxpac_tc358743_hw_params, +}; + +static struct snd_soc_dai_link imxpac_tc358743_dai = { + .name = "tc358743", + .stream_name = "TC358743", + .codec_dai_name = "tc358743-hifi", + .platform_name = "imx-pcm-audio.2", + .codec_name = "tc358743_mipi.1-000f", + .cpu_dai_name = "imx-ssi.2", + .init = imx_3stack_tc358743_init, + .ops = &imxpac_tc358743_snd_ops, +}; + +static struct snd_soc_card imxpac_tc358743 = { + .name = "cpuimx-audio_hdmi_in", + .dai_link = &imxpac_tc358743_dai, + .num_links = 1, +}; + +static struct platform_device *imxpac_tc358743_snd_device; +static struct platform_device *imxpac_tc358743_snd_device; + +static int imx_audmux_config(int slave, int master) +{ + unsigned int ptcr, pdcr; + slave = slave - 1; + master = master - 1; + + /* SSI0 mastered by port 5 */ + ptcr = MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(master | 0x8) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_RFSDIR | + MXC_AUDMUX_V2_PTCR_RFSEL(master | 0x8) | + MXC_AUDMUX_V2_PTCR_RCLKDIR | + MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) | + MXC_AUDMUX_V2_PTCR_TCSEL(master | 0x8); + pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); + mxc_audmux_v2_configure_port(slave, ptcr, pdcr); + + ptcr = MXC_AUDMUX_V2_PTCR_SYN; + pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); + mxc_audmux_v2_configure_port(master, ptcr, pdcr); + return 0; +} + +static int __devinit imx_tc358743_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + int ret = 0; + + + imx_audmux_config(plat->src_port, plat->ext_port); + + ret = -EINVAL; + if (plat->init && plat->init()) + return ret; + + printk("%s %d %s\n",__func__,__LINE__,pdev->name); + return 0; +} + +static int imx_tc358743_remove(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->finit) + plat->finit(); + + return 0; +} + +static struct platform_driver imx_tc358743_audio1_driver = { + .probe = imx_tc358743_probe, + .remove = imx_tc358743_remove, + .driver = { + .name = "imx-tc358743", + }, +}; + + +/* Codec setup */ +static int tc358743_codec_probe(struct snd_soc_codec *codec) +{ + return 0; +} + +static int tc358743_codec_remove(struct snd_soc_codec *codec) +{ + return 0; +} + +static int tc358743_codec_suspend(struct snd_soc_codec *codec, pm_message_t state) +{ +// tc358743_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int tc358743_codec_resume(struct snd_soc_codec *codec) +{ +// tc358743_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} + +static int tc358743_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + return 0; +} + +static const u8 tc358743_reg[0] = { +}; + +static struct snd_soc_codec_driver soc_codec_dev_tc358743 = { + .set_bias_level = tc358743_set_bias_level, + .reg_cache_size = ARRAY_SIZE(tc358743_reg), + .reg_word_size = sizeof(u8), + .reg_cache_default = tc358743_reg, + .probe = tc358743_codec_probe, + .remove = tc358743_codec_remove, + .suspend = tc358743_codec_suspend, + .resume = tc358743_codec_resume, +}; + +#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 +#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static int tc358743_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + return 0; +} + +static int tc358743_mute(struct snd_soc_dai *dai, int mute) +{ + return 0; +} + +static int tc358743_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + return 0; +} + +static int tc358743_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + return 0; +} + +static struct snd_soc_dai_ops tc358743_dai_ops = { + .hw_params = tc358743_hw_params, + .digital_mute = tc358743_mute, + .set_sysclk = tc358743_set_dai_sysclk, + .set_fmt = tc358743_set_dai_fmt, +}; + +static struct snd_soc_dai_driver tc358743_dai = { + .name = "tc358743-hifi", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AIC3X_RATES, + .formats = AIC3X_FORMATS,}, + .ops = &tc358743_dai_ops, + .symmetric_rates = 1, +}; + +#endif + +static char tc358743_mode_list[16][12] = +{ + "None", + "VGA", + "240p/480i", + "288p/576i", + "W240p/480i", + "W288p/576i", + "480p", + "576p", + "W480p", + "W576p", + "WW480p", + "WW576p", + "720p", + "1035i", + "1080i", + "1080p" +}; + +static char tc358743_fps_list[tc358743_max_fps+1] = +{ +[tc358743_60_fps] = 60, +[tc358743_30_fps] = 30, +[tc358743_max_fps] = 0 +}; + +static int tc358743_audio_list[16] = +{ + 44100, + 0, + 48000, + 32000, + 22050, + 384000, + 24000, + 352800, + 88200, + 768000, + 96000, + 705600, + 176400, + 0, + 192000, + 0 +}; + +static char str_on[80]; +static void report_netlink(void) +{ + char *envp[2]; + envp[0] = &str_on[0]; + envp[1] = NULL; + sprintf(envp[0], "HDMI RX: %d (%s) %d %d", (unsigned char)hdmi_mode & 0xf, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], tc358743_fps_list[fps], tc358743_audio_list[audio]); + kobject_uevent_env(&(tc358743_data.i2c_client->dev.kobj), KOBJ_CHANGE, envp); + det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; + pr_debug("%s: HDMI RX (%d) mode: %s fps: %d (%d, %d) audio: %d\n", __func__, (unsigned char)hdmi_mode, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout, tc358743_audio_list[audio]); +} + +static void det_worker(struct work_struct *work) +{ + u32 u32val; + u16 reg; + int ret; + + mutex_lock(&access_lock); + if (!det_work_disable) { + reg = 0x8621; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) { + if (audio != (((unsigned char)u32val) & 0x0f)) { + audio = ((unsigned char)u32val) & 0x0f; + report_netlink(); + } + } + reg = 0x852f; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) { + while (1) { + if (u32val & TC3587430_HDMI_DETECT) { + lock = u32val & TC3587430_HDMI_DETECT; + reg = 0x8521; + ret = tc358743_read_reg(reg, &u32val); + if (ret < 0) { + pr_err("%s: Error reading mode\n", __func__); + } + } else { + if (lock) { // check if it is realy un-plug + lock = 0; + u32val = 0x0; + hdmi_mode = 0xF0; // fake mode to detect un-plug if mode was not detected before. + } + } + if ((unsigned char)hdmi_mode != (unsigned char)u32val) { + if (u32val) + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + else + det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; + bounce = MAX_BOUNCE; + pr_debug("%s: HDMI RX (%d != %d) mode: %s fps: %d (%d, %d)\n", __func__, (unsigned char)hdmi_mode, (unsigned char)u32val, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout); + hdmi_mode = u32val; + } else if (bounce) { + bounce--; + det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; + } + + if (1 == bounce) { + if (hdmi_mode >= 0xe) { + reg = 0x852f; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) + fps = ((((unsigned char)u32val) & 0x0f) > 0xa)? tc358743_60_fps: tc358743_30_fps; + } + reg = 0x8621; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) { + audio = ((unsigned char)u32val) & 0x0f; + report_netlink(); + } + } + break; + } + } else { + pr_err("%s: Error reading lock\n", __func__); + } + } else { + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + } + mutex_unlock(&access_lock); + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); +} + +static irqreturn_t tc358743_detect_handler(int irq, void *data) +{ + + pr_debug("%s: IRQ %d\n", __func__, tc358743_data.i2c_client->irq); + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); + return IRQ_HANDLED; +} + + +/*! + * tc358743 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +#define DUMP_LENGTH 256 +static u16 regoffs = 0; + +static ssize_t tc358743_show_regdump(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i, len = 0; + int retval; + u32 u32val; + + mutex_lock(&access_lock); + for (i=0; i<DUMP_LENGTH; ) { + retval = tc358743_read_reg(regoffs+i, &u32val); + if (retval < 0) { + u32val =0xff; + retval = 1; + } + while (retval-- > 0) { + if (0 == (i & 0xf)) + len += sprintf(buf+len, "\n%04X:", regoffs+i); + len += sprintf(buf+len, " %02X", u32val&0xff); + u32val >>= 8; + i++; + } + } + mutex_unlock(&access_lock); + len += sprintf(buf+len, "\n"); + return len; +} + +static DEVICE_ATTR(regdump, S_IRUGO, tc358743_show_regdump, NULL); + +static ssize_t tc358743_store_regoffs(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 val; + int retval; + retval = sscanf(buf, "%x", &val); + if (1 == retval) + regoffs = (u16)val; + return count; +} + +static ssize_t tc358743_show_regoffs(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "0x%04X\n", regoffs); + return len; +} + +static DEVICE_ATTR(regoffs, S_IRUGO|S_IWUSR, tc358743_show_regoffs, tc358743_store_regoffs); + +static ssize_t tc358743_store_hpd(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 val; + int retval; + retval = sscanf(buf, "%d", &val); + if (1 == retval) + hpd_active = (u16)val; + return count; +} + +static ssize_t tc358743_show_hpd(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", hpd_active); + return len; +} + +static DEVICE_ATTR(hpd, S_IRUGO|S_IWUSR, tc358743_show_hpd, tc358743_store_hpd); + +static ssize_t tc358743_show_hdmirx(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", hdmi_mode); + return len; +} + +static DEVICE_ATTR(hdmirx, S_IRUGO, tc358743_show_hdmirx, NULL); + +static ssize_t tc358743_show_fps(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", tc358743_fps_list[fps]); + return len; +} + +static DEVICE_ATTR(fps, S_IRUGO, tc358743_show_fps, NULL); + +#ifdef AUDIO_ENABLE +static ssize_t tc358743_show_audio(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", tc358743_audio_list[audio]); + return len; +} + +static DEVICE_ATTR(audio, S_IRUGO, tc358743_show_audio, NULL); +#endif + +static int tc358743_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pwm_device *pwm; + struct device *dev = &client->dev; + int retval; + struct regmap *gpr; + struct sensor_data *sensor = &tc358743_data; + u32 u32val; + + + /* request power down pin */ + pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(pwn_gpio)) { + dev_warn(dev, "no sensor pwdn pin available"); + } else { + retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + "tc_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "request of pwn_gpio failed"); + return retval; + } + } + /* request reset pin */ + rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(rst_gpio)) { + dev_warn(dev, "no sensor reset pin available"); + return -EINVAL; + } + retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, + "tc_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "request of tc_mipi_reset failed"); + return retval; + } + + /* Set initial values for the sensor struct. */ + memset(sensor, 0, sizeof(*sensor)); + + sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(sensor->sensor_clk)) { + /* assuming clock enabled by default */ + sensor->sensor_clk = NULL; + dev_err(dev, "clock-frequency missing or invalid\n"); + return PTR_ERR(sensor->sensor_clk); + } + + retval = of_property_read_u32(dev->of_node, "mclk", + &(sensor->mclk)); + if (retval) { + dev_err(dev, "mclk missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "mclk_source", + (u32 *) &(sensor->mclk_source)); + if (retval) { + dev_err(dev, "mclk_source missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "csi_id", + &(sensor->csi)); + if (retval) { + dev_err(dev, "csi id missing or invalid\n"); + return retval; + } + if (((unsigned)sensor->ipu_id > 1) || ((unsigned)sensor->csi > 1)) { + dev_err(dev, "invalid ipu/csi\n"); + return -EINVAL; + } + + clk_prepare_enable(sensor->sensor_clk); + + sensor->io_init = tc_reset; + sensor->i2c_client = client; + sensor->pix.pixelformat = tc358743_formats[0].pixelformat; + sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + sensor->streamcap.capturemode = 0; + sensor->streamcap.extendedmode = tc358743_mode_1080P_1920_1080; + sensor->streamcap.timeperframe.denominator = DEFAULT_FPS; + sensor->streamcap.timeperframe.numerator = 1; + + sensor->pix.width = tc358743_mode_info_data[0][sensor->streamcap.capturemode].width; + sensor->pix.height = tc358743_mode_info_data[0][sensor->streamcap.capturemode].height; + pr_debug("%s: format: %x, capture mode: %d extended mode: %d fps: %d width: %d height: %d\n",__func__, + sensor->pix.pixelformat, + sensor->streamcap.capturemode, sensor->streamcap.extendedmode, + sensor->streamcap.timeperframe.denominator * + sensor->streamcap.timeperframe.numerator, + sensor->pix.width, + sensor->pix.height); + + pwm = pwm_get(dev, NULL); + if (!IS_ERR(pwm)) { + dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->period); + pwm_config(pwm, pwm->period >> 1, pwm->period); + pwm_enable(pwm); + } + + tc_power_on(dev); + tc_reset(); + tc_standby(0); + + retval = tc358743_read_reg(TC358743_CHIP_ID_HIGH_BYTE, &u32val); + if (retval < 0) { + pr_err("%s:cannot find camera\n", __func__); + retval = -ENODEV; + goto err4; + } + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + if (sensor->csi == sensor->ipu_id) { + int mask = sensor->csi ? (1 << 20) : (1 << 19); + + regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0); + } + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = sensor->csi ? (7 << 3) : (7 << 0); + int val = sensor->csi ? (3 << 3) : (0 << 0); + + if (sensor->ipu_id) { + dev_err(dev, "invalid ipu\n"); + return -EINVAL; + } + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + + tc358743_int_device.priv = sensor; + + //retval = device_create_file(&client->dev, &dev_attr_audio); + retval = device_create_file(&client->dev, &dev_attr_fps); + retval = device_create_file(&client->dev, &dev_attr_hdmirx); + retval = device_create_file(&client->dev, &dev_attr_hpd); + retval = device_create_file(&client->dev, &dev_attr_regoffs); + retval = device_create_file(&client->dev, &dev_attr_regdump); + + if (retval) { + pr_err("%s: create bin file failed, error=%d\n", + __func__, retval); + goto err4; + } + +#ifdef AUDIO_ENABLE +/* Audio setup */ + retval = snd_soc_register_codec(&client->dev, + &soc_codec_dev_tc358743, &tc358743_dai, 1); + if (retval) { + pr_err("%s: register failed, error=%d\n", + __func__, retval); + goto err4; + } + + retval = platform_driver_register(&imx_tc358743_audio1_driver); + if (retval) { + pr_err("%s: Platform driver register failed, error=%d\n", + __func__, retval); + goto err4; + } + + imxpac_tc358743_snd_device = platform_device_alloc("soc-audio", 5); + if (!imxpac_tc358743_snd_device) { + pr_err("%s: Platform device allocation failed, error=%d\n", + __func__, retval); + goto err4; + } + + platform_set_drvdata(imxpac_tc358743_snd_device, &imxpac_tc358743); + retval = platform_device_add(imxpac_tc358743_snd_device); + + if (retval) { + pr_err("%s: Platform device add failed, error=%d\n", + __func__, retval); + platform_device_put(imxpac_tc358743_snd_device); + goto err4; + } +#endif + +#if 1 + INIT_DELAYED_WORK(&(det_work), det_worker); + if (sensor->i2c_client->irq) { + retval = request_irq(sensor->i2c_client->irq, tc358743_detect_handler, + IRQF_SHARED | IRQF_TRIGGER_FALLING, + "tc358743_det", sensor); + if (retval < 0) + dev_warn(&sensor->i2c_client->dev, + "cound not request det irq %d\n", + sensor->i2c_client->irq); + } + + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); +#endif + retval = tc358743_reset(sensor); + + tc_standby(1); + retval = v4l2_int_device_register(&tc358743_int_device); + if (retval) { + pr_err("%s: v4l2_int_device_register failed, error=%d\n", + __func__, retval); + goto err4; + } + pr_debug("%s: finished, error=%d\n", + __func__, retval); + return retval; + +err4: + pr_err("%s: failed, error=%d\n", + __func__, retval); + return retval; +} + +/*! + * tc358743 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int tc358743_remove(struct i2c_client *client) +{ + // Stop delayed work + cancel_delayed_work_sync(&(det_work)); + + // Remove IRQ + if (tc358743_data.i2c_client->irq) { + free_irq(tc358743_data.i2c_client->irq, &tc358743_data); + } + + /*Remove sysfs entries*/ + device_remove_file(&client->dev, &dev_attr_fps); + device_remove_file(&client->dev, &dev_attr_hdmirx); + device_remove_file(&client->dev, &dev_attr_hpd); + device_remove_file(&client->dev, &dev_attr_regoffs); + device_remove_file(&client->dev, &dev_attr_regdump); + + v4l2_int_device_unregister(&tc358743_int_device); + + if (gpo_regulator) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator); + } + + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } + + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } + + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } + + return 0; +} + +/*! + * tc358743 init function + * Called by insmod tc358743_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int tc358743_init(void) +{ + int err; + + err = i2c_add_driver(&tc358743_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d\n", + __func__, err); + + return err; +} + +/*! + * tc358743 cleanup function + * Called on rmmod tc358743_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit tc358743_clean(void) +{ + i2c_del_driver(&tc358743_i2c_driver); +} + +module_init(tc358743_init); +module_exit(tc358743_clean); + +MODULE_AUTHOR("Panasonic Avionics Corp."); +MODULE_DESCRIPTION("Toshiba TC358743 HDMI-to-CSI2 Bridge MIPI Input Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_ALIAS("CSI"); diff --git a/drivers/media/platform/mxc/output/mxc_vout.c b/drivers/media/platform/mxc/output/mxc_vout.c index bd7d1f0446f3..237953f8295c 100644 --- a/drivers/media/platform/mxc/output/mxc_vout.c +++ b/drivers/media/platform/mxc/output/mxc_vout.c @@ -361,8 +361,7 @@ static int update_setting_from_fbi(struct mxc_vout_output *vout, if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) { vout->crop_bounds = g_fb_setting[i].crop_bounds; vout->disp_fmt = g_fb_setting[i].disp_fmt; - vout->disp_support_csc = - g_fb_setting[i].disp_support_csc; + vout->disp_support_csc = false; vout->disp_support_windows = g_fb_setting[i].disp_support_windows; found = true; diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3e894e84a46c..4cd4e69308a4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -626,7 +626,7 @@ config MFD_STMPE Currently supported devices are: - STMPE811: GPIO, Touchscreen + STMPE811: GPIO, Touchscreen, ADC STMPE1601: GPIO, Keypad STMPE1801: GPIO, Keypad STMPE2401: GPIO, Keypad @@ -639,6 +639,7 @@ config MFD_STMPE GPIO: stmpe-gpio Keypad: stmpe-keypad Touchscreen: stmpe-ts + ADC: stmpe-adc menu "STMicroelectronics STMPE Interface Drivers" depends on MFD_STMPE diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index bbccd514d3ec..1cc546396071 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -417,6 +417,32 @@ static struct mfd_cell stmpe_ts_cell = { }; /* + * ADC (STMPE811) + */ + +static struct resource stmpe_adc_resources[] = { + { + .name = "STMPE_TEMP_SENS", + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "STMPE_ADC", + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mfd_cell stmpe_adc_cell = { + .name = "stmpe-adc", + .of_compatible = "st,stmpe-adc", + .resources = stmpe_adc_resources, + .num_resources = ARRAY_SIZE(stmpe_adc_resources), +}; + +/* * STMPE811 or STMPE610 */ @@ -448,6 +474,11 @@ static struct stmpe_variant_block stmpe811_blocks[] = { .irq = STMPE811_IRQ_TOUCH_DET, .block = STMPE_BLOCK_TOUCHSCREEN, }, + { + .cell = &stmpe_adc_cell, + .irq = STMPE811_IRQ_TEMP_SENS, + .block = STMPE_BLOCK_ADC, + }, }; static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c index dd27b0783d52..6cf73090324e 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c @@ -1977,7 +1977,8 @@ static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card, * index anymore so we keep track of a name index. */ if (!subname) { - md->name_idx = find_first_zero_bit(name_use, max_devices); + md->name_idx = find_next_zero_bit(name_use, max_devices, + card->host->index); __set_bit(md->name_idx, name_use); } else md->name_idx = ((struct mmc_blk_data *) @@ -2138,7 +2139,8 @@ static int mmc_blk_alloc_parts(struct mmc_card *card, struct mmc_blk_data *md) return 0; for (idx = 0; idx < card->nr_parts; idx++) { - if (card->part[idx].size) { + if (card->part[idx].size && + !(card->part[idx].area_type & MMC_BLK_DATA_AREA_RPMB)) { ret = mmc_blk_alloc_part(card, md, card->part[idx].part_cfg, card->part[idx].size >> 9, diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index c40396f23202..acc69ecc23f8 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -51,7 +51,6 @@ */ #define MMC_BKOPS_MAX_TIMEOUT (4 * 60 * 1000) /* max time to wait in ms */ -static struct workqueue_struct *workqueue; static const unsigned freqs[] = { 400000, 300000, 200000, 100000 }; /* @@ -79,23 +78,6 @@ MODULE_PARM_DESC( removable, "MMC/SD cards are removable and may be removed during suspend"); -/* - * Internal function. Schedule delayed work in the MMC work queue. - */ -static int mmc_schedule_delayed_work(struct delayed_work *work, - unsigned long delay) -{ - return queue_delayed_work(workqueue, work, delay); -} - -/* - * Internal function. Flush all scheduled work from the MMC work queue. - */ -static void mmc_flush_scheduled_work(void) -{ - flush_workqueue(workqueue); -} - #ifdef CONFIG_FAIL_MMC_REQUEST /* @@ -1656,7 +1638,7 @@ void mmc_detect_change(struct mmc_host *host, unsigned long delay) spin_unlock_irqrestore(&host->lock, flags); #endif host->detect_change = 1; - mmc_schedule_delayed_work(&host->detect, delay); + queue_delayed_work(host->workqueue, &host->detect, delay); } EXPORT_SYMBOL(mmc_detect_change); @@ -2409,7 +2391,7 @@ void mmc_rescan(struct work_struct *work) out: if (host->caps & MMC_CAP_NEEDS_POLL) - mmc_schedule_delayed_work(&host->detect, HZ); + queue_delayed_work(host->workqueue, &host->detect, HZ); } void mmc_start_host(struct mmc_host *host) @@ -2434,7 +2416,7 @@ void mmc_stop_host(struct mmc_host *host) host->rescan_disable = 1; cancel_delayed_work_sync(&host->detect); - mmc_flush_scheduled_work(); + flush_workqueue(host->workqueue); /* clear pm flags now and let card drivers set them as needed */ host->pm_flags = 0; @@ -2629,7 +2611,7 @@ int mmc_suspend_host(struct mmc_host *host) int err = 0; cancel_delayed_work(&host->detect); - mmc_flush_scheduled_work(); + flush_workqueue(host->workqueue); mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { @@ -2793,13 +2775,9 @@ static int __init mmc_init(void) { int ret; - workqueue = alloc_ordered_workqueue("kmmcd", 0); - if (!workqueue) - return -ENOMEM; - ret = mmc_register_bus(); if (ret) - goto destroy_workqueue; + return ret; ret = mmc_register_host_class(); if (ret) @@ -2815,9 +2793,6 @@ unregister_host_class: mmc_unregister_host_class(); unregister_bus: mmc_unregister_bus(); -destroy_workqueue: - destroy_workqueue(workqueue); - return ret; } @@ -2826,7 +2801,6 @@ static void __exit mmc_exit(void) sdio_unregister_bus(); mmc_unregister_host_class(); mmc_unregister_bus(); - destroy_workqueue(workqueue); } subsys_initcall(mmc_init); diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 2a3593d9f87d..fb07816a1f0a 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -36,6 +36,7 @@ static void mmc_host_classdev_release(struct device *dev) { struct mmc_host *host = cls_dev_to_mmc_host(dev); mutex_destroy(&host->slot.lock); + destroy_workqueue(host->workqueue); kfree(host); } @@ -426,8 +427,8 @@ EXPORT_SYMBOL(mmc_of_parse); */ struct mmc_host *mmc_alloc_host(int extra, struct device *dev) { - int err; struct mmc_host *host; + int of_id = -1, id = -1; host = kzalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL); if (!host) @@ -437,15 +438,32 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev) host->rescan_disable = 1; idr_preload(GFP_KERNEL); spin_lock(&mmc_host_lock); - err = idr_alloc(&mmc_host_idr, host, 0, 0, GFP_NOWAIT); - if (err >= 0) - host->index = err; + + if (dev->of_node) + of_id = of_alias_get_id(dev->of_node, "mmc"); + + if (of_id >= 0) { + id = idr_alloc(&mmc_host_idr, host, of_id, of_id + 1, + GFP_NOWAIT); + if (id < 0) + dev_warn(dev, "/aliases ID %d not available\n", of_id); + } + + if (id < 0) + id = idr_alloc(&mmc_host_idr, host, 0, 0, GFP_NOWAIT); + + if (id >= 0) + host->index = id; + spin_unlock(&mmc_host_lock); idr_preload_end(); - if (err < 0) + if (id < 0) goto free; dev_set_name(&host->class_dev, "mmc%d", host->index); + host->workqueue = alloc_ordered_workqueue("kmmcd%d", 0, host->index); + if (!host->workqueue) + goto free; host->parent = dev; host->class_dev.parent = dev; diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 61fb652dfcfa..2b73811d1452 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -292,13 +292,12 @@ static int mmc_read_ext_csd(struct mmc_card *card, u8 *ext_csd) } } + /* + * The EXT_CSD format is meant to be forward compatible. As long + * as CSD_STRUCTURE does not change, all values for EXT_CSD_REV + * are authorized, see JEDEC JESD84-B50 section B.8. + */ card->ext_csd.rev = ext_csd[EXT_CSD_REV]; - if (card->ext_csd.rev > 6) { - pr_err("%s: unrecognised EXT_CSD revision %d\n", - mmc_hostname(card->host), card->ext_csd.rev); - err = -EINVAL; - goto out; - } card->ext_csd.raw_sectors[0] = ext_csd[EXT_CSD_SEC_CNT + 0]; card->ext_csd.raw_sectors[1] = ext_csd[EXT_CSD_SEC_CNT + 1]; diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index d2eb8911dc98..3c202e070aea 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -973,6 +973,9 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, else boarddata->support_vsel = true; + if (of_find_property(np, "vqmmc-1-8-v", NULL)) + boarddata->vqmmc_18v = true; + if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) boarddata->delay_line = 0; @@ -1173,6 +1176,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) } else { host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; } + if (boarddata->vqmmc_18v) + host->quirks2 |= SDHCI_QUIRK2_VQMMC_1_8_V; if (host->mmc->pm_caps & MMC_PM_KEEP_POWER && host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index beb3fc94947b..d533131d3839 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1750,6 +1750,9 @@ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (host->quirks2 & SDHCI_QUIRK2_VQMMC_1_8_V) + ios->signal_voltage = MMC_SIGNAL_VOLTAGE_180; + switch (ios->signal_voltage) { case MMC_SIGNAL_VOLTAGE_330: /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ @@ -1777,7 +1780,7 @@ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, return -EAGAIN; case MMC_SIGNAL_VOLTAGE_180: - if (host->vqmmc) { + if (host->vqmmc && !(host->quirks2 & SDHCI_QUIRK2_VQMMC_1_8_V)) { ret = regulator_set_voltage(host->vqmmc, 1700000, 1950000); if (ret) { @@ -2201,8 +2204,9 @@ static void sdhci_timeout_timer(unsigned long data) spin_lock_irqsave(&host->lock, flags); if (host->mrq) { - pr_err("%s: Timeout waiting for hardware " - "interrupt.\n", mmc_hostname(host->mmc)); + pr_err("%s: Timeout waiting for hardware interrupt. retries left=%d opcode=%x\n", + mmc_hostname(host->mmc), host->cmd ? host->cmd->retries : 0, + host->cmd ? host->cmd->opcode : 0); sdhci_dumpregs(host); if (host->data) { diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 1ae9b7f9e775..a2a2edba866f 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -644,13 +644,13 @@ int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel ipu->csi_channel[params->csi_mem.csi] = channel; /*SMFC setting*/ - if (params->csi_mem.mipi_en) { + if (params->csi_mem.mipi.en) { ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + params->csi_mem.csi)); - _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_vc, + _ipu_smfc_init(ipu, channel, params->csi_mem.mipi.vc, params->csi_mem.csi); - _ipu_csi_set_mipi_di(ipu, params->csi_mem.mipi_vc, - params->csi_mem.mipi_id, params->csi_mem.csi); + _ipu_csi_set_mipi_di(ipu, params->csi_mem.mipi.vc, + params->csi_mem.mipi.id, params->csi_mem.csi); } else { ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + params->csi_mem.csi)); @@ -675,12 +675,12 @@ int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel ipu->ic_use_count++; ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel; - if (params->csi_prp_enc_mem.mipi_en) { + if (params->csi_prp_enc_mem.mipi.en) { ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + params->csi_prp_enc_mem.csi)); _ipu_csi_set_mipi_di(ipu, - params->csi_prp_enc_mem.mipi_vc, - params->csi_prp_enc_mem.mipi_id, + params->csi_prp_enc_mem.mipi.vc, + params->csi_prp_enc_mem.mipi.id, params->csi_prp_enc_mem.csi); } else ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + @@ -716,12 +716,12 @@ int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel ipu->ic_use_count++; ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel; - if (params->csi_prp_vf_mem.mipi_en) { + if (params->csi_prp_vf_mem.mipi.en) { ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + params->csi_prp_vf_mem.csi)); _ipu_csi_set_mipi_di(ipu, - params->csi_prp_vf_mem.mipi_vc, - params->csi_prp_vf_mem.mipi_id, + params->csi_prp_vf_mem.mipi.vc, + params->csi_prp_vf_mem.mipi.id, params->csi_prp_vf_mem.csi); } else ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + @@ -932,6 +932,38 @@ err: } EXPORT_SYMBOL(ipu_init_channel); +int32_t ipu_channel_request(struct ipu_soc *ipu, ipu_channel_t channel, + ipu_channel_params_t *params, struct ipu_chan **p_ipu_chan) +{ + struct ipu_chan *ipu_chan; + unsigned channel_id = IPU_CHAN_ID(channel); + int32_t ret; + + dev_dbg(ipu->dev, "init channel = %d\n", channel_id); + *p_ipu_chan = NULL; + if (channel_id >= ARRAY_SIZE(ipu->chan)) { + dev_err(ipu->dev, "%s: ch = %d is too big!\n", __func__, + channel_id); + return -ENODEV; + } + ipu_chan = &ipu->chan[channel_id]; + if (ipu_chan->p_ipu_chan && (ipu_chan->p_ipu_chan != p_ipu_chan)) { + dev_err(ipu->dev, "%s: ch = %d is busy!\n", __func__, + channel_id); + return -EBUSY; + } + ipu_chan->p_ipu_chan = p_ipu_chan; + ipu_chan->ipu = ipu; + ipu_chan->channel = channel; + ret = ipu_init_channel(ipu, channel, params); + if (ret) + ipu_chan->p_ipu_chan = NULL; + else + *p_ipu_chan = ipu_chan; + return ret; +} +EXPORT_SYMBOL(ipu_channel_request); + /*! * This function is called to uninitialize a logical IPU channel. * @@ -1170,6 +1202,18 @@ void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel) } EXPORT_SYMBOL(ipu_uninit_channel); +void ipu_channel_free(struct ipu_chan **p_ipu_chan) +{ + struct ipu_chan *ipu_chan = *p_ipu_chan; + + *p_ipu_chan = NULL; + if (ipu_chan) { + ipu_chan->p_ipu_chan = NULL; + ipu_uninit_channel(ipu_chan->ipu, ipu_chan->channel); + } +} +EXPORT_SYMBOL(ipu_channel_free); + /*! * This function is called to initialize buffer(s) for logical IPU channel. * @@ -2472,6 +2516,15 @@ int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wai } EXPORT_SYMBOL(ipu_disable_channel); +int32_t ipu_channel_disable(struct ipu_chan *ipu_chan, bool wait_for_stop) +{ + if (ipu_chan) + if (!IS_ERR(ipu_chan)) + return ipu_disable_channel(ipu_chan->ipu, ipu_chan->channel, wait_for_stop); + return 0; +} +EXPORT_SYMBOL(ipu_channel_disable); + /*! * This function enables CSI. * @@ -2823,14 +2876,16 @@ void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id) _ipu_get(ipu); + if (ipu->irq_list[irq].dev_id != dev_id) + return; + spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags); /* disable the interrupt */ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq)); reg &= ~IPUIRQ_2_MASK(irq); ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq)); - if (ipu->irq_list[irq].dev_id == dev_id) - memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq])); + memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq])); spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags); diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h index 076339813809..ff3fee55ae4b 100644 --- a/drivers/mxc/ipu3/ipu_prv.h +++ b/drivers/mxc/ipu3/ipu_prv.h @@ -62,6 +62,14 @@ struct ipu_pltfm_data { bool bypass_reset; }; +struct ipu_soc; + +struct ipu_chan { + struct ipu_soc *ipu; + ipu_channel_t channel; + struct ipu_chan **p_ipu_chan; +}; + struct ipu_soc { bool online; struct ipu_pltfm_data *pdata; @@ -78,7 +86,7 @@ struct ipu_soc { int irq_sync; int irq_err; struct ipu_irq_node irq_list[IPU_IRQ_COUNT]; - + struct ipu_chan chan[32]; /*reg*/ void __iomem *cm_reg; void __iomem *idmac_reg; diff --git a/drivers/mxc/mipi/mxc_mipi_csi2.c b/drivers/mxc/mipi/mxc_mipi_csi2.c index df45c364f144..c56d244e1671 100644 --- a/drivers/mxc/mipi/mxc_mipi_csi2.c +++ b/drivers/mxc/mipi/mxc_mipi_csi2.c @@ -473,7 +473,7 @@ static int mipi_csi2_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gmipi_csi2); - dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed\n"); + dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed ipu%d csi%d\n", gmipi_csi2->ipu_id, gmipi_csi2->csi_id); dev_info(&pdev->dev, "i.MX MIPI CSI2 dphy version is 0x%x\n", mipi_csi2_dphy_ver); diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index ff6d7c32ae87..7a957e8f9dfc 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -55,6 +55,7 @@ #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ +#define FEC_FTRL 0x1b0 /* Frame truncation receive length*/ #define FEC_RACC 0x1C4 /* Receive Accelerator function */ #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ @@ -376,6 +377,15 @@ struct fec_enet_delayed_work { bool trig_tx; }; +struct bufdesc_prop { + /* Address of Rx and Tx buffers */ + struct bufdesc *base; + struct bufdesc *last; + struct bufdesc *cur; + dma_addr_t dma; + unsigned short ring_size; + unsigned short desc_size; +}; /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and * tx_bd_base always point to the base of the buffer descriptors. The * cur_rx and cur_tx point to the currently available buffer. @@ -401,12 +411,9 @@ struct fec_enet_private { struct sk_buff *rx_skbuff[RX_RING_SIZE]; /* CPM dual port RAM relative addresses */ - dma_addr_t bd_dma; - /* Address of Rx and Tx buffers */ - struct bufdesc *rx_bd_base; - struct bufdesc *tx_bd_base; - /* The next free ring entry */ - struct bufdesc *cur_rx, *cur_tx; + struct bufdesc_prop bd_tx; + struct bufdesc_prop bd_rx; + /* The ring entries to be free()ed */ struct bufdesc *dirty_tx; diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 1b5674a2dfb8..90ba927556e2 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -52,6 +52,7 @@ #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_gpio.h> +#include <linux/of_irq.h> #include <linux/of_net.h> #include <linux/regulator/consumer.h> #include <linux/if_vlan.h> @@ -243,22 +244,18 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); static int mii_cnt; -static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) +static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, + struct bufdesc_prop *bd) { - struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; - if (is_ex) - return (struct bufdesc *)(ex + 1); - else - return bdp + 1; + return (bdp >= bd->last) ? bd->base + : (struct bufdesc *)(((unsigned)bdp) + bd->desc_size); } -static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) +static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, + struct bufdesc_prop *bd) { - struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; - if (is_ex) - return (struct bufdesc *)(ex - 1); - else - return bdp - 1; + return (bdp <= bd->base) ? bd->last + : (struct bufdesc *)(((unsigned)bdp) - bd->desc_size); } static void *swap_buffer(void *bufaddr, int len) @@ -293,17 +290,15 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) struct fec_enet_private *fep = netdev_priv(ndev); const struct platform_device_id *id_entry = platform_get_device_id(fep->pdev); - struct bufdesc *bdp, *bdp_pre; + struct bufdesc *bdp; void *bufaddr; - unsigned short status; + unsigned short prev_status; unsigned int index; /* Fill in a Tx ring entry */ - bdp = fep->cur_tx; + bdp = fep->bd_tx.cur; - status = bdp->cbd_sc; - - if (status & BD_ENET_TX_READY) { + if (bdp->cbd_sc & BD_ENET_TX_READY) { /* Ooops. All transmit buffers are full. Bail out. * This should not happen, since ndev->tbusy should be set. */ @@ -317,9 +312,6 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) return NETDEV_TX_OK; } - /* Clear all of the status flags */ - status &= ~BD_ENET_TX_STATS; - /* Set buffer length and buffer pointer */ bufaddr = skb->data; bdp->cbd_datlen = skb->len; @@ -331,9 +323,9 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) */ if (fep->bufdesc_ex) index = (struct bufdesc_ex *)bdp - - (struct bufdesc_ex *)fep->tx_bd_base; + (struct bufdesc_ex *)fep->bd_tx.base; else - index = bdp - fep->tx_bd_base; + index = bdp - fep->bd_tx.base; if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { memcpy(fep->tx_bounce[index], skb->data, skb->len); @@ -361,12 +353,6 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) netdev_err(ndev, "Tx DMA memory map failed\n"); return NETDEV_TX_OK; } - /* Send it on its way. Tell FEC it's ready, interrupt when done, - * it's the last BD of the frame, and to put the CRC on the end. - */ - status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR - | BD_ENET_TX_LAST | BD_ENET_TX_TC); - bdp->cbd_sc = status; if (fep->bufdesc_ex) { @@ -389,27 +375,36 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) } } - bdp_pre = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && - !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { - fep->delay_work.trig_tx = true; - schedule_delayed_work(&(fep->delay_work.delay_work), - msecs_to_jiffies(1)); - } + /* Ensure the next write happens after the extended writes */ + wmb(); + /* + * Send it on its way. Tell FEC it's ready, interrupt when done, + * it's the last BD of the frame, and to put the CRC on the end. + */ + bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | + BD_ENET_TX_TC | ((bdp == fep->bd_tx.last) ? BD_SC_WRAP : 0); + + mb(); + prev_status = fec_enet_get_prevdesc(bdp, &fep->bd_tx)->cbd_sc; /* If this was the last BD in the ring, start at the beginning again. */ - if (status & BD_ENET_TX_WRAP) - bdp = fep->tx_bd_base; - else - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); skb_tx_timestamp(skb); - fep->cur_tx = bdp; + fep->bd_tx.cur = bdp; - if (fep->cur_tx == fep->dirty_tx) + if (fep->bd_tx.cur == fep->dirty_tx) netif_stop_queue(ndev); + if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && + !(prev_status & BD_ENET_TX_READY)) { + if (readl(fep->hwp + FEC_X_DES_ACTIVE)) { + fep->delay_work.trig_tx = true; + schedule_delayed_work(&(fep->delay_work.delay_work), + msecs_to_jiffies(1) + 1); + } + } /* Trigger transmission start */ writel(0, fep->hwp + FEC_X_DES_ACTIVE); @@ -425,28 +420,24 @@ static void fec_enet_bd_init(struct net_device *dev) unsigned int i; /* Initialize the receive buffer descriptors. */ - bdp = fep->rx_bd_base; - for (i = 0; i < RX_RING_SIZE; i++) { + bdp = fep->bd_rx.base; + fep->bd_rx.cur = bdp; + for (;;) { + unsigned short status = bdp->cbd_bufaddr ? BD_ENET_RX_EMPTY : 0; /* Initialize the BD for every fragment in the page. */ - if (bdp->cbd_bufaddr) - bdp->cbd_sc = BD_ENET_RX_EMPTY; - else - bdp->cbd_sc = 0; - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + if (bdp == fep->bd_rx.last) { + bdp->cbd_sc = status | BD_SC_WRAP; + break; + } + bdp->cbd_sc = status; + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_rx); } - /* Set the last buffer to wrap */ - bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - bdp->cbd_sc |= BD_SC_WRAP; - - fep->cur_rx = fep->rx_bd_base; - /* ...and the same for transmit */ - bdp = fep->tx_bd_base; - fep->cur_tx = bdp; - for (i = 0; i < TX_RING_SIZE; i++) { - + bdp = fep->bd_tx.base; + fep->bd_tx.cur = bdp; + for (i = 0; ; i++) { /* Initialize the BD for every fragment in the page. */ bdp->cbd_sc = 0; if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { @@ -454,13 +445,14 @@ static void fec_enet_bd_init(struct net_device *dev) fep->tx_skbuff[i] = NULL; } bdp->cbd_bufaddr = 0; - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + if (bdp == fep->bd_tx.last) { + /* Set the last buffer to wrap */ + bdp->cbd_sc = BD_SC_WRAP; + fep->dirty_tx = bdp; + break; + } + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); } - - /* Set the last buffer to wrap */ - bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - bdp->cbd_sc |= BD_SC_WRAP; - fep->dirty_tx = bdp; } /* This function is called to start or restart the FEC during a link @@ -517,14 +509,8 @@ fec_restart(struct net_device *ndev, int duplex) fec_enet_bd_init(ndev); /* Set receive and transmit descriptor base. */ - writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); - if (fep->bufdesc_ex) - writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) - * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); - else - writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) - * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); - + writel(fep->bd_rx.dma, fep->hwp + FEC_R_DES_START); + writel(fep->bd_tx.dma, fep->hwp + FEC_X_DES_START); for (i = 0; i <= TX_RING_MOD_MASK; i++) { if (fep->tx_skbuff[i]) { @@ -543,6 +529,9 @@ fec_restart(struct net_device *ndev, int duplex) writel(0x0, fep->hwp + FEC_X_CNTRL); } +#ifdef FEC_FTRL + writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); +#endif fep->full_duplex = duplex; /* Set MII speed */ @@ -698,11 +687,38 @@ fec_stop(struct net_device *ndev) } } +static uint last_ievents; static void fec_timeout(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); + struct bufdesc *bdp, *bdp1; + unsigned short status; + + pr_err("%s: last=%x %x, mask %x\n", __func__, last_ievents, readl(fep->hwp + FEC_IEVENT), readl(fep->hwp + FEC_IMASK)); + bdp = fep->dirty_tx; + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); + status = bdp->cbd_sc; + if ((status & BD_ENET_TX_READY) == 0) { + if (bdp != fep->bd_tx.cur) { + if (napi_schedule_prep(&fep->napi)) { + /* Disable the RX/TX interrupt */ + writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); + __napi_schedule(&fep->napi); + } + netif_wake_queue(fep->netdev); + pr_err("%s: tx int lost\n", __func__); + return; + } + } + /* Disable all interrupts */ + writel(0, fep->hwp + FEC_IMASK); + bdp1 = bdp; + do { + pr_err("%s: %p %p %x %lx\n", __func__, bdp, fep->bd_tx.cur, bdp->cbd_sc, bdp->cbd_bufaddr); + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); + } while (bdp != bdp1); ndev->stats.tx_errors++; @@ -742,22 +758,34 @@ fec_enet_tx(struct net_device *ndev) bdp = fep->dirty_tx; /* get next bdp of dirty_tx */ - if (bdp->cbd_sc & BD_ENET_TX_WRAP) - bdp = fep->tx_bd_base; - else - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); - - while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { - - /* current queue is empty */ - if (bdp == fep->cur_tx) + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); + + while (bdp != fep->bd_tx.cur) { + status = bdp->cbd_sc; + if (status & BD_ENET_TX_READY) { + /* Test for ERR006358 workaround */ + if (readl(fep->hwp + FEC_X_DES_ACTIVE)) { + const struct platform_device_id *id_entry = + platform_get_device_id(fep->pdev); + if (id_entry->driver_data & FEC_QUIRK_ERR006358) { + fep->delay_work.trig_tx = true; + schedule_delayed_work( + &fep->delay_work.delay_work, + msecs_to_jiffies(1) + 1); + } + } else { + /* ERR006358 has hit, restart tx */ + writel(0, fep->hwp + FEC_X_DES_ACTIVE); + } break; + } + bdp->cbd_sc = (bdp == fep->bd_tx.last) ? BD_SC_WRAP : 0; if (fep->bufdesc_ex) index = (struct bufdesc_ex *)bdp - - (struct bufdesc_ex *)fep->tx_bd_base; + (struct bufdesc_ex *)fep->bd_tx.base; else - index = bdp - fep->tx_bd_base; + index = bdp - fep->bd_tx.base; dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); @@ -816,14 +844,11 @@ fec_enet_tx(struct net_device *ndev) fep->dirty_tx = bdp; /* Update pointer to next buffer descriptor to be transmitted */ - if (status & BD_ENET_TX_WRAP) - bdp = fep->tx_bd_base; - else - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); /* Since we have freed up a buffer, the ring is no longer full */ - if (fep->dirty_tx != fep->cur_tx) { + if (fep->dirty_tx != fep->bd_tx.cur) { if (netif_queue_stopped(ndev)) netif_wake_queue(ndev); } @@ -832,7 +857,8 @@ fec_enet_tx(struct net_device *ndev) } -/* During a receive, the cur_rx points to the current incoming buffer. +/* + * During a receive, the bd_rx.cur points to the current incoming buffer. * When we update through the ring, if the next incoming buffer has * not been given to the system, we just set the empty indicator, * effectively tossing the packet. @@ -852,6 +878,7 @@ fec_enet_rx(struct net_device *ndev, int budget) struct bufdesc_ex *ebdp = NULL; bool vlan_packet_rcvd = false; u16 vlan_tag = 0; + int index = 0; #ifdef CONFIG_M532x flush_cache_all(); @@ -860,7 +887,7 @@ fec_enet_rx(struct net_device *ndev, int budget) /* First, grab all of the stats for the incoming packet. * These get messed up if we get called due to a busy condition. */ - bdp = fep->cur_rx; + bdp = fep->bd_rx.cur; while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { @@ -871,35 +898,36 @@ fec_enet_rx(struct net_device *ndev, int budget) /* Since we have allocated space to hold a complete frame, * the last indicator should be set. */ - if ((status & BD_ENET_RX_LAST) == 0) - netdev_err(ndev, "rcv is not +last\n"); if (!fep->opened) goto rx_processing_done; /* Check for errors. */ + status ^= BD_ENET_RX_LAST; if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | - BD_ENET_RX_CR | BD_ENET_RX_OV)) { + BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | + BD_ENET_RX_CL)) { ndev->stats.rx_errors++; - if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { - /* Frame too long or too short. */ - ndev->stats.rx_length_errors++; - } - if (status & BD_ENET_RX_NO) /* Frame alignment */ - ndev->stats.rx_frame_errors++; - if (status & BD_ENET_RX_CR) /* CRC Error */ - ndev->stats.rx_crc_errors++; - if (status & BD_ENET_RX_OV) /* FIFO overrun */ + if (status & BD_ENET_RX_OV) { + /* FIFO overrun */ ndev->stats.rx_fifo_errors++; - } - - /* Report late collisions as a frame error. - * On this error, the BD is closed, but we don't know what we - * have in the buffer. So, just drop this frame on the floor. - */ - if (status & BD_ENET_RX_CL) { - ndev->stats.rx_errors++; - ndev->stats.rx_frame_errors++; + } else { + if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH + | BD_ENET_RX_LAST)) { + /* Frame too long or too short. */ + ndev->stats.rx_length_errors++; + if (status & BD_ENET_RX_LAST) + netdev_err(ndev, + "rcv is not +last\n"); + } + if (status & BD_ENET_RX_CR) /* CRC Error */ + ndev->stats.rx_crc_errors++; + /* + * Report late collisions as a frame error. + */ + if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) + ndev->stats.rx_frame_errors++; + } goto rx_processing_done; } @@ -907,10 +935,15 @@ fec_enet_rx(struct net_device *ndev, int budget) ndev->stats.rx_packets++; pkt_len = bdp->cbd_datlen; ndev->stats.rx_bytes += pkt_len; - data = (__u8*)__va(bdp->cbd_bufaddr); - dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, - FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); + if (fep->bufdesc_ex) + index = (struct bufdesc_ex *)bdp - + (struct bufdesc_ex *)fep->bd_rx.base; + else + index = bdp - fep->bd_rx.base; + data = fep->rx_skbuff[index]->data; + dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr, + FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) swap_buffer(data, pkt_len); @@ -998,13 +1031,6 @@ fec_enet_rx(struct net_device *ndev, int budget) if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) netdev_err(ndev, "Rx DMA memory map failed\n"); rx_processing_done: - /* Clear the status flags for this buffer */ - status &= ~BD_ENET_RX_STATS; - - /* Mark the buffer empty */ - status |= BD_ENET_RX_EMPTY; - bdp->cbd_sc = status; - if (fep->bufdesc_ex) { struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; @@ -1012,19 +1038,18 @@ rx_processing_done: ebdp->cbd_prot = 0; ebdp->cbd_bdu = 0; } - + mb(); + bdp->cbd_sc = (status & BD_ENET_RX_WRAP) | BD_ENET_RX_EMPTY; /* Update BD pointer to next entry */ - if (status & BD_ENET_RX_WRAP) - bdp = fep->rx_bd_base; - else - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_rx); + /* Doing this here will keep the FEC running while we process * incoming frames. On a heavily loaded network, we should be * able to keep up at the expense of system resources. */ writel(0, fep->hwp + FEC_R_DES_ACTIVE); } - fep->cur_rx = bdp; + fep->bd_rx.cur = bdp; return pkt_received; } @@ -1034,38 +1059,37 @@ fec_enet_interrupt(int irq, void *dev_id) { struct net_device *ndev = dev_id; struct fec_enet_private *fep = netdev_priv(ndev); - uint int_events; + uint int_events, eir; irqreturn_t ret = IRQ_NONE; - do { - int_events = readl(fep->hwp + FEC_IEVENT); - writel(int_events & (~FEC_ENET_TS_TIMER), - fep->hwp + FEC_IEVENT); + while (1) { + eir = readl(fep->hwp + FEC_IEVENT); + int_events = eir & readl(fep->hwp + FEC_IMASK); + if (!int_events) + break; + last_ievents = eir; if ((int_events & FEC_ENET_TS_TIMER) && fep->bufdesc_ex) { ret = IRQ_HANDLED; if (fep->hwts_tx_en_ioctl || fep->hwts_rx_en_ioctl) fep->prtc++; - writel(FEC_ENET_TS_TIMER, fep->hwp + FEC_IEVENT); } - if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { ret = IRQ_HANDLED; - - /* Disable the RX interrupt */ if (napi_schedule_prep(&fep->napi)) { - writel(FEC_RX_DISABLED_IMASK, - fep->hwp + FEC_IMASK); + /* Disable the RX/TX interrupt */ + writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); __napi_schedule(&fep->napi); } } if (int_events & FEC_ENET_MII) { + writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); ret = IRQ_HANDLED; complete(&fep->mdio_done); } - } while (int_events); + } return ret; } @@ -1073,14 +1097,20 @@ fec_enet_interrupt(int irq, void *dev_id) static int fec_enet_rx_napi(struct napi_struct *napi, int budget) { struct net_device *ndev = napi->dev; - int pkts = fec_enet_rx(ndev, budget); struct fec_enet_private *fep = netdev_priv(ndev); + int pkts; + writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT); + pkts = fec_enet_rx(ndev, budget); fec_enet_tx(ndev); if (pkts < budget) { - napi_complete(napi); - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + uint int_events = readl(fep->hwp + FEC_IEVENT); + + if (!(int_events & (FEC_ENET_RXF | FEC_ENET_TXF))) { + napi_complete(napi); + writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + } } return pkts; } @@ -1344,7 +1374,7 @@ static int fec_enet_mii_probe(struct net_device *ndev) return 0; } -static int fec_enet_mii_init(struct platform_device *pdev) +static int fec_enet_mii_init(struct platform_device *pdev, int phy_irq) { static struct mii_bus *fec0_mii_bus; struct net_device *ndev = platform_get_drvdata(pdev); @@ -1417,7 +1447,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) } for (i = 0; i < PHY_MAX_ADDR; i++) - fep->mii_bus->irq[i] = PHY_POLL; + fep->mii_bus->irq[i] = phy_irq; if (mdiobus_register(fep->mii_bus)) goto err_out_free_mdio_irq; @@ -1717,8 +1747,8 @@ static void fec_enet_free_buffers(struct net_device *ndev) struct sk_buff *skb; struct bufdesc *bdp; - bdp = fep->rx_bd_base; - for (i = 0; i < RX_RING_SIZE; i++) { + bdp = fep->bd_rx.base; + for (i = 0; ; i++) { skb = fep->rx_skbuff[i]; if (bdp->cbd_bufaddr) @@ -1726,11 +1756,12 @@ static void fec_enet_free_buffers(struct net_device *ndev) FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); if (skb) dev_kfree_skb(skb); - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + if (bdp == fep->bd_rx.last) + break; + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_rx); } - bdp = fep->tx_bd_base; - for (i = 0; i < TX_RING_SIZE; i++) + for (i = 0; i < fep->bd_tx.ring_size; i++) kfree(fep->tx_bounce[i]); } @@ -1741,8 +1772,8 @@ static int fec_enet_alloc_buffers(struct net_device *ndev) struct sk_buff *skb; struct bufdesc *bdp; - bdp = fep->rx_bd_base; - for (i = 0; i < RX_RING_SIZE; i++) { + bdp = fep->bd_rx.base; + for (i = 0; ; i++) { skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); if (!skb) { fec_enet_free_buffers(ndev); @@ -1757,25 +1788,24 @@ static int fec_enet_alloc_buffers(struct net_device *ndev) netdev_err(ndev, "Rx DMA memory map failed\n"); return -ENOMEM; } - bdp->cbd_sc = BD_ENET_RX_EMPTY; if (fep->bufdesc_ex) { struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; ebdp->cbd_esc = BD_ENET_RX_INT; } - - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + if (bdp == fep->bd_rx.last) { + /* Set the last buffer to wrap. */ + bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_SC_WRAP; + break; + } + bdp->cbd_sc = BD_ENET_RX_EMPTY; + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_rx); } - /* Set the last buffer to wrap. */ - bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - bdp->cbd_sc |= BD_SC_WRAP; - - bdp = fep->tx_bd_base; - for (i = 0; i < TX_RING_SIZE; i++) { + bdp = fep->bd_tx.base; + for (i = 0; ; i++) { fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); - bdp->cbd_sc = 0; bdp->cbd_bufaddr = 0; if (fep->bufdesc_ex) { @@ -1783,13 +1813,14 @@ static int fec_enet_alloc_buffers(struct net_device *ndev) ebdp->cbd_esc = BD_ENET_TX_INT; } - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + if (bdp == fep->bd_tx.last) { + /* Set the last buffer to wrap. */ + bdp->cbd_sc = BD_SC_WRAP; + break; + } + bdp->cbd_sc = 0; + bdp = fec_enet_get_nextdesc(bdp, &fep->bd_tx); } - - /* Set the last buffer to wrap. */ - bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - bdp->cbd_sc |= BD_SC_WRAP; - return 0; } @@ -2041,9 +2072,11 @@ static int fec_enet_init(struct net_device *ndev) const struct platform_device_id *id_entry = platform_get_device_id(fep->pdev); struct bufdesc *cbd_base; + unsigned desc_size = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) + : sizeof(struct bufdesc); /* Allocate memory for buffer descriptors. */ - cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, + cbd_base = dma_alloc_coherent(&fep->pdev->dev, PAGE_SIZE, &fep->bd_rx.dma, GFP_KERNEL); if (!cbd_base) return -ENOMEM; @@ -2055,13 +2088,22 @@ static int fec_enet_init(struct net_device *ndev) /* Get the Ethernet address */ fec_get_mac(ndev); - /* Set receive and transmit descriptor base. */ - fep->rx_bd_base = cbd_base; - if (fep->bufdesc_ex) - fep->tx_bd_base = (struct bufdesc *) - (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); - else - fep->tx_bd_base = cbd_base + RX_RING_SIZE; + /* init the tx & rx rings */ + fep->bd_rx.base = cbd_base; + fep->bd_rx.last = (struct bufdesc *)(((unsigned)cbd_base) + + (RX_RING_SIZE - 1) * desc_size); + fep->bd_rx.cur = fep->bd_rx.base; + fep->bd_rx.ring_size = RX_RING_SIZE; + fep->bd_rx.desc_size = desc_size; + + fep->bd_tx.base = (struct bufdesc *)(((unsigned)cbd_base) + + RX_RING_SIZE * desc_size); + fep->bd_tx.last = (struct bufdesc *)(((unsigned)fep->bd_tx.base) + + (TX_RING_SIZE - 1) * desc_size); + fep->bd_tx.cur = fep->bd_tx.base; + fep->bd_tx.dma = fep->bd_rx.dma + RX_RING_SIZE * desc_size; + fep->bd_tx.ring_size = TX_RING_SIZE; + fep->bd_tx.desc_size = desc_size; /* The FEC Ethernet specific entries in the device structure */ ndev->watchdog_timeo = TX_TIMEOUT; @@ -2148,6 +2190,8 @@ fec_probe(struct platform_device *pdev) struct resource *r; const struct of_device_id *of_id; static int dev_id; + int phy_irq = PHY_POLL; + struct device_node *np; of_id = of_match_device(fec_dt_ids, &pdev->dev); if (of_id) @@ -2201,6 +2245,16 @@ fec_probe(struct platform_device *pdev) } else { fep->phy_interface = ret; } + np = of_get_child_by_name(pdev->dev.of_node, "phy_int"); + if (!np) { + pr_warn("%s: could not find phy node\n", + of_node_full_name(pdev->dev.of_node)); + } else { + phy_irq = irq_of_parse_and_map(np, 0); + pr_info("phyirq=%d\n", phy_irq); + if (phy_irq <= 0) + phy_irq = PHY_POLL; + } fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); if (IS_ERR(fep->clk_ipg)) { @@ -2268,7 +2322,7 @@ fec_probe(struct platform_device *pdev) } } - ret = fec_enet_mii_init(pdev); + ret = fec_enet_mii_init(pdev, phy_irq); if (ret) goto failed_mii_init; diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c index 0f6eb2b6d381..24da631e8713 100644 --- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c +++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c @@ -59,6 +59,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = { {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)}, {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334)}, {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4335)}, + {SDIO_DEVICE(0xe0f8, 0x5332)}, { /* end: all zeroes */ }, }; MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids); diff --git a/drivers/net/wireless/ti/wlcore/sdio.c b/drivers/net/wireless/ti/wlcore/sdio.c index 29ef2492951f..53bbb2816d2f 100644 --- a/drivers/net/wireless/ti/wlcore/sdio.c +++ b/drivers/net/wireless/ti/wlcore/sdio.c @@ -30,7 +30,7 @@ #include <linux/mmc/sdio_ids.h> #include <linux/mmc/card.h> #include <linux/mmc/host.h> -#include <linux/gpio.h> +#include <linux/of_irq.h> #include <linux/wl12xx.h> #include <linux/pm_runtime.h> #include <linux/printk.h> @@ -214,6 +214,43 @@ static struct wl1271_if_operations sdio_ops = { .set_block_size = wl1271_sdio_set_block_size, }; +static struct wl12xx_platform_data *wlcore_get_pdata_from_of(struct device *dev) +{ + struct wl12xx_platform_data *pdata; + struct device_node *np = dev->of_node; + + if (!np) { + np = of_find_matching_node(NULL, dev->driver->of_match_table); + if (!np) { + dev_notice(dev, "device tree node not available\n"); + pdata = ERR_PTR(-ENODEV); + goto out; + } + } + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(dev, "can't allocate platform data\n"); + pdata = ERR_PTR(-ENODEV); + goto out; + } + + pdata->irq = irq_of_parse_and_map(np, 0); + if (pdata->irq < 0) { + dev_err(dev, "can't get interrupt gpio from the device tree\n"); + goto out_free; + } + pdata->board_ref_clock = WL12XX_REFCLOCK_38; /* 38.4 MHz */ + goto out; + +out_free: + kfree(pdata); + pdata = ERR_PTR(-ENODEV); + +out: + return pdata; +} + static int wl1271_probe(struct sdio_func *func, const struct sdio_device_id *id) { @@ -248,11 +285,23 @@ static int wl1271_probe(struct sdio_func *func, /* Use block mode for transferring over one block size of data */ func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; + /* The pdata allocated here is freed when the device is freed, + * so we don't need an additional out label to free it in case + * of error further on. + */ + + /* Try to get legacy platform data from the board file */ pdev_data->pdata = wl12xx_get_platform_data(); if (IS_ERR(pdev_data->pdata)) { - ret = PTR_ERR(pdev_data->pdata); - dev_err(glue->dev, "missing wlan platform data: %d\n", ret); - goto out_free_glue; + dev_info(&func->dev, + "legacy platform data not found, trying device tree\n"); + + pdev_data->pdata = wlcore_get_pdata_from_of(&func->dev); + if (IS_ERR(pdev_data->pdata)) { + ret = PTR_ERR(pdev_data->pdata); + dev_err(&func->dev, "can't get platform data\n"); + goto out_free_glue; + } } /* if sdio can keep power while host is suspended, enable wow */ @@ -386,16 +435,25 @@ static const struct dev_pm_ops wl1271_sdio_pm_ops = { }; #endif +static const struct of_device_id wlcore_sdio_of_match_table[] = { + { .compatible = "ti,wilink6" }, + { .compatible = "ti,wilink7" }, + { .compatible = "ti,wilink8" }, + { } +}; +MODULE_DEVICE_TABLE(of, wlcore_sdio_of_match_table); + static struct sdio_driver wl1271_sdio_driver = { .name = "wl1271_sdio", .id_table = wl1271_devices, .probe = wl1271_probe, .remove = wl1271_remove, -#ifdef CONFIG_PM .drv = { +#ifdef CONFIG_PM .pm = &wl1271_sdio_pm_ops, - }, #endif + .of_match_table = of_match_ptr(wlcore_sdio_of_match_table), + }, }; static int __init wl1271_init(void) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 120714876e83..95b149a80964 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -20,6 +20,10 @@ config PCI_IMX6 select PCIEPORTBUS select PCIE_DW +config PCI_FORCE_GEN1 + bool "Force GEN1 speed on the PCIe controller (e.g. don't allow GEN2)" + depends on PCI_IMX6 + config EP_MODE_IN_EP_RC_SYS bool "PCI Express EP mode in the IMX6 RC/EP interconnection system" depends on PCI_IMX6 diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 8741ab67b72d..44213e110c5b 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -44,6 +44,7 @@ static u32 test_region_size = SZ_2M; struct imx6_pcie { int reset_gpio; + int reset_ep_gpio; int power_on_gpio; int wake_up_gpio; int disable_gpio; @@ -56,10 +57,18 @@ struct imx6_pcie { void __iomem *mem_base; }; +/* PCIe Root Complex registers (memory-mapped) */ +#define PCIE_RC_LCR 0x7c +#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 +#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 +#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf + /* PCIe Port Logic registers (memory-mapped) */ #define PL_OFFSET 0x700 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) +#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 @@ -71,6 +80,9 @@ struct imx6_pcie { #define PCIE_PHY_STAT (PL_OFFSET + 0x110) #define PCIE_PHY_STAT_ACK_LOC 16 +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) + /* PHY registers (not memory-mapped) */ #define PCIE_PHY_RX_ASIC_OUT 0x100D @@ -215,6 +227,18 @@ static int imx6q_pcie_abort_handler(unsigned long addr, return 0; } +static int imx6_pcie_assert_core_reset(struct pcie_port *pp) +{ + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); + + return 0; +} + static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) { struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); @@ -241,13 +265,10 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie_ref; } - if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS) - && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) { - ret = clk_prepare_enable(imx6_pcie->lvds_gate); - if (ret) { - dev_err(pp->dev, "unable to enable lvds_gate\n"); - goto err_lvds_gate; - } + ret = clk_prepare_enable(imx6_pcie->lvds_gate); + if (ret) { + dev_err(pp->dev, "unable to enable lvds_gate\n"); + goto err_lvds_gate; } ret = clk_prepare_enable(imx6_pcie->pcie_axi); @@ -259,12 +280,21 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) /* allow the clocks to stabilize */ usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { + if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) + gpio_set_value(imx6_pcie->reset_ep_gpio, 1); gpio_set_value(imx6_pcie->reset_gpio, 0); msleep(100); gpio_set_value(imx6_pcie->reset_gpio, 1); + msleep(1); + if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) + gpio_set_value(imx6_pcie->reset_ep_gpio, 0); + } else if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) { + gpio_set_value(imx6_pcie->reset_ep_gpio, 1); + msleep(100); + gpio_set_value(imx6_pcie->reset_ep_gpio, 0); } - return 0; err_pcie_axi: @@ -319,52 +349,168 @@ static irqreturn_t imx_pcie_msi_irq_handler(int irq, void *arg) return IRQ_HANDLED; } -static void imx6_pcie_host_init(struct pcie_port *pp) +static int imx6_pcie_wait_for_link(struct pcie_port *pp) { - int count = 0; - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); + int count = 200; - imx6_pcie_init_phy(pp); + while (!dw_pcie_link_up(pp)) { + usleep_range(100, 1000); + if (--count) + continue; + + dev_err(pp->dev, "phy link never came up\n"); + dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", + readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), + readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); + return -EINVAL; + } - imx6_pcie_deassert_core_reset(pp); + return 0; +} - dw_pcie_setup_rc(pp); +static int imx6_pcie_start_link(struct pcie_port *pp) +{ + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); + uint32_t tmp; + int ret; +#ifndef CONFIG_PCI_FORCE_GEN1 + int count; +#endif + /* + * Force Gen1 operation when starting the link. In case the link is + * started in Gen2 mode, there is a possibility the devices on the + * bus will not be detected at all. This happens with PCIe switches. + */ + tmp = readl(pp->dbi_base + PCIE_RC_LCR); + tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; + tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; + writel(tmp, pp->dbi_base + PCIE_RC_LCR); + /* Start LTSSM. */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); - while (!dw_pcie_link_up(pp)) { - usleep_range(100, 1000); - count++; - if (count >= 200) { - dev_err(pp->dev, "phy link never came up\n"); - dev_dbg(pp->dev, - "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", - readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), - readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); - return; + ret = imx6_pcie_wait_for_link(pp); + if (ret) + return ret; +#ifndef CONFIG_PCI_FORCE_GEN1 + /* Allow Gen2 mode after the link is up. */ + tmp = readl(pp->dbi_base + PCIE_RC_LCR); + tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; + tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; + writel(tmp, pp->dbi_base + PCIE_RC_LCR); + + /* + * Start Directed Speed Change so the best possible speed both link + * partners support can be negotiated. + */ + tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + tmp |= PORT_LOGIC_SPEED_CHANGE; + writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + + count = 200; + while (1) { + tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + /* Test if the speed change finished. */ + if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) + break; + if (count-- == 0) { + dev_err(pp->dev, "Change to gen 2 speed timeout\n"); + return -EINVAL; } + usleep_range(100, 1000); } + /* Make sure link training is finished as well! */ + ret = imx6_pcie_wait_for_link(pp); +#else + dev_info(pp->dev, "Configuration forces GEN1\n"); +#endif /* CONFIG_PCI_FORCE_GEN1 */ + + if (ret) { + dev_err(pp->dev, "Failed to bring link up!\n"); + } else { + tmp = readl(pp->dbi_base + 0x80); + dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf); + } + + return ret; +} + +static void imx6_pcie_host_init(struct pcie_port *pp) +{ + imx6_pcie_assert_core_reset(pp); + + imx6_pcie_init_phy(pp); + + imx6_pcie_deassert_core_reset(pp); + + dw_pcie_setup_rc(pp); + imx6_pcie_start_link(pp); + if (IS_ENABLED(CONFIG_PCI_MSI)) { pp->quirks |= DW_PCIE_QUIRK_NO_MSI_VEC; pp->quirks |= DW_PCIE_QUIRK_MSI_SELF_EN; dw_pcie_msi_init(pp); } +} + +static void imx6_pcie_reset_phy(struct pcie_port *pp) +{ + uint32_t temp; + + pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp); + temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | + PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp); - return; + /* BUG: scheduling while atomic: swapper/0/1/0x00000002, use udelay instead of usleep_range*/ + udelay(2000); + + pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp); + temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | + PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp); } static int imx6_pcie_link_up(struct pcie_port *pp) { - u32 rc, ltssm, rx_valid, temp; - - /* link is debug bit 36, debug register 1 starts at bit 32 */ - rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); - if (rc) - return -EAGAIN; + u32 rc, debug_r0, rx_valid; + int count = 5; /* + * Test if the PHY reports that the link is up and also that the LTSSM + * training finished. There are three possible states of the link when + * this code is called: + * 1) The link is DOWN (unlikely) + * The link didn't come up yet for some reason. This usually means + * we have a real problem somewhere. Reset the PHY and exit. This + * state calls for inspection of the DEBUG registers. + * 2) The link is UP, but still in LTSSM training + * Wait for the training to finish, which should take a very short + * time. If the training does not finish, we have a problem and we + * need to inspect the DEBUG registers. If the training does finish, + * the link is up and operating correctly. + * 3) The link is UP and no longer in LTSSM training + * The link is up and operating correctly. + */ + while (1) { + rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); + if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP)) + break; + if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) + return 1; + if (!count--) + break; + dev_dbg(pp->dev, "Link is up, but still in training\n"); + /* + * Wait a little bit, then re-check if the link finished + * the training. + */ + /* BUG: scheduling while atomic: swapper/0/1/0x00000002, use udelay instead of usleep_range*/ + udelay(1000); + } + /* * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). * If (MAC/LTSSM.state == Recovery.RcvrLock) @@ -372,31 +518,18 @@ static int imx6_pcie_link_up(struct pcie_port *pp) * to gen2 is stuck */ pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); - ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; + debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0); if (rx_valid & 0x01) return 0; - if (ltssm != 0x0d) + if ((debug_r0 & 0x3f) != 0x0d) return 0; dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); + dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc); - pcie_phy_read(pp->dbi_base, - PHY_RX_OVRD_IN_LO, &temp); - temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN - | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(pp->dbi_base, - PHY_RX_OVRD_IN_LO, temp); - - usleep_range(2000, 3000); - - pcie_phy_read(pp->dbi_base, - PHY_RX_OVRD_IN_LO, &temp); - temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN - | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(pp->dbi_base, - PHY_RX_OVRD_IN_LO, temp); + imx6_pcie_reset_phy(pp); return 0; } @@ -618,16 +751,9 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) "imprecise external abort"); dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!dbi_base) { - dev_err(&pdev->dev, "dbi_base memory resource not found\n"); - return -ENODEV; - } - pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); - if (IS_ERR(pp->dbi_base)) { - ret = PTR_ERR(pp->dbi_base); - goto err; - } + if (IS_ERR(pp->dbi_base)) + return PTR_ERR(pp->dbi_base); /* Fetch GPIOs */ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); @@ -638,7 +764,18 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) "PCIe reset"); if (ret) { dev_err(&pdev->dev, "unable to get reset gpio\n"); - goto err; + return ret; + } + } + imx6_pcie->reset_ep_gpio = of_get_named_gpio(np, "reset-ep-gpio", 0); + if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) { + ret = devm_gpio_request_one(&pdev->dev, + imx6_pcie->reset_ep_gpio, + GPIOF_OUT_INIT_HIGH, + "PCIe EP reset"); + if (ret) { + dev_err(&pdev->dev, "unable to get reset end point gpio\n"); + return ret; } } @@ -650,7 +787,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) "PCIe power enable"); if (ret) { dev_err(&pdev->dev, "unable to get power-on gpio\n"); - goto err; + return ret; } } @@ -662,7 +799,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) "PCIe wake up"); if (ret) { dev_err(&pdev->dev, "unable to get wake-up gpio\n"); - goto err; + return ret; } } @@ -674,7 +811,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) "PCIe disable endpoint"); if (ret) { dev_err(&pdev->dev, "unable to get disable-ep gpio\n"); - goto err; + return ret; } } @@ -683,32 +820,28 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) if (IS_ERR(imx6_pcie->lvds_gate)) { dev_err(&pdev->dev, "lvds_gate clock select missing or invalid\n"); - ret = PTR_ERR(imx6_pcie->lvds_gate); - goto err; + return PTR_ERR(imx6_pcie->lvds_gate); } imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m"); if (IS_ERR(imx6_pcie->sata_ref_100m)) { dev_err(&pdev->dev, "sata_ref_100m clock source missing or invalid\n"); - ret = PTR_ERR(imx6_pcie->sata_ref_100m); - goto err; + return PTR_ERR(imx6_pcie->sata_ref_100m); } imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m"); if (IS_ERR(imx6_pcie->pcie_ref_125m)) { dev_err(&pdev->dev, "pcie_ref_125m clock source missing or invalid\n"); - ret = PTR_ERR(imx6_pcie->pcie_ref_125m); - goto err; + return PTR_ERR(imx6_pcie->pcie_ref_125m); } imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi"); if (IS_ERR(imx6_pcie->pcie_axi)) { dev_err(&pdev->dev, "pcie_axi clock source missing or invalid\n"); - ret = PTR_ERR(imx6_pcie->pcie_axi); - goto err; + return PTR_ERR(imx6_pcie->pcie_axi); } /* Grab GPR config register range */ @@ -716,8 +849,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (IS_ERR(imx6_pcie->iomuxc_gpr)) { dev_err(&pdev->dev, "unable to find iomuxc registers\n"); - ret = PTR_ERR(imx6_pcie->iomuxc_gpr); - goto err; + return PTR_ERR(imx6_pcie->iomuxc_gpr); } if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) { @@ -727,16 +859,14 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) test_region_size, GFP_KERNEL); if (!test_reg1) { pr_err("pcie ep: can't alloc the test reg1.\n"); - ret = PTR_ERR(test_reg1); - goto err; + return PTR_ERR(test_reg1); } test_reg2 = devm_kzalloc(&pdev->dev, test_region_size, GFP_KERNEL); if (!test_reg2) { pr_err("pcie ep: can't alloc the test reg2.\n"); - ret = PTR_ERR(test_reg1); - goto err; + return PTR_ERR(test_reg2); } pcie_arb_base_addr = ioremap_cached(0x01000000, @@ -744,8 +874,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) if (!pcie_arb_base_addr) { pr_err("error with ioremap in ep selftest\n"); - ret = PTR_ERR(pcie_arb_base_addr); - goto err; + return PTR_ERR(pcie_arb_base_addr); } for (i = 0; i < test_region_size; i = i + 4) { @@ -868,7 +997,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) } else { ret = imx6_add_pcie_port(pp, pdev); if (ret < 0) - goto err; + return ret; platform_set_drvdata(pdev, imx6_pcie); @@ -876,9 +1005,6 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) imx_pcie_regions_setup(&pdev->dev); } return 0; - -err: - return ret; } static const struct of_device_id imx6_pcie_of_match[] = { diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index df4655c5c138..ae2167b8bc17 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2783,6 +2783,15 @@ static void fixup_ti816x_class(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); +/* TW6869 Frame grabber has same problem as ti816x */ +static void fixup_tw6869_class(struct pci_dev* dev) +{ + dev_info(&dev->dev, "Setting PCI class for tw6869 PCIe device\n"); + dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; +} +DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, + PCI_CLASS_NOT_DEFINED, 0, fixup_tw6869_class); + /* Some PCIe devices do not work reliably with the claimed maximum * payload size supported. */ diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 45ad14896af5..06bd8ce30745 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -33,13 +33,17 @@ #define MX3_PWMSAR 0x0C /* PWM Sample Register */ #define MX3_PWMPR 0x10 /* PWM Period Register */ #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define MX3_PWMCR_STOPEN (1 << 25) #define MX3_PWMCR_DOZEEN (1 << 24) #define MX3_PWMCR_WAITEN (1 << 23) #define MX3_PWMCR_DBGEN (1 << 22) -#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) -#define MX3_PWMCR_CLKSRC_IPG (1 << 16) #define MX3_PWMCR_EN (1 << 0) +#define MX3_PWMCR_CLKSRC(src) (src << 16) +#define CLKSRC_IPG 1 +#define CLKSRC_PER 2 +#define CLKSRC_32k 3 + struct imx_chip { struct clk *clk_per; struct clk *clk_ipg; @@ -102,38 +106,80 @@ static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable) static int imx_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { - struct imx_chip *imx = to_imx_chip(chip); + unsigned src, best_src = 0; + unsigned long best_rate = ~0; + unsigned long best_error = ~0; + unsigned long best_cycles = 0, best_prescale = 0; + unsigned long duty_cycles; unsigned long long c; - unsigned long period_cycles, duty_cycles, prescale; u32 cr; + struct imx_chip *imx = to_imx_chip(chip); - c = clk_get_rate(imx->clk_per); - c = c * period_ns; - do_div(c, 1000000000); - period_cycles = c; - - prescale = period_cycles / 0x10000 + 1; - - period_cycles /= prescale; - c = (unsigned long long)period_cycles * duty_ns; + for (src = CLKSRC_IPG; src <= CLKSRC_32k; src++) { + unsigned long rate; + unsigned long ns, error; + unsigned long prescale, cycles; + + switch (src) { + case CLKSRC_IPG: + rate = clk_get_rate(imx->clk_ipg); + break; + case CLKSRC_PER: + rate = clk_get_rate(imx->clk_per); + break; + case CLKSRC_32k: + rate = 32768; + } + c = rate; + c = c * (unsigned)period_ns + 500000000; + do_div(c, 1000000000); + cycles = c; + + prescale = cycles / 0x10000 + 1; + if (prescale > 4096) + prescale = 4096; + + cycles /= prescale; + if (cycles < 2) + cycles = 2; + else if (cycles > 0x10001) + cycles = 0x10001; + + c = prescale * cycles; + c = c * 1000000000 + (rate >> 1); + do_div(c, rate); + ns = c; + error = (ns >= (unsigned)period_ns) ? (ns - period_ns) : + period_ns - ns; + pr_debug("error=%ld, ns=%ld, period_ns=%d cycles=%ld\n", + error, ns, period_ns, cycles); + if (best_error >= error) { + if ((best_error > error) || (best_rate > rate)) { + best_error = error; + best_cycles = cycles; + best_prescale = prescale; + best_src = src; + best_rate = rate; + } + } + } + c = (unsigned long long)best_cycles * (unsigned)duty_ns; do_div(c, period_ns); duty_cycles = c; + if ((duty_cycles == 0) && duty_ns) + duty_cycles = 1; + pr_debug("best_src=%d best_cycles=0x%lx\n", best_src, best_cycles); + writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); /* * according to imx pwm RM, the real period value should be * PERIOD value in PWMPR plus 2. */ - if (period_cycles > 2) - period_cycles -= 2; - else - period_cycles = 0; - - writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); - writel(period_cycles, imx->mmio_base + MX3_PWMPR); + writel(best_cycles - 2, imx->mmio_base + MX3_PWMPR); - cr = MX3_PWMCR_PRESCALER(prescale) | - MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | - MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH; + cr = MX3_PWMCR_PRESCALER(best_prescale) | + MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | + MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC(best_src); if (test_bit(PWMF_ENABLED, &pwm->flags)) cr |= MX3_PWMCR_EN; diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator/88pm8607.c index 493948a38fca..3a2bb5d9098e 100644 --- a/drivers/regulator/88pm8607.c +++ b/drivers/regulator/88pm8607.c @@ -347,7 +347,7 @@ static int pm8607_regulator_probe(struct platform_device *pdev) struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent); struct pm8607_regulator_info *info = NULL; struct regulator_init_data *pdata = pdev->dev.platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct resource *res; int i; diff --git a/drivers/regulator/aat2870-regulator.c b/drivers/regulator/aat2870-regulator.c index 8b5876356db9..663a88763553 100644 --- a/drivers/regulator/aat2870-regulator.c +++ b/drivers/regulator/aat2870-regulator.c @@ -162,7 +162,7 @@ static struct aat2870_regulator *aat2870_get_regulator(int id) static int aat2870_regulator_probe(struct platform_device *pdev) { struct aat2870_regulator *ri; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; ri = aat2870_get_regulator(pdev->id); diff --git a/drivers/regulator/ab3100.c b/drivers/regulator/ab3100.c index 3be9e46594a1..16d71b34bd7f 100644 --- a/drivers/regulator/ab3100.c +++ b/drivers/regulator/ab3100.c @@ -503,7 +503,7 @@ static int ab3100_regulator_register(struct platform_device *pdev, struct regulator_desc *desc; struct ab3100_regulator *reg; struct regulator_dev *rdev; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int err, i; for (i = 0; i < AB3100_NUM_REGULATORS; i++) { diff --git a/drivers/regulator/ab8500-ext.c b/drivers/regulator/ab8500-ext.c index b4d45472aae6..95cc9697bd2f 100644 --- a/drivers/regulator/ab8500-ext.c +++ b/drivers/regulator/ab8500-ext.c @@ -315,7 +315,7 @@ int ab8500_ext_regulator_init(struct platform_device *pdev) struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); struct ab8500_platform_data *ppdata; struct ab8500_regulator_platform_data *pdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int i, err; if (!ab8500) { diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c index f6656b8c28b6..0c9930469d78 100644 --- a/drivers/regulator/ab8500.c +++ b/drivers/regulator/ab8500.c @@ -3032,7 +3032,7 @@ static int ab8500_regulator_register(struct platform_device *pdev, { struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); struct ab8500_regulator_info *info = NULL; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int err; /* assign per-regulator data */ diff --git a/drivers/regulator/ad5398.c b/drivers/regulator/ad5398.c index 6b981b5faa70..4c6ff962c1e4 100644 --- a/drivers/regulator/ad5398.c +++ b/drivers/regulator/ad5398.c @@ -215,7 +215,7 @@ static int ad5398_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct regulator_init_data *init_data = client->dev.platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct ad5398_chip_info *chip; const struct ad5398_current_data_format *df = (struct ad5398_current_data_format *)id->driver_data; diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c index c91ab175a58e..6f5d71bcf060 100644 --- a/drivers/regulator/anatop-regulator.c +++ b/drivers/regulator/anatop-regulator.c @@ -204,7 +204,7 @@ static int anatop_regulator_probe(struct platform_device *pdev) struct regulator_dev *rdev; struct anatop_regulator *sreg; struct regulator_init_data *initdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int ret = 0; initdata = of_get_regulator_init_data(dev, np); diff --git a/drivers/regulator/arizona-ldo1.c b/drivers/regulator/arizona-ldo1.c index 81d8681c3195..c5886323b32f 100644 --- a/drivers/regulator/arizona-ldo1.c +++ b/drivers/regulator/arizona-ldo1.c @@ -184,7 +184,7 @@ static int arizona_ldo1_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); const struct regulator_desc *desc; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct arizona_ldo1 *ldo1; int ret; diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index e87536bf0bed..eaa3c862a4a2 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -189,7 +189,7 @@ static const struct regulator_init_data arizona_micsupp_default = { static int arizona_micsupp_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct arizona_micsupp *micsupp; int ret; diff --git a/drivers/regulator/as3711-regulator.c b/drivers/regulator/as3711-regulator.c index 3da6bd6950cf..ffac74d83eee 100644 --- a/drivers/regulator/as3711-regulator.c +++ b/drivers/regulator/as3711-regulator.c @@ -330,7 +330,7 @@ static int as3711_regulator_probe(struct platform_device *pdev) struct as3711_regulator_pdata *pdata = dev_get_platdata(&pdev->dev); struct as3711 *as3711 = dev_get_drvdata(pdev->dev.parent); struct regulator_init_data *reg_data; - struct regulator_config config = {.dev = &pdev->dev,}; + struct regulator_config config = {.dev = &pdev->dev, .ena_gpio = -ENODEV}; struct as3711_regulator *reg = NULL; struct as3711_regulator *regs; struct device_node *of_node[AS3711_REGULATOR_NUM] = {}; diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index d9081cb3f751..1552910a83eb 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -3611,7 +3611,7 @@ regulator_register(const struct regulator_desc *regulator_desc, dev_set_drvdata(&rdev->dev, rdev); - if (config->ena_gpio && gpio_is_valid(config->ena_gpio)) { + if (gpio_is_valid(config->ena_gpio)) { ret = regulator_ena_gpio_request(rdev, config); if (ret != 0) { rdev_err(rdev, "Failed to request enable GPIO%d: %d\n", diff --git a/drivers/regulator/da903x.c b/drivers/regulator/da903x.c index 2afa5730f324..5212b6b70b96 100644 --- a/drivers/regulator/da903x.c +++ b/drivers/regulator/da903x.c @@ -464,7 +464,7 @@ static int da903x_regulator_probe(struct platform_device *pdev) { struct da903x_regulator_info *ri = NULL; struct regulator_dev *rdev; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; ri = find_regulator_info(pdev->id); if (ri == NULL) { diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c index 96b569abb46c..e78ae18fe90f 100644 --- a/drivers/regulator/da9052-regulator.c +++ b/drivers/regulator/da9052-regulator.c @@ -338,7 +338,7 @@ static inline struct da9052_regulator_info *find_regulator_info(u8 chip_id, static int da9052_regulator_probe(struct platform_device *pdev) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct da9052_regulator *regulator; struct da9052 *da9052; struct da9052_pdata *pdata; diff --git a/drivers/regulator/da9055-regulator.c b/drivers/regulator/da9055-regulator.c index 30221099d09c..115f29c82957 100644 --- a/drivers/regulator/da9055-regulator.c +++ b/drivers/regulator/da9055-regulator.c @@ -532,7 +532,7 @@ static inline struct da9055_regulator_info *find_regulator_info(int id) static int da9055_regulator_probe(struct platform_device *pdev) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct da9055_regulator *regulator; struct da9055 *da9055 = dev_get_drvdata(pdev->dev.parent); struct da9055_pdata *pdata = da9055->dev->platform_data; diff --git a/drivers/regulator/db8500-prcmu.c b/drivers/regulator/db8500-prcmu.c index a53c11a529d5..72b13c479f1d 100644 --- a/drivers/regulator/db8500-prcmu.c +++ b/drivers/regulator/db8500-prcmu.c @@ -418,7 +418,7 @@ static int db8500_regulator_register(struct platform_device *pdev, struct device_node *np) { struct dbx500_regulator_info *info; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int err; /* assign per-regulator data */ diff --git a/drivers/regulator/dummy.c b/drivers/regulator/dummy.c index df9f42524abb..c5b4eeb05b8b 100644 --- a/drivers/regulator/dummy.c +++ b/drivers/regulator/dummy.c @@ -39,7 +39,7 @@ static struct regulator_desc dummy_desc = { static int dummy_regulator_probe(struct platform_device *pdev) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int ret; config.dev = &pdev->dev; diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index f0e1ae52bb05..d9a65ec4f50b 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -233,7 +233,7 @@ static int fan53555_regulator_probe(struct i2c_client *client, { struct fan53555_device_info *di; struct fan53555_platform_data *pdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; unsigned int val; int ret; diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c index e5c03b534fae..a61185c98236 100644 --- a/drivers/regulator/fixed.c +++ b/drivers/regulator/fixed.c @@ -138,7 +138,7 @@ static int reg_fixed_voltage_probe(struct platform_device *pdev) { struct fixed_voltage_config *config; struct fixed_voltage_data *drvdata; - struct regulator_config cfg = { }; + struct regulator_config cfg = { .ena_gpio = -ENODEV }; int ret; if (pdev->dev.of_node) { diff --git a/drivers/regulator/gpio-regulator.c b/drivers/regulator/gpio-regulator.c index 9d39eb4aafa3..0b7371a41d98 100644 --- a/drivers/regulator/gpio-regulator.c +++ b/drivers/regulator/gpio-regulator.c @@ -222,7 +222,7 @@ static int gpio_regulator_probe(struct platform_device *pdev) struct gpio_regulator_config *config = pdev->dev.platform_data; struct device_node *np = pdev->dev.of_node; struct gpio_regulator_data *drvdata; - struct regulator_config cfg = { }; + struct regulator_config cfg = { .ena_gpio = -ENODEV }; int ptr, ret, state; if (np) { diff --git a/drivers/regulator/isl6271a-regulator.c b/drivers/regulator/isl6271a-regulator.c index d1e5bee2a26b..92cf9f48ad4b 100644 --- a/drivers/regulator/isl6271a-regulator.c +++ b/drivers/regulator/isl6271a-regulator.c @@ -109,7 +109,7 @@ static const struct regulator_desc isl_rd[] = { static int isl6271a_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_init_data *init_data = i2c->dev.platform_data; struct isl_pmic *pmic; int err, i; diff --git a/drivers/regulator/lp3971.c b/drivers/regulator/lp3971.c index d8af9e773310..f06389c81c6c 100644 --- a/drivers/regulator/lp3971.c +++ b/drivers/regulator/lp3971.c @@ -393,7 +393,7 @@ static int setup_regulators(struct lp3971 *lp3971, /* Instantiate the regulators */ for (i = 0; i < pdata->num_regulators; i++) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct lp3971_regulator_subdev *reg = &pdata->regulators[i]; config.dev = lp3971->dev; diff --git a/drivers/regulator/lp3972.c b/drivers/regulator/lp3972.c index 61e4cf9edf6e..b0e8924c24b7 100644 --- a/drivers/regulator/lp3972.c +++ b/drivers/regulator/lp3972.c @@ -489,7 +489,7 @@ static int setup_regulators(struct lp3972 *lp3972, /* Instantiate the regulators */ for (i = 0; i < pdata->num_regulators; i++) { struct lp3972_regulator_subdev *reg = &pdata->regulators[i]; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; config.dev = lp3972->dev; config.init_data = reg->initdata; diff --git a/drivers/regulator/lp872x.c b/drivers/regulator/lp872x.c index f5fc4a142cdf..1925ab508f70 100644 --- a/drivers/regulator/lp872x.c +++ b/drivers/regulator/lp872x.c @@ -780,7 +780,7 @@ static struct regulator_init_data static int lp872x_regulator_register(struct lp872x *lp) { struct regulator_desc *desc; - struct regulator_config cfg = { }; + struct regulator_config cfg = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; int i, ret; diff --git a/drivers/regulator/lp8755.c b/drivers/regulator/lp8755.c index f0f6ea05065b..ed262d3bfe62 100644 --- a/drivers/regulator/lp8755.c +++ b/drivers/regulator/lp8755.c @@ -328,7 +328,7 @@ static int lp8755_regulator_init(struct lp8755_chip *pchip) { int ret, icnt, buck_num; struct lp8755_platform_data *pdata = pchip->pdata; - struct regulator_config rconfig = { }; + struct regulator_config rconfig = { .ena_gpio = -ENODEV }; rconfig.regmap = pchip->regmap; rconfig.dev = pchip->dev; diff --git a/drivers/regulator/lp8788-buck.c b/drivers/regulator/lp8788-buck.c index eb1e1e88ae51..7497c761464a 100644 --- a/drivers/regulator/lp8788-buck.c +++ b/drivers/regulator/lp8788-buck.c @@ -493,7 +493,7 @@ static int lp8788_buck_probe(struct platform_device *pdev) struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent); int id = pdev->id; struct lp8788_buck *buck; - struct regulator_config cfg = { }; + struct regulator_config cfg = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; int ret; diff --git a/drivers/regulator/lp8788-ldo.c b/drivers/regulator/lp8788-ldo.c index 0ce2c4c194b3..fd2d3f10ae67 100644 --- a/drivers/regulator/lp8788-ldo.c +++ b/drivers/regulator/lp8788-ldo.c @@ -520,7 +520,7 @@ static int lp8788_dldo_probe(struct platform_device *pdev) struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent); int id = pdev->id; struct lp8788_ldo *ldo; - struct regulator_config cfg = { }; + struct regulator_config cfg = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; int ret; @@ -581,7 +581,7 @@ static int lp8788_aldo_probe(struct platform_device *pdev) struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent); int id = pdev->id; struct lp8788_ldo *ldo; - struct regulator_config cfg = { }; + struct regulator_config cfg = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; int ret; diff --git a/drivers/regulator/max1586.c b/drivers/regulator/max1586.c index 54af61015814..1c6f2111fb07 100644 --- a/drivers/regulator/max1586.c +++ b/drivers/regulator/max1586.c @@ -164,7 +164,7 @@ static int max1586_pmic_probe(struct i2c_client *client, { struct regulator_dev **rdev; struct max1586_platform_data *pdata = client->dev.platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct max1586_data *max1586; int i, id, ret = -ENOMEM; diff --git a/drivers/regulator/max17135-regulator.c b/drivers/regulator/max17135-regulator.c index 3b3d71b4d6bf..0967dfe47962 100644 --- a/drivers/regulator/max17135-regulator.c +++ b/drivers/regulator/max17135-regulator.c @@ -703,7 +703,7 @@ static int max17135_regulator_probe(struct platform_device *pdev) struct max17135_platform_data *pdata = max17135->pdata; struct max17135_data *priv; struct regulator_dev **rdev; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int size, i, ret = 0; if (max17135->dev->of_node) { diff --git a/drivers/regulator/max77686.c b/drivers/regulator/max77686.c index 20935b1a6ed4..0f0e8666ea86 100644 --- a/drivers/regulator/max77686.c +++ b/drivers/regulator/max77686.c @@ -443,7 +443,7 @@ static int max77686_pmic_probe(struct platform_device *pdev) struct max77686_platform_data *pdata = dev_get_platdata(iodev->dev); struct max77686_data *max77686; int i, ret = 0; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; dev_dbg(&pdev->dev, "%s\n", __func__); diff --git a/drivers/regulator/max8649.c b/drivers/regulator/max8649.c index db6c9be10f3f..200787692603 100644 --- a/drivers/regulator/max8649.c +++ b/drivers/regulator/max8649.c @@ -154,7 +154,7 @@ static int max8649_regulator_probe(struct i2c_client *client, { struct max8649_platform_data *pdata = client->dev.platform_data; struct max8649_regulator_info *info = NULL; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; unsigned int val; unsigned char data; int ret; diff --git a/drivers/regulator/max8660.c b/drivers/regulator/max8660.c index d428ef9a626f..23de54b68c0c 100644 --- a/drivers/regulator/max8660.c +++ b/drivers/regulator/max8660.c @@ -310,7 +310,7 @@ static int max8660_probe(struct i2c_client *client, { struct regulator_dev **rdev; struct max8660_platform_data *pdata = client->dev.platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct max8660 *max8660; int boot_on, i, id, ret = -EINVAL; diff --git a/drivers/regulator/max8907-regulator.c b/drivers/regulator/max8907-regulator.c index 4568c15fa78d..cdd2f8e3fe29 100644 --- a/drivers/regulator/max8907-regulator.c +++ b/drivers/regulator/max8907-regulator.c @@ -283,7 +283,7 @@ static int max8907_regulator_probe(struct platform_device *pdev) struct max8907_regulator *pmic; unsigned int val; int i; - struct regulator_config config = {}; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_init_data *idata; const char *mbatt_rail_name = NULL; diff --git a/drivers/regulator/max8925-regulator.c b/drivers/regulator/max8925-regulator.c index 3597da8f0dca..88e7151d864a 100644 --- a/drivers/regulator/max8925-regulator.c +++ b/drivers/regulator/max8925-regulator.c @@ -278,7 +278,7 @@ static int max8925_regulator_probe(struct platform_device *pdev) { struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent); struct regulator_init_data *pdata = pdev->dev.platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct max8925_regulator_info *ri; struct resource *res; struct regulator_dev *rdev; diff --git a/drivers/regulator/max8952.c b/drivers/regulator/max8952.c index 5259c2fea90a..c32d9899bce1 100644 --- a/drivers/regulator/max8952.c +++ b/drivers/regulator/max8952.c @@ -197,7 +197,7 @@ static int max8952_pmic_probe(struct i2c_client *client, { struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); struct max8952_platform_data *pdata = client->dev.platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct max8952_data *max8952; int ret = 0, err = 0; diff --git a/drivers/regulator/max8973-regulator.c b/drivers/regulator/max8973-regulator.c index adb1414e5e37..1b751ba5e568 100644 --- a/drivers/regulator/max8973-regulator.c +++ b/drivers/regulator/max8973-regulator.c @@ -363,7 +363,7 @@ static int max8973_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct max8973_regulator_platform_data *pdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; struct max8973_chip *max; int ret; diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c index df20069f0537..4c1610148f27 100644 --- a/drivers/regulator/max8997.c +++ b/drivers/regulator/max8997.c @@ -1028,7 +1028,7 @@ static int max8997_pmic_probe(struct platform_device *pdev) { struct max8997_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct max8997_platform_data *pdata = iodev->pdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev **rdev; struct max8997_data *max8997; struct i2c_client *i2c; diff --git a/drivers/regulator/max8998.c b/drivers/regulator/max8998.c index a57a1b15cdba..146e3b90d4af 100644 --- a/drivers/regulator/max8998.c +++ b/drivers/regulator/max8998.c @@ -625,7 +625,7 @@ static int max8998_pmic_probe(struct platform_device *pdev) { struct max8998_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct max8998_platform_data *pdata = dev_get_platdata(iodev->dev); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev **rdev; struct max8998_data *max8998; struct i2c_client *i2c; diff --git a/drivers/regulator/mc13783-regulator.c b/drivers/regulator/mc13783-regulator.c index fdf7f0a09090..ee47a74da5b4 100644 --- a/drivers/regulator/mc13783-regulator.c +++ b/drivers/regulator/mc13783-regulator.c @@ -399,7 +399,7 @@ static int mc13783_regulator_probe(struct platform_device *pdev) struct mc13xxx_regulator_platform_data *pdata = dev_get_platdata(&pdev->dev); struct mc13xxx_regulator_init_data *mc13xxx_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int i, ret, num_regulators; num_regulators = mc13xxx_get_num_regulators_dt(pdev); diff --git a/drivers/regulator/mc13892-regulator.c b/drivers/regulator/mc13892-regulator.c index b716283a8760..4da51ebbd094 100644 --- a/drivers/regulator/mc13892-regulator.c +++ b/drivers/regulator/mc13892-regulator.c @@ -534,7 +534,7 @@ static int mc13892_regulator_probe(struct platform_device *pdev) struct mc13xxx_regulator_platform_data *pdata = dev_get_platdata(&pdev->dev); struct mc13xxx_regulator_init_data *mc13xxx_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int i, ret; int num_regulators = 0; u32 val; diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c index 3ae44ac12a94..ab749956bb66 100644 --- a/drivers/regulator/palmas-regulator.c +++ b/drivers/regulator/palmas-regulator.c @@ -768,7 +768,7 @@ static int palmas_regulators_probe(struct platform_device *pdev) struct palmas_pmic_platform_data *pdata = pdev->dev.platform_data; struct device_node *node = pdev->dev.of_node; struct regulator_dev *rdev; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct palmas_pmic *pmic; struct palmas_reg_init *reg_init; int id = 0, ret; diff --git a/drivers/regulator/pcap-regulator.c b/drivers/regulator/pcap-regulator.c index 4899342f1fc1..f053b8da9a86 100644 --- a/drivers/regulator/pcap-regulator.c +++ b/drivers/regulator/pcap-regulator.c @@ -240,7 +240,7 @@ static int pcap_regulator_probe(struct platform_device *pdev) { struct regulator_dev *rdev; void *pcap = dev_get_drvdata(pdev->dev.parent); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; config.dev = &pdev->dev; config.init_data = pdev->dev.platform_data; diff --git a/drivers/regulator/pcf50633-regulator.c b/drivers/regulator/pcf50633-regulator.c index 534075e13d6d..166a775a6979 100644 --- a/drivers/regulator/pcf50633-regulator.c +++ b/drivers/regulator/pcf50633-regulator.c @@ -80,7 +80,7 @@ static int pcf50633_regulator_probe(struct platform_device *pdev) { struct regulator_dev *rdev; struct pcf50633 *pcf; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; /* Already set by core driver */ pcf = dev_to_pcf50633(pdev->dev.parent); diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c index b9c1b9a906d6..4ec8d77b9eb1 100644 --- a/drivers/regulator/pfuze100-regulator.c +++ b/drivers/regulator/pfuze100-regulator.c @@ -400,7 +400,7 @@ static int pfuze100_regulator_probe(struct i2c_client *client, struct pfuze_chip *pfuze_chip; struct pfuze_regulator_platform_data *pdata = dev_get_platdata(&client->dev); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int i, ret; const struct of_device_id *match; u32 regulator_num; diff --git a/drivers/regulator/rc5t583-regulator.c b/drivers/regulator/rc5t583-regulator.c index 5885b4504596..6de341dada8f 100644 --- a/drivers/regulator/rc5t583-regulator.c +++ b/drivers/regulator/rc5t583-regulator.c @@ -120,7 +120,7 @@ static int rc5t583_regulator_probe(struct platform_device *pdev) struct rc5t583 *rc5t583 = dev_get_drvdata(pdev->dev.parent); struct rc5t583_platform_data *pdata = dev_get_platdata(rc5t583->dev); struct regulator_init_data *reg_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct rc5t583_regulator *reg = NULL; struct rc5t583_regulator *regs; struct regulator_dev *rdev; diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index cd9ea2ea1826..3f0a595e0a84 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -235,7 +235,7 @@ static int s2mps11_pmic_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct sec_platform_data *pdata = dev_get_platdata(iodev->dev); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct s2mps11_info *s2mps11; int i, ret; unsigned char ramp_enable, ramp_reg = 0; diff --git a/drivers/regulator/s5m8767.c b/drivers/regulator/s5m8767.c index c24448bc43cf..d75556e49e74 100644 --- a/drivers/regulator/s5m8767.c +++ b/drivers/regulator/s5m8767.c @@ -654,7 +654,7 @@ static int s5m8767_pmic_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct sec_platform_data *pdata = iodev->pdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev **rdev; struct s5m8767_info *s5m8767; int i, ret, size, buck_init; diff --git a/drivers/regulator/tps51632-regulator.c b/drivers/regulator/tps51632-regulator.c index 6e67be75ea1b..c09adf35c99d 100644 --- a/drivers/regulator/tps51632-regulator.c +++ b/drivers/regulator/tps51632-regulator.c @@ -263,7 +263,7 @@ static int tps51632_probe(struct i2c_client *client, struct regulator_dev *rdev; struct tps51632_chip *tps; int ret; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; if (client->dev.of_node) { const struct of_device_id *match; diff --git a/drivers/regulator/tps6105x-regulator.c b/drivers/regulator/tps6105x-regulator.c index ec9453ffb77f..6f111a996f9d 100644 --- a/drivers/regulator/tps6105x-regulator.c +++ b/drivers/regulator/tps6105x-regulator.c @@ -131,7 +131,7 @@ static int tps6105x_regulator_probe(struct platform_device *pdev) { struct tps6105x *tps6105x = dev_get_platdata(&pdev->dev); struct tps6105x_platform_data *pdata = tps6105x->pdata; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int ret; /* This instance is not set for regulator mode so bail out */ diff --git a/drivers/regulator/tps62360-regulator.c b/drivers/regulator/tps62360-regulator.c index 612919c3081c..6a8aa59dbbc1 100644 --- a/drivers/regulator/tps62360-regulator.c +++ b/drivers/regulator/tps62360-regulator.c @@ -342,7 +342,7 @@ MODULE_DEVICE_TABLE(of, tps62360_of_match); static int tps62360_probe(struct i2c_client *client, const struct i2c_device_id *id) { - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct tps62360_regulator_platform_data *pdata; struct regulator_dev *rdev; struct tps62360_chip *tps; diff --git a/drivers/regulator/tps65023-regulator.c b/drivers/regulator/tps65023-regulator.c index 9d053e23e9eb..f34698f0815a 100644 --- a/drivers/regulator/tps65023-regulator.c +++ b/drivers/regulator/tps65023-regulator.c @@ -204,7 +204,7 @@ static int tps_65023_probe(struct i2c_client *client, { const struct tps_driver_data *drv_data = (void *)id->driver_data; const struct tps_info *info = drv_data->info; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_init_data *init_data; struct regulator_dev *rdev; struct tps_pmic *tps; diff --git a/drivers/regulator/tps6507x-regulator.c b/drivers/regulator/tps6507x-regulator.c index 4117ff52dba1..afe97f2c307b 100644 --- a/drivers/regulator/tps6507x-regulator.c +++ b/drivers/regulator/tps6507x-regulator.c @@ -437,7 +437,7 @@ static int tps6507x_pmic_probe(struct platform_device *pdev) { struct tps6507x_dev *tps6507x_dev = dev_get_drvdata(pdev->dev.parent); struct tps_info *info = &tps6507x_pmic_regs[0]; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_init_data *init_data; struct regulator_dev *rdev; struct tps6507x_pmic *tps; diff --git a/drivers/regulator/tps65090-regulator.c b/drivers/regulator/tps65090-regulator.c index c8e70451df38..bf8ebe32922e 100644 --- a/drivers/regulator/tps65090-regulator.c +++ b/drivers/regulator/tps65090-regulator.c @@ -138,6 +138,8 @@ static void tps65090_configure_regulator_config( config->ena_gpio = tps_pdata->gpio; config->ena_gpio_flags = gpio_flag; } + else + cfg.ena_gpio = -ENODEV; } #ifdef CONFIG_OF @@ -230,7 +232,7 @@ static int tps65090_regulator_probe(struct platform_device *pdev) { struct tps65090 *tps65090_mfd = dev_get_drvdata(pdev->dev.parent); struct tps65090_regulator *ri = NULL; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; struct tps65090_regulator_plat_data *tps_pdata; struct tps65090_regulator *pmic; diff --git a/drivers/regulator/tps65217-regulator.c b/drivers/regulator/tps65217-regulator.c index df395187c063..bdd9375163a8 100644 --- a/drivers/regulator/tps65217-regulator.c +++ b/drivers/regulator/tps65217-regulator.c @@ -338,7 +338,7 @@ static int tps65217_regulator_probe(struct platform_device *pdev) struct tps65217_board *pdata = dev_get_platdata(tps->dev); struct regulator_init_data *reg_data; struct regulator_dev *rdev; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int i, ret; if (tps->dev->of_node) diff --git a/drivers/regulator/tps6524x-regulator.c b/drivers/regulator/tps6524x-regulator.c index 1094393155ed..a06dbc02d70e 100644 --- a/drivers/regulator/tps6524x-regulator.c +++ b/drivers/regulator/tps6524x-regulator.c @@ -598,7 +598,7 @@ static int pmic_probe(struct spi_device *spi) struct device *dev = &spi->dev; const struct supply_info *info = supply_info; struct regulator_init_data *init_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int ret = 0, i; init_data = dev->platform_data; diff --git a/drivers/regulator/tps6586x-regulator.c b/drivers/regulator/tps6586x-regulator.c index 2c9155b66f09..313fe7eb73a8 100644 --- a/drivers/regulator/tps6586x-regulator.c +++ b/drivers/regulator/tps6586x-regulator.c @@ -346,7 +346,7 @@ static struct tps6586x_platform_data *tps6586x_parse_regulator_dt( static int tps6586x_regulator_probe(struct platform_device *pdev) { struct tps6586x_regulator *ri = NULL; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev **rdev; struct regulator_init_data *reg_data; struct tps6586x_platform_data *pdata; diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c index 45c16447744b..66a1eb1bce71 100644 --- a/drivers/regulator/tps65910-regulator.c +++ b/drivers/regulator/tps65910-regulator.c @@ -1042,7 +1042,7 @@ static inline struct tps65910_board *tps65910_parse_dt_reg_data( static int tps65910_probe(struct platform_device *pdev) { struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct tps_info *info; struct regulator_init_data *reg_data; struct regulator_dev *rdev; diff --git a/drivers/regulator/tps65912-regulator.c b/drivers/regulator/tps65912-regulator.c index 17e994e47dc1..3c716f5aa2cf 100644 --- a/drivers/regulator/tps65912-regulator.c +++ b/drivers/regulator/tps65912-regulator.c @@ -462,7 +462,7 @@ static struct regulator_ops tps65912_ops_ldo = { static int tps65912_probe(struct platform_device *pdev) { struct tps65912 *tps65912 = dev_get_drvdata(pdev->dev.parent); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct tps_info *info; struct regulator_init_data *reg_data; struct regulator_dev *rdev; diff --git a/drivers/regulator/tps80031-regulator.c b/drivers/regulator/tps80031-regulator.c index 6511d0bfd896..494e0152bb4d 100644 --- a/drivers/regulator/tps80031-regulator.c +++ b/drivers/regulator/tps80031-regulator.c @@ -679,7 +679,7 @@ static int tps80031_regulator_probe(struct platform_device *pdev) struct tps80031_regulator *ri; struct tps80031_regulator *pmic; struct regulator_dev *rdev; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct tps80031 *tps80031_mfd = dev_get_drvdata(pdev->dev.parent); int ret; int num; diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c index fb6e67d74ffb..0a1773da507a 100644 --- a/drivers/regulator/twl-regulator.c +++ b/drivers/regulator/twl-regulator.c @@ -1097,7 +1097,7 @@ static int twlreg_probe(struct platform_device *pdev) struct regulator_dev *rdev; struct twl_regulator_driver_data *drvdata; const struct of_device_id *match; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; match = of_match_device(twl_of_match, &pdev->dev); if (match) { diff --git a/drivers/regulator/vexpress.c b/drivers/regulator/vexpress.c index 4668c7f8133d..7335a0b09a1a 100644 --- a/drivers/regulator/vexpress.c +++ b/drivers/regulator/vexpress.c @@ -60,7 +60,7 @@ static int vexpress_regulator_probe(struct platform_device *pdev) int err; struct vexpress_regulator *reg; struct regulator_init_data *init_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; reg = devm_kzalloc(&pdev->dev, sizeof(*reg), GFP_KERNEL); if (!reg) { diff --git a/drivers/regulator/wm831x-dcdc.c b/drivers/regulator/wm831x-dcdc.c index 0af6898bcd79..26111df52445 100644 --- a/drivers/regulator/wm831x-dcdc.c +++ b/drivers/regulator/wm831x-dcdc.c @@ -452,7 +452,7 @@ static int wm831x_buckv_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id; struct wm831x_dcdc *dcdc; struct resource *res; @@ -627,7 +627,7 @@ static int wm831x_buckp_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id; struct wm831x_dcdc *dcdc; struct resource *res; @@ -775,7 +775,7 @@ static int wm831x_boostp_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id = pdev->id % ARRAY_SIZE(pdata->dcdc); struct wm831x_dcdc *dcdc; struct resource *res; @@ -887,7 +887,7 @@ static int wm831x_epe_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id = pdev->id % ARRAY_SIZE(pdata->epe); struct wm831x_dcdc *dcdc; int ret; diff --git a/drivers/regulator/wm831x-isink.c b/drivers/regulator/wm831x-isink.c index 68586ee3e1cb..c683fdc0171a 100644 --- a/drivers/regulator/wm831x-isink.c +++ b/drivers/regulator/wm831x-isink.c @@ -154,7 +154,7 @@ static int wm831x_isink_probe(struct platform_device *pdev) struct wm831x_pdata *pdata = wm831x->dev->platform_data; struct wm831x_isink *isink; int id = pdev->id % ARRAY_SIZE(pdata->isink); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct resource *res; int ret, irq; diff --git a/drivers/regulator/wm831x-ldo.c b/drivers/regulator/wm831x-ldo.c index 1ec379a9a95c..5db276aa98e1 100644 --- a/drivers/regulator/wm831x-ldo.c +++ b/drivers/regulator/wm831x-ldo.c @@ -251,7 +251,7 @@ static int wm831x_gp_ldo_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id; struct wm831x_ldo *ldo; struct resource *res; @@ -508,7 +508,7 @@ static int wm831x_aldo_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id; struct wm831x_ldo *ldo; struct resource *res; @@ -664,7 +664,7 @@ static int wm831x_alive_ldo_probe(struct platform_device *pdev) { struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); struct wm831x_pdata *pdata = wm831x->dev->platform_data; - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; int id; struct wm831x_ldo *ldo; struct resource *res; diff --git a/drivers/regulator/wm8350-regulator.c b/drivers/regulator/wm8350-regulator.c index 7f0fa22ef2aa..d3b286a806e1 100644 --- a/drivers/regulator/wm8350-regulator.c +++ b/drivers/regulator/wm8350-regulator.c @@ -1193,7 +1193,7 @@ static irqreturn_t pmic_uv_handler(int irq, void *data) static int wm8350_regulator_probe(struct platform_device *pdev) { struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; int ret; u16 val; diff --git a/drivers/regulator/wm8400-regulator.c b/drivers/regulator/wm8400-regulator.c index c6a32ea80b9d..670b2989dc84 100644 --- a/drivers/regulator/wm8400-regulator.c +++ b/drivers/regulator/wm8400-regulator.c @@ -229,7 +229,7 @@ static struct regulator_desc regulators[] = { static int wm8400_regulator_probe(struct platform_device *pdev) { struct wm8400 *wm8400 = container_of(pdev, struct wm8400, regulators[pdev->id]); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct regulator_dev *rdev; config.dev = &pdev->dev; diff --git a/drivers/regulator/wm8994-regulator.c b/drivers/regulator/wm8994-regulator.c index a612c356a697..ecd980dcd365 100644 --- a/drivers/regulator/wm8994-regulator.c +++ b/drivers/regulator/wm8994-regulator.c @@ -127,7 +127,7 @@ static int wm8994_ldo_probe(struct platform_device *pdev) struct wm8994 *wm8994 = dev_get_drvdata(pdev->dev.parent); struct wm8994_pdata *pdata = wm8994->dev->platform_data; int id = pdev->id % ARRAY_SIZE(pdata->ldo); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; struct wm8994_ldo *ldo; int ret; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index b9838130a7b0..04f0515ffe41 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -480,7 +480,7 @@ config RTC_DRV_EM3027 will be called rtc-em3027. config RTC_DRV_RV3029C2 - tristate "Micro Crystal RTC" + tristate "Micro Crystal RV-3029-C2 RTC" help If you say yes here you get support for the Micro Crystal RV3029-C2 RTC chips. @@ -488,6 +488,15 @@ config RTC_DRV_RV3029C2 This driver can also be built as a module. If so, the module will be called rtc-rv3029c2. +config RTC_DRV_RV4162 + tristate "Micro Crystal RTC RV-4162" + help + If you say yes here you get support for the Micro Crystal + RV4162-C7 RTC chips. + + This driver can also be built as a module. If so, the module + will be called rtc-rv4162. + endif # I2C comment "SPI RTC drivers" diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index c33f86f1a69b..d948024f6773 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o +obj-$(CONFIG_RTC_DRV_RV4162) += rtc-rv4162.o obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c index 42bd57da239d..dbb73af913e9 100644 --- a/drivers/rtc/interface.c +++ b/drivers/rtc/interface.c @@ -323,7 +323,7 @@ int rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) } EXPORT_SYMBOL_GPL(rtc_read_alarm); -static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) +static int check_alarm_past(struct rtc_device *rtc, struct rtc_wkalrm *alarm) { struct rtc_time tm; long now, scheduled; @@ -337,8 +337,16 @@ static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) /* Make sure we're not setting alarms in the past */ err = __rtc_read_time(rtc, &tm); rtc_tm_to_time(&tm, &now); - if (scheduled <= now) + if (scheduled <= now) { + pr_info("%s: alarm in the past\n", __func__); return -ETIME; + } + return 0; +} + +static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) +{ + int err = check_alarm_past(rtc, alarm); /* * XXX - We just checked to make sure the alarm time is not * in the past, but there is still a race window where if @@ -346,12 +354,15 @@ static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) * over right here, before we set the alarm. */ + if (err) + return err; if (!rtc->ops) err = -ENODEV; else if (!rtc->ops->set_alarm) err = -EINVAL; - else + else { err = rtc->ops->set_alarm(rtc->dev.parent, alarm); + } return err; } @@ -383,11 +394,10 @@ EXPORT_SYMBOL_GPL(rtc_set_alarm); /* Called once per device from rtc_device_register */ int rtc_initialize_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) { - int err; struct rtc_time now; + int err = check_alarm_past(rtc, alarm); - err = rtc_valid_tm(&alarm->time); - if (err != 0) + if (err) return err; err = rtc_read_time(rtc, &now); diff --git a/drivers/rtc/rtc-isl1208.c b/drivers/rtc/rtc-isl1208.c index c016ad81767a..5a0c829ac18b 100644 --- a/drivers/rtc/rtc-isl1208.c +++ b/drivers/rtc/rtc-isl1208.c @@ -243,14 +243,16 @@ static int isl1208_rtc_proc(struct device *dev, struct seq_file *seq) { struct i2c_client *const client = to_i2c_client(dev); - int sr, dtr, atr, usr; + int sr, dtr, atr, usr, icr; sr = isl1208_i2c_get_sr(client); if (sr < 0) { dev_err(&client->dev, "%s: reading SR failed\n", __func__); return sr; } + icr = i2c_smbus_read_byte_data(client, ISL1208_REG_INT); + seq_printf(seq, "int reg\t: %x\n", icr); seq_printf(seq, "status_reg\t:%s%s%s%s%s%s (0x%.2x)\n", (sr & ISL1208_REG_SR_RTCF) ? " RTCF" : "", (sr & ISL1208_REG_SR_BAT) ? " BAT" : "", @@ -389,10 +391,12 @@ isl1208_i2c_set_alarm(struct i2c_client *client, struct rtc_wkalrm *alarm) return err; /* If the alarm time is before the current time disable the alarm */ - if (!alarm->enabled || alarm_secs <= rtc_secs) + if (!alarm->enabled || alarm_secs <= rtc_secs) { enable = 0x00; - else + dev_info(&client->dev, "%s: alarm in the past\n", __func__); + } else { enable = 0x80; + } /* Program the alarm and enable it for each setting */ regs[ISL1208_REG_SCA - offs] = bin2bcd(alarm_tm->tm_sec) | enable; @@ -429,7 +433,7 @@ isl1208_rtc_read_time(struct device *dev, struct rtc_time *tm) static int isl1208_i2c_set_time(struct i2c_client *client, struct rtc_time const *tm) { - int sr; + int sr, ret; u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, }; /* The clock has an 8 bit wide bcd-coded register (they never learn) @@ -455,6 +459,12 @@ isl1208_i2c_set_time(struct i2c_client *client, struct rtc_time const *tm) return sr; } + /* + * manual says writes of 1 have no effect, it lies + * So, we cannot do + * sr |= ISL1208_REG_SR_ALM; + * + */ /* set WRTC */ sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR, sr | ISL1208_REG_SR_WRTC); @@ -464,11 +474,11 @@ isl1208_i2c_set_time(struct i2c_client *client, struct rtc_time const *tm) } /* write RTC registers */ - sr = isl1208_i2c_set_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN); - if (sr < 0) { + ret = isl1208_i2c_set_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN); + if (ret < 0) { dev_err(&client->dev, "%s: writing RTC section failed\n", __func__); - return sr; + return ret; } /* clear WRTC again */ @@ -649,7 +659,7 @@ isl1208_probe(struct i2c_client *client, const struct i2c_device_id *id) if (client->irq > 0) { rc = request_threaded_irq(client->irq, NULL, isl1208_rtc_interrupt, - IRQF_SHARED, + IRQF_SHARED | IRQF_ONESHOT, isl1208_driver.driver.name, client); if (!rc) { device_init_wakeup(&client->dev, 1); @@ -717,9 +727,15 @@ static const struct i2c_device_id isl1208_id[] = { }; MODULE_DEVICE_TABLE(i2c, isl1208_id); +static struct of_device_id isl1208_dt_ids[] = { + { .compatible = "isl,isl1208" }, + { /* sentinel */ } +}; + static struct i2c_driver isl1208_driver = { .driver = { .name = "rtc-isl1208", + .of_match_table = of_match_ptr(isl1208_dt_ids), }, .probe = isl1208_probe, .remove = isl1208_remove, diff --git a/drivers/rtc/rtc-rv4162.c b/drivers/rtc/rtc-rv4162.c new file mode 100644 index 000000000000..846f7b305f87 --- /dev/null +++ b/drivers/rtc/rtc-rv4162.c @@ -0,0 +1,185 @@ +/* + * An rtc/i2c driver for the Micro Crystal RV-4162 Real-time clock + * + * Copyright 2013 Boundary Devices + * + * Author: Eric Nelson <eric.nelson@boundarydevices.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/i2c.h> +#include <linux/rtc.h> + +/* Registers */ +#define RV4162_REG_SECS 0x01 +#define RV4162_SECFLAG_ST 0x80 + +#define RV4162_REG_FLAGS 0x0f +#define RV4162_FLAG_OF 4 + +static struct i2c_driver rv4162_driver; + +#define BCD_TO_BIN(v) (((v)&0x0f)+(((v)&0xF0)>>4)*10) + +static int rv4162_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + u8 addr = 0; + u8 buf[8]; + int err; + struct i2c_msg msgs[] = { + {client->addr, 0, 1, &addr}, + {client->addr, I2C_M_RD, sizeof(buf), buf}, + }; + memset(tm,0,sizeof(*tm)); + if (2 == (err=i2c_transfer(client->adapter, &msgs[0], 2))) { + tm->tm_sec = BCD_TO_BIN(buf[1]&0x7f); + tm->tm_min = BCD_TO_BIN(buf[2]&0x7f); + tm->tm_hour = BCD_TO_BIN(buf[3]); + tm->tm_mon = BCD_TO_BIN(buf[6]&0x1F)-1; + tm->tm_mday = BCD_TO_BIN(buf[5]); + tm->tm_wday = (buf[4]&7)-1; + tm->tm_yday = -1; + tm->tm_year = BCD_TO_BIN(buf[7])+(100*(buf[6]>>6)); + dev_dbg(&client->dev, "%s: read time: %04u-%02u-%02u %02u:%02u:%02u\n", + __func__, + tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + dev_dbg(&client->dev, "%s: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", + __func__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + return 0; + } + else { + dev_err(&client->dev, "%s: error %d reading time\n", + __func__, err); + return err; + } +} + +#define BIN_TO_BCD(v) ((((v)/10)<<4)|((v)%10)) + +static int rv4162_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + u8 buf[9]; + int err; + struct i2c_msg msg = { + client->addr, 0, sizeof(buf), buf + }; + buf[0] = 0; + buf[1] = 0; + buf[2] = BIN_TO_BCD(tm->tm_sec); + buf[3] = BIN_TO_BCD(tm->tm_min); + buf[4] = BIN_TO_BCD(tm->tm_hour); + buf[5] = tm->tm_wday+1; + buf[6] = BIN_TO_BCD(tm->tm_mday); + buf[7] = BIN_TO_BCD(tm->tm_mon+1) | ((tm->tm_year/100)<<6); + buf[8] = BIN_TO_BCD(tm->tm_year%100); + if (1 == (err=i2c_transfer(client->adapter, &msg, 1))) { + dev_dbg(&client->dev, "%s: %04u-%02u-%02u %02u:%02u:%02u\n", + __func__, + tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + dev_dbg(&client->dev, "%s: %02x:%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", + __func__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7], buf[8]); + return 0; + } + else { + dev_err(&client->dev, "%s: error %d saving time\n", + __func__, err); + return err; + } +} + +static const struct rtc_class_ops rv4162_rtc_ops = { + .read_time = rv4162_rtc_read_time, + .set_time = rv4162_rtc_set_time, +}; + +static int rv4162_remove(struct i2c_client *client) +{ + struct rtc_device *rtc = i2c_get_clientdata(client); + + if (rtc) + rtc_device_unregister(rtc); + + return 0; +} + +static int rv4162_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct rtc_device *rtc; + unsigned char addr = RV4162_REG_FLAGS; + unsigned char flags; + struct i2c_msg msgs[] = { + {client->addr, 0, 1, &addr}, + {client->addr, I2C_M_RD, 1, &flags}, + }; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return -ENODEV; + + if ((i2c_transfer(client->adapter, &msgs[0], 2)) != 2) { + dev_err(&client->dev, "%s: read error\n", __func__); + return -EIO; + } + + dev_info(&client->dev, "%s: chip found: flags 0x%02x\n", __func__, flags); + + rtc = rtc_device_register(rv4162_driver.driver.name, &client->dev, + &rv4162_rtc_ops, THIS_MODULE); + + if (IS_ERR(rtc)) + return PTR_ERR(rtc); + + i2c_set_clientdata(client, rtc); + + return 0; +} + +static struct i2c_device_id rv4162_id[] = { + { "rv4162", 0 }, + { } +}; + +static struct of_device_id rv4162_dt_ids[] = { + { .compatible = "mcrystal,rv4162" }, + { /* sentinel */ } +}; + +static struct i2c_driver rv4162_driver = { + .driver = { + .name = "rtc-rv4162", + .of_match_table = of_match_ptr(rv4162_dt_ids), + }, + .probe = &rv4162_probe, + .remove = &rv4162_remove, + .id_table = rv4162_id, +}; + +static int __init rv4162_init(void) +{ + return i2c_add_driver(&rv4162_driver); +} + +static void __exit rv4162_exit(void) +{ + i2c_del_driver(&rv4162_driver); +} + +MODULE_AUTHOR("Eric Nelson <eric.nelson@boundarydevices.com>"); +MODULE_DESCRIPTION("Micro Crystal RV-4162 Real-time clock driver"); +MODULE_LICENSE("GPL"); + +module_init(rv4162_init); +module_exit(rv4162_exit); diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig index cabc7a367db5..3ff4a64c63d0 100644 --- a/drivers/staging/iio/adc/Kconfig +++ b/drivers/staging/iio/adc/Kconfig @@ -130,4 +130,10 @@ config SPEAR_ADC Say yes here to build support for the integrated ADC inside the ST SPEAr SoC. Provides direct access via sysfs. +config STMPE_ADC + bool "ST Microelectronics STMPE ADC driver" + depends on MFD_STMPE + help + Say yes here to build support for ST Microelectronics STMPE + built in ADC block (stmpe811). endmenu diff --git a/drivers/staging/iio/adc/Makefile b/drivers/staging/iio/adc/Makefile index 3e9fb143d25b..3f37ee59cc44 100644 --- a/drivers/staging/iio/adc/Makefile +++ b/drivers/staging/iio/adc/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_AD7280) += ad7280a.o obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o obj-$(CONFIG_SPEAR_ADC) += spear_adc.o +obj-$(CONFIG_STMPE_ADC) += stmpe-adc.o diff --git a/drivers/staging/iio/adc/stmpe-adc.c b/drivers/staging/iio/adc/stmpe-adc.c new file mode 100644 index 000000000000..64d081a0d98a --- /dev/null +++ b/drivers/staging/iio/adc/stmpe-adc.c @@ -0,0 +1,415 @@ +/* + * stmpe.c - STMicroelectronics STMPE811 IIO ADC Driver + * + * 4 channel, 10/12-bit ADC + * + * Copyright (C) 2013 Toradex AG <stefan.agner@toradex.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/iio/events.h> +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mfd/stmpe.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/slab.h> + +#define STMPE_REG_INT_STA 0x0B +#define STMPE_REG_ADC_INT_EN 0x0E +#define STMPE_REG_ADC_INT_STA 0x0F + +#define STMPE_REG_ADC_CTRL1 0x20 +#define STMPE_REG_ADC_CTRL2 0x21 +#define STMPE_REG_ADC_CAPT 0x22 +#define STMPE_REG_ADC_DATA_CH(channel) (0x30 + 2*channel) + +#define STMPE_REG_TEMP_CTRL 0x60 +#define STMPE_START_ONE_TEMP_CONV (0x08 + 0x02 + 0x01) +#define STMPE_REG_TEMP_DATA 0x61 +#define STMPE_REG_TEMP_TH 0x63 + +#define STMPE_ADC_CH(channel) ((1 << channel) & 0xff) + +#define STMPE_ADC_TIMEOUT (msecs_to_jiffies(1000)) + +struct stmpe_adc { + struct stmpe *stmpe; + struct clk *clk; + struct device *dev; + unsigned int irq; + + struct completion completion; + + u8 channel; + u32 value; + u8 sample_time; + u8 mod_12b; + u8 ref_sel; + u8 adc_freq; +}; + +static int stmpe_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, + int *val2, + long mask) +{ + struct stmpe_adc *info = iio_priv(indio_dev); + unsigned long timeout; + + if (mask > 0) + return -EINVAL; + + mutex_lock(&indio_dev->mlock); + + info->channel = (u8)chan->channel; + switch (chan->type) + { + case IIO_VOLTAGE: + BUG_ON(info->channel > 7); + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_EN, + STMPE_ADC_CH(info->channel)); + + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_CAPT, + STMPE_ADC_CH(info->channel)); + + timeout = wait_for_completion_interruptible_timeout + (&info->completion, STMPE_ADC_TIMEOUT); + + *val = info->value; + break; + case IIO_TEMP: + BUG_ON(info->channel != 8); + stmpe_reg_write(info->stmpe, STMPE_REG_TEMP_CTRL, + STMPE_START_ONE_TEMP_CONV); + + timeout = wait_for_completion_interruptible_timeout + (&info->completion, STMPE_ADC_TIMEOUT); + /* absolute temp = +V3.3 * value /7.51 [K] */ + /* scale to [milli °C] */ + *val = ((449960l * info->value) / 1024l) - 273150; + break; + default: + BUG(); + break; + } + + mutex_unlock(&indio_dev->mlock); + + if (timeout == -ERESTARTSYS) + return -EINTR; + + if (timeout == 0) + return -ETIMEDOUT; + + return IIO_VAL_INT; +} + +static irqreturn_t stmpe_adc_isr(int irq, void *dev_id) +{ + struct stmpe_adc *info = (struct stmpe_adc *)dev_id; + u8 data[2]; + int int_sta; + + if(info->channel < 8) { + int_sta = stmpe_reg_read(info->stmpe, STMPE_REG_ADC_INT_STA); + + /* Is the interrupt relevant */ + if (!(int_sta & STMPE_ADC_CH(info->channel))) + return IRQ_NONE; + + /* Read value */ + stmpe_block_read(info->stmpe, + STMPE_REG_ADC_DATA_CH(info->channel), 2, data); + info->value = ((u32)data[0] << 8) + data[1]; + + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, int_sta); + + complete(&info->completion); + } else if (info->channel == 8) { + /* Read value */ + stmpe_block_read(info->stmpe, STMPE_REG_TEMP_DATA, 2, data); + info->value = ((u32)data[0] << 8) + data[1]; + + complete(&info->completion); + } else + return IRQ_NONE; + + return IRQ_HANDLED; +} + +static const struct iio_info stmpe_adc_iio_info = { + .read_raw = &stmpe_read_raw, + .driver_module = THIS_MODULE, +}; + +#define STMPE_EV_M \ + (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \ + | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING)) + +#define STMPE_VOLTAGE_CHAN(_chan) \ +{ \ + .type = IIO_VOLTAGE, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .indexed = 1, \ + .channel = _chan, \ + .event_mask = STMPE_EV_M, \ +} + +static const struct iio_chan_spec stmpe_adc_all_iio_channels[] = { + STMPE_VOLTAGE_CHAN(0), + STMPE_VOLTAGE_CHAN(1), + STMPE_VOLTAGE_CHAN(2), + STMPE_VOLTAGE_CHAN(3), + STMPE_VOLTAGE_CHAN(4), + STMPE_VOLTAGE_CHAN(5), + STMPE_VOLTAGE_CHAN(6), + STMPE_VOLTAGE_CHAN(7), + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .indexed = 1, + .channel = 8, + .event_mask = + IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING)| + IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING) + } +}; + +static const struct iio_chan_spec stmpe_adc_iio_channels[] = { + STMPE_VOLTAGE_CHAN(4), + STMPE_VOLTAGE_CHAN(5), + STMPE_VOLTAGE_CHAN(6), + STMPE_VOLTAGE_CHAN(7), + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .indexed = 1, + .channel = 8, + .event_mask = + IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING)| + IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING) + } +}; + + +static int stmpe_adc_remove_devices(struct device *dev, void *c) +{ + struct platform_device *pdev = to_platform_device(dev); + + platform_device_unregister(pdev); + + return 0; +} + +static int stmpe_adc_init_hw(struct stmpe_adc *adc) +{ + int ret; + u8 adc_ctrl1, adc_ctrl1_mask; + struct stmpe *stmpe = adc->stmpe; + struct device *dev = adc->dev; + + ret = stmpe_enable(stmpe, STMPE_BLOCK_ADC); + if (ret) { + dev_err(dev, "Could not enable clock for ADC\n"); + return ret; + } + + adc_ctrl1 = SAMPLE_TIME(adc->sample_time) | MOD_12B(adc->mod_12b) | + REF_SEL(adc->ref_sel); + adc_ctrl1_mask = SAMPLE_TIME(0xff) | MOD_12B(0xff) | REF_SEL(0xff); + + ret = stmpe_set_bits(stmpe, STMPE_REG_ADC_CTRL1, + adc_ctrl1_mask, adc_ctrl1); + if (ret) { + dev_err(dev, "Could not setup ADC\n"); + return ret; + } + + ret = stmpe_set_bits(stmpe, STMPE_REG_ADC_CTRL2, + ADC_FREQ(0xff), ADC_FREQ(adc->adc_freq)); + if (ret) { + dev_err(dev, "Could not setup ADC\n"); + return ret; + } + + /* use temp irq for each conversion completion */ + stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH, 0); + stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH + 1, 0); + + return 0; +} + +static void stmpe_adc_get_platform_info(struct platform_device *pdev, + struct stmpe_adc *adc) +{ + struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); + struct device_node *np = pdev->dev.of_node; + struct stmpe_adc_platform_data *adc_pdata = NULL; + + adc->stmpe = stmpe; + + if (stmpe->pdata && stmpe->pdata->adc) + { + adc_pdata = stmpe->pdata->adc; + + adc->sample_time = adc_pdata->sample_time; + adc->mod_12b = adc_pdata->mod_12b; + adc->ref_sel = adc_pdata->ref_sel; + adc->adc_freq = adc_pdata->adc_freq; + } else if (np) { + u32 val; + + if (!of_property_read_u32(np, "st,sample-time", &val)) + adc->sample_time = val; + if (!of_property_read_u32(np, "st,mod-12b", &val)) + adc->mod_12b = val; + if (!of_property_read_u32(np, "st,ref-sel", &val)) + adc->ref_sel = val; + if (!of_property_read_u32(np, "st,adc-freq", &val)) + adc->adc_freq = val; + } +} + +static int stmpe_adc_probe(struct platform_device *pdev) +{ + struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); + struct stmpe_adc *info = NULL; + struct iio_dev *indio_dev = NULL; + int ret = -ENODEV; + int irq; + + irq = platform_get_irq_byname(pdev, "STMPE_ADC"); + if (irq < 0) + return irq; + + indio_dev = iio_device_alloc(sizeof(struct stmpe_adc)); + if (!indio_dev) { + dev_err(&pdev->dev, "failed allocating iio device\n"); + return -ENOMEM; + } + + info = iio_priv(indio_dev); + info->irq = irq; + + init_completion(&info->completion); + ret = request_threaded_irq(info->irq, NULL, stmpe_adc_isr, IRQF_ONESHOT, + "stmpe-adc", info); + if (ret < 0) { + dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", + info->irq); + goto err_free; + } + + irq = platform_get_irq_byname(pdev, "STMPE_TEMP_SENS"); + ret = -1; + if (irq >= 0) + ret = request_threaded_irq(irq, NULL, stmpe_adc_isr, IRQF_ONESHOT, + "stmpe-adc", info); + if (ret < 0) + dev_warn(&pdev->dev, "failed requesting irq for temp sensor, irq = %d\n", + info->irq); + + platform_set_drvdata(pdev, indio_dev); + + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.parent = &pdev->dev; + indio_dev->info = &stmpe_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + + /* Register TS-Channels only if they are available */ + if (stmpe->pdata->blocks & STMPE_BLOCK_TOUCHSCREEN) + indio_dev->channels = stmpe_adc_iio_channels; + else + indio_dev->channels = stmpe_adc_all_iio_channels; + indio_dev->num_channels = ARRAY_SIZE(stmpe_adc_iio_channels); + + stmpe_adc_get_platform_info(pdev, info); + + ret = stmpe_adc_init_hw(info); + if (ret) + goto err_irq; + + ret = iio_device_register(indio_dev); + if (ret) + goto err_irq; + + + dev_info(&pdev->dev, "Initialized\n"); + + return 0; + +err_irq: + free_irq(info->irq, info); +err_free: + kfree(indio_dev); + return ret; +} + +static int stmpe_adc_remove(struct platform_device *pdev) +{ + struct iio_dev *indio_dev = platform_get_drvdata(pdev); + struct stmpe_adc *info = iio_priv(indio_dev); + + device_for_each_child(&pdev->dev, NULL, + stmpe_adc_remove_devices); + iio_device_unregister(indio_dev); + free_irq(info->irq, info); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int stmpe_adc_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct stmpe_adc *info = iio_priv(indio_dev); + + stmpe_adc_init_hw(info); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume); + +static struct platform_driver stmpe_adc_driver = { + .probe = stmpe_adc_probe, + .remove = stmpe_adc_remove, + .driver = { + .name = "stmpe-adc", + .owner = THIS_MODULE, + .pm = &stmpe_adc_pm_ops, + }, +}; + +module_platform_driver(stmpe_adc_driver); + +MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); +MODULE_DESCRIPTION("STMPEXXX ADC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:stmpe-adc"); diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index d799140e53b6..bf2dbd7e7e40 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -120,6 +120,7 @@ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_DTRDEN (1<<3) /* DTR delta interrupt enable */ #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ #define UCR3_BPEN (1<<0) /* Preset registers enable */ @@ -155,8 +156,10 @@ #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ #define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_RIIN (1<<9) /* RI pin status */ #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ #define USR2_WAKE (1<<7) /* Wake */ +#define USR2_DCDIN (1<<5) /* DCD pin status */ #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ #define USR2_TXDC (1<<3) /* Transmitter complete */ #define USR2_BRCD (1<<2) /* Break condition */ @@ -226,6 +229,8 @@ struct imx_port { unsigned int tx_bytes; unsigned int dma_tx_nents; wait_queue_head_t dma_wait; + + struct serial_rs485 rs485; }; struct imx_port_ucrs { @@ -298,6 +303,32 @@ static inline int is_imx6q_uart(struct imx_port *sport) { return sport->devdata->devtype == IMX6Q_UART; } + +static inline void imx_rs485_switch_to_rx(struct imx_port *sport) { + writel(readl(sport->port.membase + UCR2) & ~UCR2_CTS, + sport->port.membase + UCR2); +} + +static inline void imx_rs485_switch_to_tx(struct imx_port *sport) { + writel(readl(sport->port.membase + UCR2) | UCR2_CTS, + sport->port.membase + UCR2); +} + +static inline void imx_rs485_config(struct imx_port *sport) { + if (sport->have_rtscts) { + if (sport->rs485.flags & SER_RS485_ENABLED) { + writel(readl(sport->port.membase + UCR2) & ~UCR2_CTSC, + sport->port.membase + UCR2); + imx_rs485_switch_to_rx(sport); + } + else + writel(readl(sport->port.membase + UCR2) | UCR2_CTSC, + sport->port.membase + UCR2); + } + else + sport->rs485.flags &= ~SER_RS485_ENABLED; +} + /* * Save and restore functions for UCR1, UCR2 and UCR3 registers */ @@ -374,6 +405,13 @@ static void imx_stop_tx(struct uart_port *port) struct imx_port *sport = (struct imx_port *)port; unsigned long temp; + if (readl(sport->port.membase + USR2) & USR2_TXDC) { + if (sport->rs485.flags & SER_RS485_ENABLED) + imx_rs485_switch_to_rx(sport); + writel(readl(sport->port.membase + UCR4) & ~UCR4_TCEN, + sport->port.membase + UCR4); + } + if (USE_IRDA(sport)) { /* half duplex - wait for end of transmission */ int n = 256; @@ -597,6 +635,12 @@ static void imx_start_tx(struct uart_port *port) writel(temp, sport->port.membase + UCR4); } + if (sport->rs485.flags & SER_RS485_ENABLED) { + writel(readl(sport->port.membase + UCR4) | UCR4_TCEN, + sport->port.membase + UCR4); + imx_rs485_switch_to_tx(sport); + } + if (sport->dma_is_enabled) { imx_dma_tx(sport); return; @@ -643,6 +687,7 @@ static irqreturn_t imx_txint(int irq, void *dev_id) imx_transmit_buffer(sport); + //TODO: Is this needed here, imx_transmit_buffer(sport) already does this if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(&sport->port); @@ -730,7 +775,7 @@ static void imx_dma_rxint(struct imx_port *sport) if ((temp & USR2_RDR) && !sport->dma_is_rxing) { sport->dma_is_rxing = 1; - /* disable the `Recerver Ready Interrrupt` */ + /* disable the `Receiver Ready Interrrupt` */ temp = readl(sport->port.membase + UCR1); temp &= ~(UCR1_RRDYEN); writel(temp, sport->port.membase + UCR1); @@ -746,6 +791,10 @@ static irqreturn_t imx_int(int irq, void *dev_id) unsigned int sts; unsigned int sts2; + if (readl(sport->port.membase + USR2) & USR2_TXDC && + readl(sport->port.membase + UCR4) & UCR4_TCEN) + imx_txint(irq, dev_id); + sts = readl(sport->port.membase + USR1); if (sts & USR1_RRDY) { @@ -771,6 +820,18 @@ static irqreturn_t imx_int(int irq, void *dev_id) sport->port.icount.overrun++; writel(sts2 | USR2_ORE, sport->port.membase + USR2); } + + if (sts & ((1>>10) | (1<<8) | (1<<7))) { + dev_err(sport->port.dev, "Unexpected int, USR1 = %x\n", sts); + writel(((1>>10) | (1<<8) | (1<<7)) , sport->port.membase + USR1); + } +/* FIXME remove when really unneeded */ +#if 0 + if (sts2 & ((1<<15) | USR2_DTRF | USR2_IDLE | (1<<11) | (1<<10) | (1<<8) | (1<<7) | (1<<6) | (1<<4))) { + dev_err(sport->port.dev, "Unexpected int, USR2 = %x\n", sts2); + writel(sts2 | ((1<<15) | USR2_DTRF | USR2_IDLE | (1<<11) | (1<<10) | (1<<8) | (1<<7) | (1<<6) | (1<<5)), sport->port.membase + USR2); + } +#endif return IRQ_HANDLED; } @@ -798,7 +859,18 @@ static unsigned int imx_tx_empty(struct uart_port *port) static unsigned int imx_get_mctrl(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; - unsigned int tmp = TIOCM_DSR | TIOCM_CAR; + unsigned int tmp = 0; + + if(sport->dte_mode) { + /* TODO: assume for now that DSR and CAR are the same signal, use GPIO + functionality to get the DSR state */ + if(!(readl(sport->port.membase + USR2) & USR2_DCDIN)) + tmp |= (TIOCM_CAR | TIOCM_DSR); + if(!(readl(sport->port.membase + USR2) & USR2_RIIN)) + tmp |= TIOCM_RI; + } + else + tmp = TIOCM_DSR | TIOCM_CAR; if (readl(sport->port.membase + USR1) & USR1_RTSS) tmp |= TIOCM_CTS; @@ -817,13 +889,16 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) struct imx_port *sport = (struct imx_port *)port; unsigned long temp; - temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; + /* RTS must not be touched in RS485 mode */ + if (!(sport->rs485.flags & SER_RS485_ENABLED)) { + temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; - if (mctrl & TIOCM_RTS) - if (!sport->dma_is_enabled) - temp |= UCR2_CTS; + if (mctrl & TIOCM_RTS) + if (!sport->dma_is_enabled) + temp |= UCR2_CTS; - writel(temp, sport->port.membase + UCR2); + writel(temp, sport->port.membase + UCR2); + } temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; if (mctrl & TIOCM_LOOP) @@ -1201,6 +1276,9 @@ static int imx_startup(struct uart_port *port) imx_enable_ms(&sport->port); spin_unlock_irqrestore(&sport->port.lock, flags); + /* Handle RX485 configuration */ + imx_rs485_config(sport); + if (USE_IRDA(sport)) { struct imxuart_platform_data *pdata; pdata = dev_get_platdata(sport->port.dev); @@ -1301,6 +1379,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, struct imx_port *sport = (struct imx_port *)port; unsigned long flags; unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; + unsigned ucr3 = 0; unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; unsigned int div, ufcr; unsigned long num, denom; @@ -1330,7 +1409,8 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, else ucr2 = UCR2_SRST | UCR2_IRTS; - if (termios->c_cflag & CRTSCTS) { + /* RTS must not be touched in RS485 mode, also the RS485 code is not written for DMA */ + if (termios->c_cflag & CRTSCTS && !(sport->rs485.flags & SER_RS485_ENABLED)) { if (sport->have_rtscts) { ucr2 &= ~UCR2_IRTS; ucr2 |= UCR2_CTSC; @@ -1438,8 +1518,13 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, ufcr = readl(sport->port.membase + UFCR); ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); - if (sport->dte_mode) + if (sport->dte_mode) { + ucr3 = readl(sport->port.membase + UCR3); + /* disable DCD/RI interrupts */ + ucr3 &= ~(UCR3_DCD | UCR3_RI | UCR3_DTREN | UCR3_DTRDEN); + writel(ucr3, sport->port.membase + UCR3); ufcr |= UFCR_DCEDTE; + } writel(ufcr, sport->port.membase + UFCR); writel(num, sport->port.membase + UBIR); @@ -1603,6 +1688,31 @@ static void imx_poll_put_char(struct uart_port *port, unsigned char c) } #endif +static int imx_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) +{ + struct imx_port *sport = (struct imx_port *)port; + + switch (cmd) { + case TIOCSRS485: + if (copy_from_user(&(sport->rs485), (struct serial_rs485 *) arg, + sizeof(struct serial_rs485))) + return -EFAULT; + if (sport->rs485.flags & SER_RS485_ENABLED) + imx_rs485_config(sport); + break; + + case TIOCGRS485: + if (copy_to_user((struct serial_rs485 *) arg, &(sport->rs485), + sizeof(struct serial_rs485))) + return -EFAULT; + break; + + default: + return -ENOIOCTLCMD; + } + return 0; +} + static struct uart_ops imx_pops = { .tx_empty = imx_tx_empty, .set_mctrl = imx_set_mctrl, @@ -1621,6 +1731,7 @@ static struct uart_ops imx_pops = { .request_port = imx_request_port, .config_port = imx_config_port, .verify_port = imx_verify_port, + .ioctl = imx_ioctl, #if defined(CONFIG_CONSOLE_POLL) .poll_get_char = imx_poll_get_char, .poll_put_char = imx_poll_put_char, @@ -1902,6 +2013,9 @@ static int serial_imx_probe_dt(struct imx_port *sport, if (of_get_property(np, "fsl,dte-mode", NULL)) sport->dte_mode = 1; + if (of_get_property(np, "linux,rs485-enabled-at-boot-time", NULL)) + sport->rs485.flags |= SER_RS485_ENABLED; + sport->devdata = of_id->data; return 0; @@ -1993,6 +2107,19 @@ static int serial_imx_probe(struct platform_device *pdev) imx_ports[sport->port.line] = sport; pdata = dev_get_platdata(&pdev->dev); + + if (sport->dte_mode == 1) { + unsigned int temp; + /* set the uart to dcedte mode immediately as pins do change directions + * and it is likely that we have outputs connected to outputs */ + /* disable DCD/RI interrupts */ + temp = readl(sport->port.membase + UCR3) & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN | UCR3_DTRDEN); + writel(temp, sport->port.membase + UCR3); + temp = readl(sport->port.membase + UFCR) | UFCR_DCEDTE; + writel(temp, sport->port.membase + UFCR); + } + + if (pdata && pdata->init) { ret = pdata->init(pdev); if (ret) diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c index 17ac14ff082b..1d9b57a07228 100644 --- a/drivers/usb/chipidea/ci_hdrc_imx.c +++ b/drivers/usb/chipidea/ci_hdrc_imx.c @@ -83,6 +83,8 @@ struct ci_hdrc_imx_data { struct regmap *anatop; struct pinctrl *pinctrl; struct pinctrl_state *pinctrl_hsic_active; + int reset_gpio; + int reset_active_low; }; /* Common functions shared by usbmisc drivers */ @@ -200,6 +202,31 @@ static int ci_hdrc_imx_notify_event(struct ci_hdrc *ci, unsigned event) return ret; } +static int setup_reset_gpio(struct platform_device *pdev, struct ci_hdrc_imx_data *data) +{ + int err = 0; + int gpio; + enum of_gpio_flags flags; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + + data->reset_gpio = -1; + gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &flags); + pr_info("%s:%d\n", __func__, gpio); + if (!gpio_is_valid(gpio)) + return 0; + + data->reset_active_low = flags & OF_GPIO_ACTIVE_LOW; + err = devm_gpio_request_one(dev, gpio, data->reset_active_low ? + GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, + "ehci_reset_gpio"); + if (err) + dev_err(dev, "can't request reset gpio %d", gpio); + data->reset_gpio = gpio; + + return err; +} + static int ci_hdrc_imx_probe(struct platform_device *pdev) { struct ci_hdrc_imx_data *data; @@ -224,6 +251,7 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, data); + setup_reset_gpio(pdev, data); data->usbmisc_data = usbmisc_get_init_data(&pdev->dev); if (IS_ERR(data->usbmisc_data)) @@ -406,6 +434,8 @@ static int ci_hdrc_imx_remove(struct platform_device *pdev) release_bus_freq(BUS_FREQ_HIGH); if (data->imx6_usb_charger_detection) imx6_usb_remove_charger(&data->charger); + if (gpio_is_valid(data->reset_gpio)) + gpio_set_value(data->reset_gpio, data->reset_active_low ? 0 : 1); return 0; } diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 098bfc64cfb9..9fe03c1e2acd 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -1099,14 +1099,16 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, case FBIOPUT_VSCREENINFO: if (copy_from_user(&var, argp, sizeof(var))) return -EFAULT; - if (!lock_fb_info(info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(info)) { + console_unlock(); + return -ENODEV; + } info->flags |= FBINFO_MISC_USEREVENT; ret = fb_set_var(info, &var); info->flags &= ~FBINFO_MISC_USEREVENT; - console_unlock(); unlock_fb_info(info); + console_unlock(); if (!ret && copy_to_user(argp, &var, sizeof(var))) ret = -EFAULT; break; @@ -1135,12 +1137,14 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, case FBIOPAN_DISPLAY: if (copy_from_user(&var, argp, sizeof(var))) return -EFAULT; - if (!lock_fb_info(info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(info)) { + console_unlock(); + return -ENODEV; + } ret = fb_pan_display(info, &var); - console_unlock(); unlock_fb_info(info); + console_unlock(); if (ret == 0 && copy_to_user(argp, &var, sizeof(var))) return -EFAULT; break; @@ -1175,23 +1179,27 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, break; } event.data = &con2fb; - if (!lock_fb_info(info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(info)) { + console_unlock(); + return -ENODEV; + } event.info = info; ret = fb_notifier_call_chain(FB_EVENT_SET_CONSOLE_MAP, &event); - console_unlock(); unlock_fb_info(info); + console_unlock(); break; case FBIOBLANK: - if (!lock_fb_info(info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(info)) { + console_unlock(); + return -ENODEV; + } info->flags |= FBINFO_MISC_USEREVENT; ret = fb_blank(info, arg); info->flags &= ~FBINFO_MISC_USEREVENT; - console_unlock(); unlock_fb_info(info); + console_unlock(); break; default: if (!lock_fb_info(info)) @@ -1649,12 +1657,15 @@ static int do_register_framebuffer(struct fb_info *fb_info) registered_fb[i] = fb_info; event.info = fb_info; - if (!lock_fb_info(fb_info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(fb_info)) { + console_unlock(); + return -ENODEV; + } + fb_notifier_call_chain(FB_EVENT_FB_REGISTERED, &event); - console_unlock(); unlock_fb_info(fb_info); + console_unlock(); return 0; } @@ -1667,13 +1678,16 @@ static int do_unregister_framebuffer(struct fb_info *fb_info) if (i < 0 || i >= FB_MAX || registered_fb[i] != fb_info) return -EINVAL; - if (!lock_fb_info(fb_info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(fb_info)) { + console_unlock(); + return -ENODEV; + } + event.info = fb_info; ret = fb_notifier_call_chain(FB_EVENT_FB_UNBIND, &event); - console_unlock(); unlock_fb_info(fb_info); + console_unlock(); if (ret) return -EINVAL; diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c index ef476b02fbe5..53444ac19fe0 100644 --- a/drivers/video/fbsysfs.c +++ b/drivers/video/fbsysfs.c @@ -177,9 +177,12 @@ static ssize_t store_modes(struct device *device, if (i * sizeof(struct fb_videomode) != count) return -EINVAL; - if (!lock_fb_info(fb_info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(fb_info)) { + console_unlock(); + return -ENODEV; + } + list_splice(&fb_info->modelist, &old_list); fb_videomode_to_modelist((const struct fb_videomode *)buf, i, &fb_info->modelist); @@ -189,8 +192,8 @@ static ssize_t store_modes(struct device *device, } else fb_destroy_modelist(&old_list); - console_unlock(); unlock_fb_info(fb_info); + console_unlock(); return 0; } @@ -404,12 +407,16 @@ static ssize_t store_fbstate(struct device *device, state = simple_strtoul(buf, &last, 0); - if (!lock_fb_info(fb_info)) - return -ENODEV; console_lock(); + if (!lock_fb_info(fb_info)) { + console_unlock(); + return -ENODEV; + } + fb_set_suspend(fb_info, (int)state); - console_unlock(); + unlock_fb_info(fb_info); + console_unlock(); return count; } diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile index c0fec9e79727..008474cc766c 100644 --- a/drivers/video/mxc/Makefile +++ b/drivers/video/mxc/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_FB_MXC_MIPI_DSI) += mipi_dsi.o obj-$(CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL) += mxcfb_hx8369_wvga.o obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o -obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_dispdrv.o mxc_lcdif.o mxc_ipuv3_fb.o +obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_dispdrv.o mxc_lcdif.o mxc_vdacif.o mxc_ipuv3_fb.o obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o obj-$(CONFIG_FB_MXS_SII902X) += mxsfb_sii902x.o obj-$(CONFIG_HANNSTAR_CABC) += hannstar_cabc.o diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c index 2c7d647cc89c..40e05d62b94d 100644 --- a/drivers/video/mxc/ldb.c +++ b/drivers/video/mxc/ldb.c @@ -78,6 +78,9 @@ #define LDB_SPLIT_MODE_EN 0x00000010 +#define LDB_CH0_MASKS LDB_CH0_MODE_MASK | LDB_DATA_WIDTH_CH0_MASK | LDB_BIT_MAP_CH0_MASK +#define LDB_CH1_MASKS LDB_CH1_MODE_MASK | LDB_DATA_WIDTH_CH1_MASK | LDB_BIT_MAP_CH1_MASK + enum { IMX6_LDB, }; @@ -136,6 +139,39 @@ static int g_ldb_mode; static struct fb_videomode ldb_modedb[] = { { + "LDB-AM-800600LTNQW-A0H", 60, 800, 600, 25000, + .left_margin = 40, + .right_margin = 88, + .hsync_len = 128, + .upper_margin = 1, + .lower_margin = 23, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = FB_MODE_IS_DETAILED,}, + { + "LDB-Fusion10", 62, 1024, 600, 20833, + .left_margin = 104, + .right_margin = 43, + .hsync_len = 5, + .upper_margin = 24, + .lower_margin = 20, + .vsync_len = 5, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = FB_MODE_IS_DETAILED,}, + { + "LDB-LG-LP156WF1", 60, 1920, 1080, 7220, + .left_margin = 80, + .right_margin = 48, + .hsync_len = 32, + .upper_margin = 23, + .lower_margin = 3, + .vsync_len = 5, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = FB_MODE_IS_DETAILED,}, + { "LDB-WXGA", 60, 1280, 800, 14065, 40, 40, 10, 3, @@ -469,14 +505,14 @@ int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v) #define LVDS0_MUX_CTL_MASK (LVDS_MUX_CTL_MASK << 6) #define LVDS1_MUX_CTL_MASK (LVDS_MUX_CTL_MASK << 8) #define ROUTE_IPU_DI(ipu, di) (((ipu << 1) | di) & LVDS_MUX_CTL_MASK) -static int ldb_ipu_ldb_route(int ipu, int di, struct ldb_data *ldb) +static int ldb_ipu_ldb_route(int ipu, int di, struct ldb_data *ldb, int channel) { uint32_t reg; - int channel; int shift; int mode = ldb->mode; reg = readl(ldb->gpr3_reg); + if (mode < LDB_SIN0) { reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK); reg |= (ROUTE_IPU_DI(ipu, di) << LVDS0_MUX_CTL_OFFS) | @@ -484,64 +520,58 @@ static int ldb_ipu_ldb_route(int ipu, int di, struct ldb_data *ldb) dev_dbg(&ldb->pdev->dev, "Dual/Split mode both channels route to IPU%d-DI%d\n", ipu, di); - } else if ((mode == LDB_SIN0) || (mode == LDB_SIN1)) { - reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK); - channel = mode - LDB_SIN0; - shift = LVDS0_MUX_CTL_OFFS + channel * LVDS_MUX_CTL_WIDTH; - reg |= ROUTE_IPU_DI(ipu, di) << shift; - dev_dbg(&ldb->pdev->dev, - "Single mode channel %d route to IPU%d-DI%d\n", - channel, ipu, di); } else { - static bool first = true; - - if (first) { - if (mode == LDB_SEP0) { - reg &= ~LVDS0_MUX_CTL_MASK; - channel = 0; - } else { - reg &= ~LVDS1_MUX_CTL_MASK; - channel = 1; - } - first = false; - } else { - if (mode == LDB_SEP0) { - reg &= ~LVDS1_MUX_CTL_MASK; - channel = 1; - } else { - reg &= ~LVDS0_MUX_CTL_MASK; - channel = 0; - } - } - shift = LVDS0_MUX_CTL_OFFS + channel * LVDS_MUX_CTL_WIDTH; + reg &= ~(LVDS_MUX_CTL_MASK << shift); reg |= ROUTE_IPU_DI(ipu, di) << shift; - dev_dbg(&ldb->pdev->dev, - "Separate mode channel %d route to IPU%d-DI%d\n", + "channel %d route to IPU%d-DI%d\n", channel, ipu, di); } writel(reg, ldb->gpr3_reg); - return 0; } +const static unsigned char lvds_enables[] = { + [LDB_SPL_DI0] = LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0 + | LDB_CH1_MODE_EN_TO_DI0, + [LDB_SPL_DI1] = LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI1 + | LDB_CH1_MODE_EN_TO_DI1, + [LDB_DUL_DI0] = LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0, + [LDB_DUL_DI1] = LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1, + [LDB_SIN0] = LDB_CH0_MODE_EN_TO_DI0, + [LDB_SIN0 + 1] = LDB_CH0_MODE_EN_TO_DI1, + [LDB_SIN0 + 2] = LDB_CH1_MODE_EN_TO_DI0, + [LDB_SIN0 + 3] = LDB_CH1_MODE_EN_TO_DI1 +}; + static int ldb_disp_init(struct mxc_dispdrv_handle *disp, struct mxc_dispdrv_setting *setting) { - int ret = 0, i, lvds_channel = 0; + int ret = 0, i; struct ldb_data *ldb = mxc_dispdrv_getdata(disp); struct fsl_mxc_ldb_platform_data *plat_data = ldb->pdev->dev.platform_data; struct resource *res; - uint32_t reg, setting_idx; - uint32_t ch_mask = 0, ch_val = 0; - uint32_t ipu_id, disp_id; + uint32_t reg; + uint32_t setting_idx = ldb->inited ? 1 : 0; + uint32_t ch_mask = 0; + uint32_t reg_set = 0, reg_clear = 0; + int lvds_channel = ldb->inited ? 1 : 0; + int mode; char di_clk[] = "ipu1_di0_sel"; char ldb_clk[] = "ldb_di0"; char div_3_5_clk[] = "di0_div_3_5"; char div_7_clk[] = "di0_div_7"; char div_sel_clk[] = "di0_div_sel"; + mode = (g_ldb_mode >= LDB_SPL_DI0) ? g_ldb_mode : plat_data->mode; + ldb->mode = mode; + + if ((mode == LDB_SIN1) || (mode == LDB_SEP1) || (mode == LDB_SPL_DI1)) + lvds_channel ^= 1; + setting->dev_id = plat_data->ipu_id; + setting->disp_id = lvds_channel; + /* if input format not valid, make RGB666 as default*/ if (!valid_mode(setting->if_fmt)) { dev_warn(&ldb->pdev->dev, "Input pixel format not valid" @@ -550,7 +580,6 @@ static int ldb_disp_init(struct mxc_dispdrv_handle *disp, } if (!ldb->inited) { - setting_idx = 0; res = platform_get_resource(ldb->pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&ldb->pdev->dev, "get iomem fail.\n"); @@ -562,157 +591,29 @@ static int ldb_disp_init(struct mxc_dispdrv_handle *disp, ldb->control_reg = ldb->reg + 2; ldb->gpr3_reg = ldb->reg + 3; - /* ipu selected by platform data setting */ - setting->dev_id = plat_data->ipu_id; - - reg = readl(ldb->control_reg); - - /* refrence resistor select */ - reg &= ~LDB_BGREF_RMODE_MASK; - if (plat_data->ext_ref) - reg |= LDB_BGREF_RMODE_EXT; - else - reg |= LDB_BGREF_RMODE_INT; - - /* TODO: now only use SPWG data mapping for both channel */ - reg &= ~(LDB_BIT_MAP_CH0_MASK | LDB_BIT_MAP_CH1_MASK); - reg |= LDB_BIT_MAP_CH0_SPWG | LDB_BIT_MAP_CH1_SPWG; - - /* channel mode setting */ - reg &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK); - reg &= ~(LDB_DATA_WIDTH_CH0_MASK | LDB_DATA_WIDTH_CH1_MASK); - - if (bits_per_pixel(setting->if_fmt) == 24) - reg |= LDB_DATA_WIDTH_CH0_24 | LDB_DATA_WIDTH_CH1_24; - else - reg |= LDB_DATA_WIDTH_CH0_18 | LDB_DATA_WIDTH_CH1_18; - - if (g_ldb_mode >= LDB_SPL_DI0) - ldb->mode = g_ldb_mode; - else - ldb->mode = plat_data->mode; - - if ((ldb->mode == LDB_SIN0) || (ldb->mode == LDB_SIN1)) { - ret = ldb->mode - LDB_SIN0; - if (plat_data->disp_id != ret) { - dev_warn(&ldb->pdev->dev, - "change IPU DI%d to IPU DI%d for LDB " - "channel%d.\n", - plat_data->disp_id, ret, ret); - plat_data->disp_id = ret; - } - } else if (((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1)) - && is_imx6_ldb(plat_data)) { - if (plat_data->disp_id == plat_data->sec_disp_id) { - dev_err(&ldb->pdev->dev, - "For LVDS separate mode," - "two DIs should be different!\n"); - return -EINVAL; - } - - if (((!plat_data->disp_id) && (ldb->mode == LDB_SEP1)) - || ((plat_data->disp_id) && - (ldb->mode == LDB_SEP0))) { - dev_dbg(&ldb->pdev->dev, - "LVDS separate mode:" - "swap DI configuration!\n"); - ipu_id = plat_data->ipu_id; - disp_id = plat_data->disp_id; - plat_data->ipu_id = plat_data->sec_ipu_id; - plat_data->disp_id = plat_data->sec_disp_id; - plat_data->sec_ipu_id = ipu_id; - plat_data->sec_disp_id = disp_id; - } - } - - if (ldb->mode == LDB_SPL_DI0) { - reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0 - | LDB_CH1_MODE_EN_TO_DI0; - setting->disp_id = 0; - } else if (ldb->mode == LDB_SPL_DI1) { - reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI1 - | LDB_CH1_MODE_EN_TO_DI1; - setting->disp_id = 1; - } else if (ldb->mode == LDB_DUL_DI0) { - reg &= ~LDB_SPLIT_MODE_EN; - reg |= LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0; - setting->disp_id = 0; - } else if (ldb->mode == LDB_DUL_DI1) { - reg &= ~LDB_SPLIT_MODE_EN; - reg |= LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1; - setting->disp_id = 1; - } else if (ldb->mode == LDB_SIN0) { - reg &= ~LDB_SPLIT_MODE_EN; - setting->disp_id = plat_data->disp_id; - if (setting->disp_id == 0) - reg |= LDB_CH0_MODE_EN_TO_DI0; - else - reg |= LDB_CH0_MODE_EN_TO_DI1; - ch_mask = LDB_CH0_MODE_MASK; - ch_val = reg & LDB_CH0_MODE_MASK; - } else if (ldb->mode == LDB_SIN1) { - reg &= ~LDB_SPLIT_MODE_EN; - setting->disp_id = plat_data->disp_id; - if (setting->disp_id == 0) - reg |= LDB_CH1_MODE_EN_TO_DI0; - else - reg |= LDB_CH1_MODE_EN_TO_DI1; - ch_mask = LDB_CH1_MODE_MASK; - ch_val = reg & LDB_CH1_MODE_MASK; - } else { /* separate mode*/ - setting->disp_id = plat_data->disp_id; - - /* first output is LVDS0 or LVDS1 */ - if (ldb->mode == LDB_SEP0) - lvds_channel = 0; - else - lvds_channel = 1; - - reg &= ~LDB_SPLIT_MODE_EN; - - if ((lvds_channel == 0) && (setting->disp_id == 0)) - reg |= LDB_CH0_MODE_EN_TO_DI0; - else if ((lvds_channel == 0) && (setting->disp_id == 1)) - reg |= LDB_CH0_MODE_EN_TO_DI1; - else if ((lvds_channel == 1) && (setting->disp_id == 0)) - reg |= LDB_CH1_MODE_EN_TO_DI0; - else - reg |= LDB_CH1_MODE_EN_TO_DI1; - ch_mask = lvds_channel ? LDB_CH1_MODE_MASK : - LDB_CH0_MODE_MASK; - ch_val = reg & ch_mask; - - if (bits_per_pixel(setting->if_fmt) == 24) { - if (lvds_channel == 0) - reg &= ~LDB_DATA_WIDTH_CH1_24; - else - reg &= ~LDB_DATA_WIDTH_CH0_24; - } else { - if (lvds_channel == 0) - reg &= ~LDB_DATA_WIDTH_CH1_18; - else - reg &= ~LDB_DATA_WIDTH_CH0_18; - } - } - - writel(reg, ldb->control_reg); - if (ldb->mode < LDB_SIN0) { + /* reference resistor select */ + reg_clear |= LDB_BGREF_RMODE_MASK; + if (!plat_data->ext_ref) + reg_set |= LDB_BGREF_RMODE_EXT; + + if (ldb->mode < LDB_SIN0) { + reg_clear |= LDB_CH0_MASKS | LDB_CH1_MASKS + | LDB_SPLIT_MODE_EN; + if (bits_per_pixel(setting->if_fmt) == 24) + reg_set |= LDB_DATA_WIDTH_CH0_24 | LDB_DATA_WIDTH_CH1_24; + reg_set |= lvds_enables[ldb->mode]; ch_mask = LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK; - ch_val = reg & (LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK); + } else { + setting->disp_id = plat_data->disp_id; } - } else { /* second time for separate mode */ - if ((ldb->mode == LDB_SPL_DI0) || - (ldb->mode == LDB_SPL_DI1) || - (ldb->mode == LDB_DUL_DI0) || - (ldb->mode == LDB_DUL_DI1) || - (ldb->mode == LDB_SIN0) || - (ldb->mode == LDB_SIN1)) { + } else { + /* second time for separate mode */ + if ((ldb->mode != LDB_SEP0) && (ldb->mode != LDB_SEP1)) { dev_err(&ldb->pdev->dev, "for second ldb disp" "ldb mode should in separate mode\n"); return -EINVAL; } - setting_idx = 1; if (is_imx6_ldb(plat_data)) { setting->dev_id = plat_data->sec_ipu_id; setting->disp_id = plat_data->sec_disp_id; @@ -720,75 +621,71 @@ static int ldb_disp_init(struct mxc_dispdrv_handle *disp, setting->dev_id = plat_data->ipu_id; setting->disp_id = !plat_data->disp_id; } - if (setting->disp_id == ldb->setting[0].di) { + if ((setting->disp_id == ldb->setting[0].di) && (setting->dev_id == ldb->setting[0].ipu)) { dev_err(&ldb->pdev->dev, "Err: for second ldb disp in" - "separate mode, DI should be different!\n"); + "separate mode, IPU/DI should be different!\n"); return -EINVAL; } + } + if (ldb->mode >= LDB_SIN0) { + int lvds_ch_disp = (is_imx6_ldb(plat_data)) ? lvds_channel + : setting->disp_id; - /* second output is LVDS0 or LVDS1 */ - if (ldb->mode == LDB_SEP0) - lvds_channel = 1; - else - lvds_channel = 0; - - reg = readl(ldb->control_reg); - if ((lvds_channel == 0) && (setting->disp_id == 0)) - reg |= LDB_CH0_MODE_EN_TO_DI0; - else if ((lvds_channel == 0) && (setting->disp_id == 1)) - reg |= LDB_CH0_MODE_EN_TO_DI1; - else if ((lvds_channel == 1) && (setting->disp_id == 0)) - reg |= LDB_CH1_MODE_EN_TO_DI0; - else - reg |= LDB_CH1_MODE_EN_TO_DI1; - ch_mask = lvds_channel ? LDB_CH1_MODE_MASK : + reg_clear |= ((lvds_channel ? LDB_CH1_MASKS : LDB_CH0_MASKS) + | LDB_SPLIT_MODE_EN); + reg_set |= lvds_enables[LDB_SIN0 + ((lvds_channel << 1) + | lvds_ch_disp)]; + if (bits_per_pixel(setting->if_fmt) == 24) + reg_set |= (lvds_channel ? LDB_DATA_WIDTH_CH1_24 + : LDB_DATA_WIDTH_CH0_24); + ch_mask = lvds_channel ? LDB_CH1_MODE_MASK : LDB_CH0_MODE_MASK; - ch_val = reg & ch_mask; - - if (bits_per_pixel(setting->if_fmt) == 24) { - if (lvds_channel == 0) - reg |= LDB_DATA_WIDTH_CH0_24; - else - reg |= LDB_DATA_WIDTH_CH1_24; - } else { - if (lvds_channel == 0) - reg |= LDB_DATA_WIDTH_CH0_18; - else - reg |= LDB_DATA_WIDTH_CH1_18; - } - writel(reg, ldb->control_reg); } + reg = readl(ldb->control_reg); + reg &= ~reg_clear; + reg |= reg_set; + writel(reg, ldb->control_reg); - /* get clocks */ - if (is_imx6_ldb(plat_data) && - ((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1))) { - ldb_clk[6] += lvds_channel; - div_3_5_clk[2] += lvds_channel; - div_7_clk[2] += lvds_channel; - div_sel_clk[2] += lvds_channel; - } else { - ldb_clk[6] += setting->disp_id; - div_3_5_clk[2] += setting->disp_id; - div_7_clk[2] += setting->disp_id; - div_sel_clk[2] += setting->disp_id; - } + /* clock setting */ + ldb_clk[6] = '0' + lvds_channel; + div_3_5_clk[2] = '0' + lvds_channel; + div_7_clk[2] = '0' + lvds_channel; + div_sel_clk[2] = '0' + lvds_channel; ldb->setting[setting_idx].ldb_di_clk = clk_get(&ldb->pdev->dev, - ldb_clk); + ldb_clk); if (IS_ERR(ldb->setting[setting_idx].ldb_di_clk)) { dev_err(&ldb->pdev->dev, "get ldb clk failed\n"); + if (!ldb->inited) + iounmap(ldb->reg); return PTR_ERR(ldb->setting[setting_idx].ldb_di_clk); } + di_clk[3] = '1' + setting->dev_id; + di_clk[7] = '0' + setting->disp_id; + ldb->setting[setting_idx].di_clk = clk_get(&ldb->pdev->dev, di_clk); + if (IS_ERR(ldb->setting[setting_idx].di_clk)) { + dev_err(&ldb->pdev->dev, "get di clk0 failed\n"); + if (!ldb->inited) + iounmap(ldb->reg); + return PTR_ERR(ldb->setting[setting_idx].di_clk); + } + + dev_dbg(&ldb->pdev->dev, "ldb_clk to di clk: %s -> %s\n", ldb_clk, di_clk); + ldb->setting[setting_idx].div_3_5_clk = clk_get(&ldb->pdev->dev, div_3_5_clk); if (IS_ERR(ldb->setting[setting_idx].div_3_5_clk)) { dev_err(&ldb->pdev->dev, "get div 3.5 clk failed\n"); + if (!ldb->inited) + iounmap(ldb->reg); return PTR_ERR(ldb->setting[setting_idx].div_3_5_clk); } ldb->setting[setting_idx].div_7_clk = clk_get(&ldb->pdev->dev, div_7_clk); if (IS_ERR(ldb->setting[setting_idx].div_7_clk)) { - dev_err(&ldb->pdev->dev, "get div 7 clk failed\n"); + dev_err(&ldb->pdev->dev, "get %s failed\n", div_7_clk); + if (!ldb->inited) + iounmap(ldb->reg); return PTR_ERR(ldb->setting[setting_idx].div_7_clk); } @@ -796,23 +693,16 @@ static int ldb_disp_init(struct mxc_dispdrv_handle *disp, div_sel_clk); if (IS_ERR(ldb->setting[setting_idx].div_sel_clk)) { dev_err(&ldb->pdev->dev, "get div sel clk failed\n"); + if (!ldb->inited) + iounmap(ldb->reg); return PTR_ERR(ldb->setting[setting_idx].div_sel_clk); } - di_clk[3] += setting->dev_id; - di_clk[7] += setting->disp_id; - ldb->setting[setting_idx].di_clk = clk_get(&ldb->pdev->dev, - di_clk); - if (IS_ERR(ldb->setting[setting_idx].di_clk)) { - dev_err(&ldb->pdev->dev, "get di clk failed\n"); - return PTR_ERR(ldb->setting[setting_idx].di_clk); - } - ldb->setting[setting_idx].ch_mask = ch_mask; - ldb->setting[setting_idx].ch_val = ch_val; + ldb->setting[setting_idx].ch_val = reg & ch_mask; if (is_imx6_ldb(plat_data)) - ldb_ipu_ldb_route(setting->dev_id, setting->disp_id, ldb); + ldb_ipu_ldb_route(setting->dev_id, setting->disp_id, ldb, lvds_channel); /* must use spec video mode defined by driver */ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str, @@ -821,13 +711,23 @@ static int ldb_disp_init(struct mxc_dispdrv_handle *disp, fb_videomode_to_var(&setting->fbi->var, &ldb_modedb[0]); INIT_LIST_HEAD(&setting->fbi->modelist); - for (i = 0; i < ldb_modedb_sz; i++) { + { struct fb_videomode m; + fb_var_to_videomode(&m, &setting->fbi->var); - if (fb_mode_is_equal(&m, &ldb_modedb[i])) { - fb_add_videomode(&ldb_modedb[i], - &setting->fbi->modelist); - break; + if (0) pr_info("%s: ret=%d, %dx%d\n", __func__, ret, m.xres, m.yres); + if (0) pr_info("%s:r=%d, x=%d, y=%d, p=%d, l=%d, r=%d, upper=%d, lower=%d, h=%d, v=%d\n", + __func__, m.refresh, m.xres, m.yres, m.pixclock, + m.left_margin, m.right_margin, + m.upper_margin, m.lower_margin, + m.hsync_len, m.vsync_len); + + for (i = 0; i < ldb_modedb_sz; i++) { + if (!fb_mode_is_equal(&m, &ldb_modedb[i])) { + if (0) pr_info("%s: %dx%d\n", __func__, ldb_modedb[i].xres, ldb_modedb[i].yres); + fb_add_videomode(&ldb_modedb[i], + &setting->fbi->modelist); + } } } diff --git a/drivers/video/mxc/mxc_hdmi.c b/drivers/video/mxc/mxc_hdmi.c index e510025f7bad..75825092b731 100644 --- a/drivers/video/mxc/mxc_hdmi.c +++ b/drivers/video/mxc/mxc_hdmi.c @@ -80,6 +80,10 @@ #define YCBCR422_8BITS 3 #define XVYCC444 4 +static int only_cea; +module_param(only_cea, bool, 0644); +MODULE_PARM_DESC(only_cea, "Allow only CEA modes"); + /* * We follow a flowchart which is in the "Synopsys DesignWare Courses * HDMI Transmitter Controller User Guide, 1.30a", section 3.1 @@ -169,11 +173,11 @@ struct mxc_hdmi { bool dft_mode_set; char *dft_mode_str; int default_bpp; - u8 latest_intr_stat; bool irq_enabled; spinlock_t irq_lock; bool phy_enabled; struct fb_videomode default_mode; + struct fb_videomode previous_mode; struct fb_videomode previous_non_vga_mode; bool requesting_vga_for_initialization; @@ -942,6 +946,9 @@ static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi, return data; } +static int keepalive=1; +module_param(keepalive, int, 0644); +MODULE_PARM_DESC(keepalive, "Allow only CEA modes"); /* "Power-down enable (active low)" * That mean that power up == 1! */ @@ -1267,9 +1274,6 @@ static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi) || (hdmi->blank != FB_BLANK_UNBLANK)) return; - if (!hdmi->hdmi_data.video_mode.mDVI) - hdmi_enable_overflow_interrupts(); - /*check csc whether needed activated in HDMI mode */ cscon = (isColorSpaceConversion(hdmi) && !hdmi->hdmi_data.video_mode.mDVI); @@ -1286,6 +1290,8 @@ static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi) } hdmi->phy_enabled = true; + if (!hdmi->hdmi_data.video_mode.mDVI) + hdmi_enable_overflow_interrupts(); } static void hdmi_config_AVI(struct mxc_hdmi *hdmi) @@ -1800,7 +1806,7 @@ static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi) mode = &hdmi->fbi->monspecs.modedb[i]; if (!(mode->vmode & FB_VMODE_INTERLACED) && - (mxc_edid_mode_to_vic(mode) != 0)) { + (!only_cea || mxc_edid_mode_to_vic(mode))) { dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i); dev_dbg(&hdmi->pdev->dev, @@ -1928,8 +1934,9 @@ static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi) mxc_hdmi_edid_rebuild_modelist(hdmi); break; - /* Nothing to do if EDID same */ + /* Rebuild even if they're the same in case only_cea changed */ case HDMI_EDID_SAME: + mxc_hdmi_edid_rebuild_modelist(hdmi); break; case HDMI_EDID_FAIL: @@ -1979,74 +1986,70 @@ static void hotplug_worker(struct work_struct *work) struct delayed_work *delay_work = to_delayed_work(work); struct mxc_hdmi *hdmi = container_of(delay_work, struct mxc_hdmi, hotplug_work); - u32 phy_int_stat, phy_int_pol, phy_int_mask; - u8 val; + u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0; unsigned long flags; char event_string[32]; + int isalive = 0; char *envp[] = { event_string, NULL }; - phy_int_stat = hdmi->latest_intr_stat; - phy_int_pol = hdmi_readb(HDMI_PHY_POL0); - dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x, phy_int_pol=0x%x\n", - phy_int_stat, phy_int_pol); + hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0); + hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0); + + dev_dbg(&hdmi->pdev->dev, "hdmi_phy_stat0=0x%x, hdmi_phy_pol0=0x%x\n", + hdmi_phy_stat0, hdmi_phy_pol0); + + /* Make HPD intr active low to capture unplug event or + * active high to capture plugin event */ + hdmi_writeb((HDMI_DVI_STAT & ~hdmi_phy_stat0), HDMI_PHY_POL0); /* check cable status */ - if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) { - /* cable connection changes */ - if (phy_int_pol & HDMI_PHY_HPD) { - /* Plugin event */ - dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n"); - mxc_hdmi_cable_connected(hdmi); - - /* Make HPD intr active low to capture unplug event */ - val = hdmi_readb(HDMI_PHY_POL0); - val &= ~HDMI_PHY_HPD; - hdmi_writeb(val, HDMI_PHY_POL0); - - hdmi_set_cable_state(1); - - sprintf(event_string, "EVENT=plugin"); - kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); -#ifdef CONFIG_MXC_HDMI_CEC - mxc_hdmi_cec_handle(0x80); -#endif - } else if (!(phy_int_pol & HDMI_PHY_HPD)) { - /* Plugout event */ - dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n"); - hdmi_set_cable_state(0); - mxc_hdmi_abort_stream(); - mxc_hdmi_cable_disconnected(hdmi); + if (hdmi_phy_stat0 & HDMI_DVI_STAT) { + /* Plugin event */ + dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n"); + mxc_hdmi_cable_connected(hdmi); - /* Make HPD intr active high to capture plugin event */ - val = hdmi_readb(HDMI_PHY_POL0); - val |= HDMI_PHY_HPD; - hdmi_writeb(val, HDMI_PHY_POL0); + hdmi_set_cable_state(1); - sprintf(event_string, "EVENT=plugout"); - kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); + sprintf(event_string, "EVENT=plugin"); + kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); +#ifdef CONFIG_MXC_HDMI_CEC + mxc_hdmi_cec_handle(0x80); +#endif + if (keepalive) + hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0); + isalive=1; + } else if (!keepalive) { + /* Plugout event */ + dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n"); + hdmi_set_cable_state(0); + mxc_hdmi_abort_stream(); + mxc_hdmi_cable_disconnected(hdmi); + + sprintf(event_string, "EVENT=plugout"); + kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); #ifdef CONFIG_MXC_HDMI_CEC - mxc_hdmi_cec_handle(0x100); + mxc_hdmi_cec_handle(0x100); #endif - } else - dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n"); } /* Lock here to ensure full powerdown sequence * completed before next interrupt processed */ spin_lock_irqsave(&hdmi->irq_lock, flags); - /* Re-enable HPD interrupts */ - phy_int_mask = hdmi_readb(HDMI_PHY_MASK0); - phy_int_mask &= ~HDMI_PHY_HPD; - hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0); + if (!(keepalive || isalive)) { + /* Re-enable HPD interrupts */ + hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0); + hdmi_phy_mask0 &= ~HDMI_DVI_STAT; + hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0); - /* Unmute interrupts */ - hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); + /* Unmute interrupts */ + hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0); - if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) - mxc_hdmi_clear_overflow(hdmi); + if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) + mxc_hdmi_clear_overflow(hdmi); + } spin_unlock_irqrestore(&hdmi->irq_lock, flags); } @@ -2069,7 +2072,7 @@ static void hdcp_hdp_worker(struct work_struct *work) static irqreturn_t mxc_hdmi_hotplug(int irq, void *data) { struct mxc_hdmi *hdmi = data; - u8 val, intr_stat; + u8 val; unsigned long flags; spin_lock_irqsave(&hdmi->irq_lock, flags); @@ -2091,25 +2094,22 @@ static irqreturn_t mxc_hdmi_hotplug(int irq, void *data) * HDMI registers. */ /* Capture status - used in hotplug_worker ISR */ - intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0); - - if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + if (hdmi_readb(HDMI_IH_PHY_STAT0) & HDMI_DVI_IH_STAT) { dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n"); - hdmi->latest_intr_stat = intr_stat; /* Mute interrupts until handled */ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0); - val |= HDMI_IH_MUTE_PHY_STAT0_HPD; + val |= HDMI_DVI_IH_STAT; hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0); val = hdmi_readb(HDMI_PHY_MASK0); - val |= HDMI_PHY_HPD; + val |= HDMI_DVI_STAT; hdmi_writeb(val, HDMI_PHY_MASK0); /* Clear Hotplug interrupts */ - hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0); schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20)); } @@ -2141,6 +2141,9 @@ static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event) dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__); + /* Save mode as 'previous_mode' so that we can know if mode changed. */ + memcpy(&hdmi->previous_mode, &m, sizeof(struct fb_videomode)); + hdmi->vic = 0; if (!hdmi->requesting_vga_for_initialization) { /* Save mode if this isn't the result of requesting @@ -2261,13 +2264,13 @@ static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi) HDMI_PHY_I2CM_CTLINT_ADDR); /* enable cable hot plug irq */ - hdmi_writeb((u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); + hdmi_writeb((u8)~HDMI_DVI_STAT, HDMI_PHY_MASK0); /* Clear Hotplug interrupts */ - hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0); /* Unmute interrupts */ - hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); + hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0); hdmi->fb_reg = true; @@ -2280,6 +2283,7 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb, { struct fb_event *event = v; struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb); + struct fb_videomode *mode; if (strcmp(event->info->fix.id, hdmi->fbi->fix.id)) return 0; @@ -2299,7 +2303,10 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb, case FB_EVENT_MODE_CHANGE: dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n"); - if (hdmi->fb_reg) + mode = (struct fb_videomode *)event->data; + if ((hdmi->fb_reg) && + (mode != NULL) && + !fb_mode_is_equal(&hdmi->previous_mode, mode)) mxc_hdmi_setup(hdmi, val); break; @@ -2579,10 +2586,10 @@ static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp, /* Configure registers related to HDMI interrupt * generation before registering IRQ. */ - hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0); + hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0); /* Clear Hotplug interrupts */ - hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0); hdmi->nb.notifier_call = mxc_hdmi_fb_event; ret = fb_register_client(&hdmi->nb); diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index 3cf386f2b78d..a30dab1bf11f 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -607,6 +607,15 @@ static int mxcfb_set_par(struct fb_info *fbi) dev_dbg(fbi->device, "pixclock = %ul Hz\n", (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + dev_info(fbi->device,"%dx%d h_sync,r,l: %d,%d,%d v_sync,l,u: %d,%d,%d pixclock=%u Hz\n", + fbi->var.xres, fbi->var.yres, + fbi->var.hsync_len, + fbi->var.right_margin, + fbi->var.left_margin, + fbi->var.vsync_len, + fbi->var.lower_margin, + fbi->var.upper_margin, + (u32)(PICOS2KHZ(fbi->var.pixclock) * 1000UL)); if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di, (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, @@ -1953,6 +1962,10 @@ static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi) name[5] += pdev->id; if (fb_get_options(name, &options)) { + if (options && !strncmp(options, "off", 3)) { + dev_info(&pdev->dev, "%s is turned off!\n", name); + return -ENODEV; + } dev_err(&pdev->dev, "Can't get fb option for %s!\n", name); return -ENODEV; } @@ -2239,8 +2252,10 @@ static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg) } static bool ipu_usage[2][2]; -static int ipu_test_set_usage(int ipu, int di) +static int ipu_test_set_usage(unsigned ipu, unsigned di) { + if ((ipu >= 2) || (di >= 2)) + return -EINVAL; if (ipu_usage[ipu][di]) return -EBUSY; else @@ -2250,6 +2265,8 @@ static int ipu_test_set_usage(int ipu, int di) static void ipu_clear_usage(int ipu, int di) { + if ((ipu >= 2) || (di >= 2)) + return; ipu_usage[ipu][di] = false; } @@ -2427,7 +2444,7 @@ static int mxcfb_probe(struct platform_device *pdev) mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF; mxcfbi->ipu_ch = MEM_BG_SYNC; /* Unblank the primary fb only by default */ - if (pdev->id == 0) + if (1) //if (pdev->id == 0) mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK; else mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN; @@ -2468,7 +2485,7 @@ static int mxcfb_probe(struct platform_device *pdev) mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK; mxcfbi->ipu_alp_ch_irq = -1; mxcfbi->ipu_ch = MEM_DC_SYNC; - mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN; + mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK; ret = mxcfb_register(fbi); if (ret < 0) diff --git a/drivers/video/mxc/mxc_lcdif.c b/drivers/video/mxc/mxc_lcdif.c index a0cca1c347fb..e05e10584f36 100644 --- a/drivers/video/mxc/mxc_lcdif.c +++ b/drivers/video/mxc/mxc_lcdif.c @@ -37,6 +37,42 @@ struct mxc_lcdif_data { static struct fb_videomode lcdif_modedb[] = { { + /* 1024x600 @ 59 Hz , pixel clk @ 45 MHz */ /* 22222 ps*/ + "FusionF10A", 59, 1024, 600, 22222, + .left_margin = 104, + .right_margin = 43, + .hsync_len = 5, + .upper_margin = 24, + .lower_margin = 20, + .vsync_len = 5, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { + /* 800x480 @ 60 Hz , pixel clk @ 33.26MHz */ + "FusionF07A", 60, 800, 480, 30066, + .left_margin = 88, + .right_margin = 40, + .hsync_len = 128, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { + /* 800x480 @ 60 Hz , pixel clk @ 33.26MHz */ + "EDT-WVGA", 60, 800, 480, 30066, + .left_margin = 88, + .right_margin = 40, + .hsync_len = 128, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, FB_SYNC_CLK_LAT_FALL, @@ -48,6 +84,30 @@ static struct fb_videomode lcdif_modedb[] = { FB_SYNC_CLK_LAT_FALL, FB_VMODE_NONINTERLACED, 0,}, + { + /* 640x480 @ 60 Hz , pixel clk @ 25.175MHz */ + "EDT-VGA", 60, 640, 480, 39721, + .left_margin = 114, + .right_margin = 16, + .hsync_len = 30, + .upper_margin = 32, + .lower_margin = 10, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { + /* 480x272 @ 60 Hz , pixel clk @ 25.175MHz */ + "EDT-480x272", 60, 480, 272, 111111, + .left_margin = 2, + .right_margin = 2, + .hsync_len = 41, + .upper_margin = 2, + .lower_margin = 2, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, }; static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb); diff --git a/drivers/video/mxc/mxc_vdacif.c b/drivers/video/mxc/mxc_vdacif.c new file mode 100644 index 000000000000..e0636122641f --- /dev/null +++ b/drivers/video/mxc/mxc_vdacif.c @@ -0,0 +1,354 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * copy of mxc_lcdif.c + * adds a second parallel output which drives a Video DAC + * available on the second IPU, first DI on a + * Apalis iMX6 module + */ + +#include <linux/init.h> +#include <linux/ipu.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mxcfb.h> +#include <linux/of_device.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> + +#include "mxc_dispdrv.h" + +struct mxc_vdac_platform_data { + u32 default_ifmt; + u32 ipu_id; + u32 disp_id; +}; + +struct mxc_vdacif_data { + struct platform_device *pdev; + struct mxc_dispdrv_handle *disp_vdacif; +}; + +#define DISPDRV_LCD "vdac" + +static struct fb_videomode vdacif_modedb[] = { + /* 0 640x350-85 VESA */ + { NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, + FB_MODE_IS_VESA}, + /* 1 640x400-85 VESA */ + { NULL, 85, 640, 400, 31746, 96, 32, 41, 01, 64, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, + FB_MODE_IS_VESA }, + /* 2 720x400-85 VESA */ + { NULL, 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, + FB_MODE_IS_VESA }, + /* 3 640x480-60 VESA */ + { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 4 640x480-72 VESA */ + { NULL, 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 5 640x480-75 VESA */ + { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 6 640x480-85 VESA */ + { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 7 800x600-56 VESA */ + { NULL, 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 8 800x600-60 VESA */ + { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 9 800x600-72 VESA */ + { NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 10 800x600-75 VESA */ + { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 11 800x600-85 VESA */ + { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 12 1024x768i-43 VESA */ + { NULL, 43, 1024, 768, 22271, 56, 8, 41, 0, 176, 8, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_INTERLACED, FB_MODE_IS_VESA }, + /* 13 1024x768-60 VESA */ + { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 14 1024x768-70 VESA */ + { NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 15 1024x768-75 VESA */ + { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 16 1024x768-85 VESA */ + { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 17 1152x864-75 VESA */ + { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 18 1280x960-60 VESA */ + { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 19 1280x960-85 VESA */ + { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 20 1280x1024-60 VESA */ + { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 21 1280x1024-75 VESA */ + { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 22 1280x1024-85 VESA */ + { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 23 1600x1200-60 VESA */ + { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 24 1600x1200-65 VESA */ + { NULL, 65, 1600, 1200, 5698, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 25 1600x1200-70 VESA */ + { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 26 1600x1200-75 VESA */ + { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 27 1600x1200-85 VESA */ + { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 28 1792x1344-60 VESA */ + { NULL, 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 29 1792x1344-75 VESA */ + { NULL, 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 30 1856x1392-60 VESA */ + { NULL, 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 31 1856x1392-75 VESA */ + { NULL, 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 32 1920x1440-60 VESA */ + { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 33 1920x1440-75 VESA */ + { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */ + { NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED }, + /* #16: 1920x1080p@60Hz 16:9 */ + { NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, 0 }, +}; +static int vdacif_modedb_sz = ARRAY_SIZE(vdacif_modedb); + +static int vdacif_init(struct mxc_dispdrv_handle *disp, + struct mxc_dispdrv_setting *setting) +{ + int ret, i; + struct mxc_vdacif_data *vdacif = mxc_dispdrv_getdata(disp); + struct mxc_vdac_platform_data *plat_data + = vdacif->pdev->dev.platform_data; + struct fb_videomode *modedb = vdacif_modedb; + int modedb_sz = vdacif_modedb_sz; + + /* use platform defined ipu/di */ + setting->dev_id = plat_data->ipu_id; + setting->disp_id = plat_data->disp_id; + + ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str, + modedb, modedb_sz, NULL, setting->default_bpp); + if (!ret) { + fb_videomode_to_var(&setting->fbi->var, &modedb[0]); + setting->if_fmt = plat_data->default_ifmt; + } + /* Peter's VDAC requires OE to be low active */ + setting->fbi->var.sync |= FB_SYNC_OE_LOW_ACT; + + INIT_LIST_HEAD(&setting->fbi->modelist); + for (i = 0; i < modedb_sz; i++) { + struct fb_videomode m; + fb_var_to_videomode(&m, &setting->fbi->var); + if (fb_mode_is_equal(&m, &modedb[i])) { + fb_add_videomode(&modedb[i], + &setting->fbi->modelist); + break; + } + } + + return ret; +} + +void vdacif_deinit(struct mxc_dispdrv_handle *disp) +{ + /*TODO*/ +} + +static struct mxc_dispdrv_driver vdacif_drv = { + .name = DISPDRV_LCD, + .init = vdacif_init, + .deinit = vdacif_deinit, +}; + +static int vdac_get_of_property(struct platform_device *pdev, + struct mxc_vdac_platform_data *plat_data) +{ + struct device_node *np = pdev->dev.of_node; + int err; + u32 ipu_id, disp_id; + const char *default_ifmt; + + err = of_property_read_string(np, "default_ifmt", &default_ifmt); + if (err) { + dev_dbg(&pdev->dev, "get of property default_ifmt fail\n"); + return err; + } + err = of_property_read_u32(np, "ipu_id", &ipu_id); + if (err) { + dev_dbg(&pdev->dev, "get of property ipu_id fail\n"); + return err; + } + err = of_property_read_u32(np, "disp_id", &disp_id); + if (err) { + dev_dbg(&pdev->dev, "get of property disp_id fail\n"); + return err; + } + + if ( (ipu_id == 0) || (disp_id == 1) ) { + dev_err(&pdev->dev, "wrong ipu_id %x or disp_id %x, expected 1, 0\n", ipu_id, disp_id); + } + plat_data->ipu_id = ipu_id; + plat_data->disp_id = disp_id; + if (!strncmp(default_ifmt, "RGB565", 6)) + plat_data->default_ifmt = IPU_PIX_FMT_RGB565; + else { + dev_err(&pdev->dev, "err default_ifmt!\n"); + return -ENOENT; + } + + return err; +} + +static int mxc_vdacif_probe(struct platform_device *pdev) +{ + int ret; + struct pinctrl *pinctrl; + struct mxc_vdacif_data *vdacif; + struct mxc_vdac_platform_data *plat_data; + + dev_dbg(&pdev->dev, "%s enter\n", __func__); + dev_err(&pdev->dev, "%s enter\n", __func__); + vdacif = devm_kzalloc(&pdev->dev, sizeof(struct mxc_vdacif_data), + GFP_KERNEL); + if (!vdacif) + return -ENOMEM; + plat_data = devm_kzalloc(&pdev->dev, + sizeof(struct mxc_vdac_platform_data), + GFP_KERNEL); + if (!plat_data) + return -ENOMEM; + pdev->dev.platform_data = plat_data; + + ret = vdac_get_of_property(pdev, plat_data); + if (ret < 0) { + dev_err(&pdev->dev, "get vdac of property fail\n"); + return ret; + } + + pinctrl = devm_pinctrl_get_select_default(&pdev->dev); + if (IS_ERR(pinctrl)) { + dev_err(&pdev->dev, "can't get/select pinctrl\n"); + return PTR_ERR(pinctrl); + } + + vdacif->pdev = pdev; + vdacif->disp_vdacif = mxc_dispdrv_register(&vdacif_drv); + mxc_dispdrv_setdata(vdacif->disp_vdacif, vdacif); + + dev_set_drvdata(&pdev->dev, vdacif); + dev_dbg(&pdev->dev, "%s exit\n", __func__); + + return ret; +} + +static int mxc_vdacif_remove(struct platform_device *pdev) +{ + struct mxc_vdacif_data *vdacif = dev_get_drvdata(&pdev->dev); + + mxc_dispdrv_puthandle(vdacif->disp_vdacif); + mxc_dispdrv_unregister(vdacif->disp_vdacif); + kfree(vdacif); + return 0; +} + +static const struct of_device_id imx_vdac_dt_ids[] = { + { .compatible = "fsl,vdac"}, + { /* sentinel */ } +}; +static struct platform_driver mxc_vdacif_driver = { + .driver = { + .name = "mxc_vdacif", + .of_match_table = imx_vdac_dt_ids, + }, + .probe = mxc_vdacif_probe, + .remove = mxc_vdacif_remove, +}; + +static int __init mxc_vdacif_init(void) +{ + return platform_driver_register(&mxc_vdacif_driver); +} + +static void __exit mxc_vdacif_exit(void) +{ + platform_driver_unregister(&mxc_vdacif_driver); +} + +module_init(mxc_vdacif_init); +module_exit(mxc_vdacif_exit); + +MODULE_AUTHOR("Toradex AG"); +MODULE_DESCRIPTION("i.MX ipuv3 VDAC extern port driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index 0264704a52be..45d031233253 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c @@ -574,8 +574,9 @@ static int sh_mobile_lcdc_display_notify(struct sh_mobile_lcdc_chan *ch, switch (event) { case SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT: /* HDMI plug in */ + console_lock(); if (lock_fb_info(info)) { - console_lock(); + ch->display.width = monspec->max_x * 10; ch->display.height = monspec->max_y * 10; @@ -594,19 +595,20 @@ static int sh_mobile_lcdc_display_notify(struct sh_mobile_lcdc_chan *ch, fb_set_suspend(info, 0); } - console_unlock(); + unlock_fb_info(info); } + console_unlock(); break; case SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT: /* HDMI disconnect */ + console_lock(); if (lock_fb_info(info)) { - console_lock(); fb_set_suspend(info, 1); - console_unlock(); unlock_fb_info(info); } + console_unlock(); break; case SH_MOBILE_LCDC_EVENT_DISPLAY_MODE: diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h new file mode 100644 index 000000000000..042e7b3b6296 --- /dev/null +++ b/include/dt-bindings/input/input.h @@ -0,0 +1,525 @@ +/* + * This header provides constants for most input bindings. + * + * Most input bindings include key code, matrix key code format. + * In most cases, key code and matrix key code format uses + * the standard values/macro defined in this header. + */ + +#ifndef _DT_BINDINGS_INPUT_INPUT_H +#define _DT_BINDINGS_INPUT_INPUT_H + +#define KEY_RESERVED 0 +#define KEY_ESC 1 +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_0 11 +#define KEY_MINUS 12 +#define KEY_EQUAL 13 +#define KEY_BACKSPACE 14 +#define KEY_TAB 15 +#define KEY_Q 16 +#define KEY_W 17 +#define KEY_E 18 +#define KEY_R 19 +#define KEY_T 20 +#define KEY_Y 21 +#define KEY_U 22 +#define KEY_I 23 +#define KEY_O 24 +#define KEY_P 25 +#define KEY_LEFTBRACE 26 +#define KEY_RIGHTBRACE 27 +#define KEY_ENTER 28 +#define KEY_LEFTCTRL 29 +#define KEY_A 30 +#define KEY_S 31 +#define KEY_D 32 +#define KEY_F 33 +#define KEY_G 34 +#define KEY_H 35 +#define KEY_J 36 +#define KEY_K 37 +#define KEY_L 38 +#define KEY_SEMICOLON 39 +#define KEY_APOSTROPHE 40 +#define KEY_GRAVE 41 +#define KEY_LEFTSHIFT 42 +#define KEY_BACKSLASH 43 +#define KEY_Z 44 +#define KEY_X 45 +#define KEY_C 46 +#define KEY_V 47 +#define KEY_B 48 +#define KEY_N 49 +#define KEY_M 50 +#define KEY_COMMA 51 +#define KEY_DOT 52 +#define KEY_SLASH 53 +#define KEY_RIGHTSHIFT 54 +#define KEY_KPASTERISK 55 +#define KEY_LEFTALT 56 +#define KEY_SPACE 57 +#define KEY_CAPSLOCK 58 +#define KEY_F1 59 +#define KEY_F2 60 +#define KEY_F3 61 +#define KEY_F4 62 +#define KEY_F5 63 +#define KEY_F6 64 +#define KEY_F7 65 +#define KEY_F8 66 +#define KEY_F9 67 +#define KEY_F10 68 +#define KEY_NUMLOCK 69 +#define KEY_SCROLLLOCK 70 +#define KEY_KP7 71 +#define KEY_KP8 72 +#define KEY_KP9 73 +#define KEY_KPMINUS 74 +#define KEY_KP4 75 +#define KEY_KP5 76 +#define KEY_KP6 77 +#define KEY_KPPLUS 78 +#define KEY_KP1 79 +#define KEY_KP2 80 +#define KEY_KP3 81 +#define KEY_KP0 82 +#define KEY_KPDOT 83 + +#define KEY_ZENKAKUHANKAKU 85 +#define KEY_102ND 86 +#define KEY_F11 87 +#define KEY_F12 88 +#define KEY_RO 89 +#define KEY_KATAKANA 90 +#define KEY_HIRAGANA 91 +#define KEY_HENKAN 92 +#define KEY_KATAKANAHIRAGANA 93 +#define KEY_MUHENKAN 94 +#define KEY_KPJPCOMMA 95 +#define KEY_KPENTER 96 +#define KEY_RIGHTCTRL 97 +#define KEY_KPSLASH 98 +#define KEY_SYSRQ 99 +#define KEY_RIGHTALT 100 +#define KEY_LINEFEED 101 +#define KEY_HOME 102 +#define KEY_UP 103 +#define KEY_PAGEUP 104 +#define KEY_LEFT 105 +#define KEY_RIGHT 106 +#define KEY_END 107 +#define KEY_DOWN 108 +#define KEY_PAGEDOWN 109 +#define KEY_INSERT 110 +#define KEY_DELETE 111 +#define KEY_MACRO 112 +#define KEY_MUTE 113 +#define KEY_VOLUMEDOWN 114 +#define KEY_VOLUMEUP 115 +#define KEY_POWER 116 /* SC System Power Down */ +#define KEY_KPEQUAL 117 +#define KEY_KPPLUSMINUS 118 +#define KEY_PAUSE 119 +#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ + +#define KEY_KPCOMMA 121 +#define KEY_HANGEUL 122 +#define KEY_HANGUEL KEY_HANGEUL +#define KEY_HANJA 123 +#define KEY_YEN 124 +#define KEY_LEFTMETA 125 +#define KEY_RIGHTMETA 126 +#define KEY_COMPOSE 127 + +#define KEY_STOP 128 /* AC Stop */ +#define KEY_AGAIN 129 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ +#define KEY_FRONT 132 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ +#define KEY_SETUP 141 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ +#define KEY_SENDFILE 145 +#define KEY_DELETEFILE 146 +#define KEY_XFER 147 +#define KEY_PROG1 148 +#define KEY_PROG2 149 +#define KEY_WWW 150 /* AL Internet Browser */ +#define KEY_MSDOS 151 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE +#define KEY_DIRECTION 153 +#define KEY_CYCLEWINDOWS 154 +#define KEY_MAIL 155 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ +#define KEY_COMPUTER 157 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ +#define KEY_CLOSECD 160 +#define KEY_EJECTCD 161 +#define KEY_EJECTCLOSECD 162 +#define KEY_NEXTSONG 163 +#define KEY_PLAYPAUSE 164 +#define KEY_PREVIOUSSONG 165 +#define KEY_STOPCD 166 +#define KEY_RECORD 167 +#define KEY_REWIND 168 +#define KEY_PHONE 169 /* Media Select Telephone */ +#define KEY_ISO 170 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ +#define KEY_MOVE 175 +#define KEY_EDIT 176 +#define KEY_SCROLLUP 177 +#define KEY_SCROLLDOWN 178 +#define KEY_KPLEFTPAREN 179 +#define KEY_KPRIGHTPAREN 180 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ + +#define KEY_F13 183 +#define KEY_F14 184 +#define KEY_F15 185 +#define KEY_F16 186 +#define KEY_F17 187 +#define KEY_F18 188 +#define KEY_F19 189 +#define KEY_F20 190 +#define KEY_F21 191 +#define KEY_F22 192 +#define KEY_F23 193 +#define KEY_F24 194 + +#define KEY_PLAYCD 200 +#define KEY_PAUSECD 201 +#define KEY_PROG3 202 +#define KEY_PROG4 203 +#define KEY_DASHBOARD 204 /* AL Dashboard */ +#define KEY_SUSPEND 205 +#define KEY_CLOSE 206 /* AC Close */ +#define KEY_PLAY 207 +#define KEY_FASTFORWARD 208 +#define KEY_BASSBOOST 209 +#define KEY_PRINT 210 /* AC Print */ +#define KEY_HP 211 +#define KEY_CAMERA 212 +#define KEY_SOUND 213 +#define KEY_QUESTION 214 +#define KEY_EMAIL 215 +#define KEY_CHAT 216 +#define KEY_SEARCH 217 +#define KEY_CONNECT 218 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ +#define KEY_SPORT 220 +#define KEY_SHOP 221 +#define KEY_ALTERASE 222 +#define KEY_CANCEL 223 /* AC Cancel */ +#define KEY_BRIGHTNESSDOWN 224 +#define KEY_BRIGHTNESSUP 225 +#define KEY_MEDIA 226 + +#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video + outputs (Monitor/LCD/TV-out/etc) */ +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ +#define KEY_DOCUMENTS 235 + +#define KEY_BATTERY 236 + +#define KEY_BLUETOOTH 237 +#define KEY_WLAN 238 +#define KEY_UWB 239 + +#define KEY_UNKNOWN 240 + +#define KEY_VIDEO_NEXT 241 /* drive next video source */ +#define KEY_VIDEO_PREV 242 /* drive previous video source */ +#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ +#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */ +#define KEY_DISPLAY_OFF 245 /* display device to off state */ + +#define KEY_WIMAX 246 +#define KEY_RFKILL 247 /* Key that controls all radios */ + +#define KEY_MICMUTE 248 /* Mute / unmute the microphone */ + +/* Code 255 is reserved for special needs of AT keyboard driver */ + +#define BTN_MISC 0x100 +#define BTN_0 0x100 +#define BTN_1 0x101 +#define BTN_2 0x102 +#define BTN_3 0x103 +#define BTN_4 0x104 +#define BTN_5 0x105 +#define BTN_6 0x106 +#define BTN_7 0x107 +#define BTN_8 0x108 +#define BTN_9 0x109 + +#define BTN_MOUSE 0x110 +#define BTN_LEFT 0x110 +#define BTN_RIGHT 0x111 +#define BTN_MIDDLE 0x112 +#define BTN_SIDE 0x113 +#define BTN_EXTRA 0x114 +#define BTN_FORWARD 0x115 +#define BTN_BACK 0x116 +#define BTN_TASK 0x117 + +#define BTN_JOYSTICK 0x120 +#define BTN_TRIGGER 0x120 +#define BTN_THUMB 0x121 +#define BTN_THUMB2 0x122 +#define BTN_TOP 0x123 +#define BTN_TOP2 0x124 +#define BTN_PINKIE 0x125 +#define BTN_BASE 0x126 +#define BTN_BASE2 0x127 +#define BTN_BASE3 0x128 +#define BTN_BASE4 0x129 +#define BTN_BASE5 0x12a +#define BTN_BASE6 0x12b +#define BTN_DEAD 0x12f + +#define BTN_GAMEPAD 0x130 +#define BTN_SOUTH 0x130 +#define BTN_A BTN_SOUTH +#define BTN_EAST 0x131 +#define BTN_B BTN_EAST +#define BTN_C 0x132 +#define BTN_NORTH 0x133 +#define BTN_X BTN_NORTH +#define BTN_WEST 0x134 +#define BTN_Y BTN_WEST +#define BTN_Z 0x135 +#define BTN_TL 0x136 +#define BTN_TR 0x137 +#define BTN_TL2 0x138 +#define BTN_TR2 0x139 +#define BTN_SELECT 0x13a +#define BTN_START 0x13b +#define BTN_MODE 0x13c +#define BTN_THUMBL 0x13d +#define BTN_THUMBR 0x13e + +#define BTN_DIGI 0x140 +#define BTN_TOOL_PEN 0x140 +#define BTN_TOOL_RUBBER 0x141 +#define BTN_TOOL_BRUSH 0x142 +#define BTN_TOOL_PENCIL 0x143 +#define BTN_TOOL_AIRBRUSH 0x144 +#define BTN_TOOL_FINGER 0x145 +#define BTN_TOOL_MOUSE 0x146 +#define BTN_TOOL_LENS 0x147 +#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_TOUCH 0x14a +#define BTN_STYLUS 0x14b +#define BTN_STYLUS2 0x14c +#define BTN_TOOL_DOUBLETAP 0x14d +#define BTN_TOOL_TRIPLETAP 0x14e +#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ + +#define BTN_WHEEL 0x150 +#define BTN_GEAR_DOWN 0x150 +#define BTN_GEAR_UP 0x151 + +#define KEY_OK 0x160 +#define KEY_SELECT 0x161 +#define KEY_GOTO 0x162 +#define KEY_CLEAR 0x163 +#define KEY_POWER2 0x164 +#define KEY_OPTION 0x165 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ +#define KEY_TIME 0x167 +#define KEY_VENDOR 0x168 +#define KEY_ARCHIVE 0x169 +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ +#define KEY_CHANNEL 0x16b +#define KEY_FAVORITES 0x16c +#define KEY_EPG 0x16d +#define KEY_PVR 0x16e /* Media Select Home */ +#define KEY_MHP 0x16f +#define KEY_LANGUAGE 0x170 +#define KEY_TITLE 0x171 +#define KEY_SUBTITLE 0x172 +#define KEY_ANGLE 0x173 +#define KEY_ZOOM 0x174 +#define KEY_MODE 0x175 +#define KEY_KEYBOARD 0x176 +#define KEY_SCREEN 0x177 +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ +#define KEY_SAT2 0x17e +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ +#define KEY_RADIO 0x181 +#define KEY_TUNER 0x182 /* Media Select Tuner */ +#define KEY_PLAYER 0x183 +#define KEY_TEXT 0x184 +#define KEY_DVD 0x185 /* Media Select DVD */ +#define KEY_AUX 0x186 +#define KEY_MP3 0x187 +#define KEY_AUDIO 0x188 /* AL Audio Browser */ +#define KEY_VIDEO 0x189 /* AL Movie Browser */ +#define KEY_DIRECTORY 0x18a +#define KEY_LIST 0x18b +#define KEY_MEMO 0x18c /* Media Select Messages */ +#define KEY_CALENDAR 0x18d +#define KEY_RED 0x18e +#define KEY_GREEN 0x18f +#define KEY_YELLOW 0x190 +#define KEY_BLUE 0x191 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ +#define KEY_FIRST 0x194 +#define KEY_LAST 0x195 /* Recall Last */ +#define KEY_AB 0x196 +#define KEY_NEXT 0x197 +#define KEY_RESTART 0x198 +#define KEY_SLOW 0x199 +#define KEY_SHUFFLE 0x19a +#define KEY_BREAK 0x19b +#define KEY_PREVIOUS 0x19c +#define KEY_DIGITS 0x19d +#define KEY_TEEN 0x19e +#define KEY_TWEN 0x19f +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ +#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ +#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ +#define KEY_LOGOFF 0x1b1 /* AL Logoff */ + +#define KEY_DOLLAR 0x1b2 +#define KEY_EURO 0x1b3 + +#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ +#define KEY_FRAMEFORWARD 0x1b5 +#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ +#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ +#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ +#define KEY_IMAGES 0x1ba /* AL Image Browser */ + +#define KEY_DEL_EOL 0x1c0 +#define KEY_DEL_EOS 0x1c1 +#define KEY_INS_LINE 0x1c2 +#define KEY_DEL_LINE 0x1c3 + +#define KEY_FN 0x1d0 +#define KEY_FN_ESC 0x1d1 +#define KEY_FN_F1 0x1d2 +#define KEY_FN_F2 0x1d3 +#define KEY_FN_F3 0x1d4 +#define KEY_FN_F4 0x1d5 +#define KEY_FN_F5 0x1d6 +#define KEY_FN_F6 0x1d7 +#define KEY_FN_F7 0x1d8 +#define KEY_FN_F8 0x1d9 +#define KEY_FN_F9 0x1da +#define KEY_FN_F10 0x1db +#define KEY_FN_F11 0x1dc +#define KEY_FN_F12 0x1dd +#define KEY_FN_1 0x1de +#define KEY_FN_2 0x1df +#define KEY_FN_D 0x1e0 +#define KEY_FN_E 0x1e1 +#define KEY_FN_F 0x1e2 +#define KEY_FN_S 0x1e3 +#define KEY_FN_B 0x1e4 + +#define KEY_BRL_DOT1 0x1f1 +#define KEY_BRL_DOT2 0x1f2 +#define KEY_BRL_DOT3 0x1f3 +#define KEY_BRL_DOT4 0x1f4 +#define KEY_BRL_DOT5 0x1f5 +#define KEY_BRL_DOT6 0x1f6 +#define KEY_BRL_DOT7 0x1f7 +#define KEY_BRL_DOT8 0x1f8 +#define KEY_BRL_DOT9 0x1f9 +#define KEY_BRL_DOT10 0x1fa + +#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ +#define KEY_NUMERIC_1 0x201 /* and other keypads */ +#define KEY_NUMERIC_2 0x202 +#define KEY_NUMERIC_3 0x203 +#define KEY_NUMERIC_4 0x204 +#define KEY_NUMERIC_5 0x205 +#define KEY_NUMERIC_6 0x206 +#define KEY_NUMERIC_7 0x207 +#define KEY_NUMERIC_8 0x208 +#define KEY_NUMERIC_9 0x209 +#define KEY_NUMERIC_STAR 0x20a +#define KEY_NUMERIC_POUND 0x20b + +#define KEY_CAMERA_FOCUS 0x210 +#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ + +#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ +#define KEY_TOUCHPAD_ON 0x213 +#define KEY_TOUCHPAD_OFF 0x214 + +#define KEY_CAMERA_ZOOMIN 0x215 +#define KEY_CAMERA_ZOOMOUT 0x216 +#define KEY_CAMERA_UP 0x217 +#define KEY_CAMERA_DOWN 0x218 +#define KEY_CAMERA_LEFT 0x219 +#define KEY_CAMERA_RIGHT 0x21a + +#define KEY_ATTENDANT_ON 0x21b +#define KEY_ATTENDANT_OFF 0x21c +#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ +#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ + +#define BTN_DPAD_UP 0x220 +#define BTN_DPAD_DOWN 0x221 +#define BTN_DPAD_LEFT 0x222 +#define BTN_DPAD_RIGHT 0x223 + +#define MATRIX_KEY(row, col, code) \ + ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) + +#endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/include/linux/input/fusion_F0710A.h b/include/linux/input/fusion_F0710A.h new file mode 100644 index 000000000000..7d152cbdd06e --- /dev/null +++ b/include/linux/input/fusion_F0710A.h @@ -0,0 +1,20 @@ +/* linux/input/fusion_F0710A.h + * + * Platform data for Fusion F0710A driver + * + * Copyright (c) 2013 Toradex AG (stefan.agner@toradex.ch) + * + * For licencing details see kernel-base/COPYING + */ + +#ifndef __LINUX_I2C_FUSION_F0710A_H +#define __LINUX_I2C_FUSION_F0710A_H + +/* Board specific touch screen initial values */ +struct fusion_f0710a_init_data { + int (*pinmux_fusion_pins)(void); + int gpio_int; + int gpio_reset; +}; + +#endif /* __LINUX_I2C_FUSION_F0710A_H */ diff --git a/include/linux/ipu-v3.h b/include/linux/ipu-v3.h index c57d7ded4f6a..1145c79030da 100644 --- a/include/linux/ipu-v3.h +++ b/include/linux/ipu-v3.h @@ -127,15 +127,18 @@ typedef enum { XY } display_addressing_t; +struct mipi_fields { + uint32_t id; + uint32_t vc; + bool en; +}; /*! * Union of initialization parameters for a logical channel. */ typedef union { struct { uint32_t csi; - uint32_t mipi_id; - uint32_t mipi_vc; - bool mipi_en; + struct mipi_fields mipi; bool interlaced; } csi_mem; struct { @@ -148,9 +151,7 @@ typedef union { uint32_t outh_resize_ratio; uint32_t outv_resize_ratio; uint32_t csi; - uint32_t mipi_id; - uint32_t mipi_vc; - bool mipi_en; + struct mipi_fields mipi; } csi_prp_enc_mem; struct { uint32_t in_width; @@ -189,9 +190,7 @@ typedef union { ipu_motion_sel motion_sel; enum v4l2_field field_fmt; uint32_t csi; - uint32_t mipi_id; - uint32_t mipi_vc; - bool mipi_en; + struct mipi_fields mipi; } csi_prp_vf_mem; struct { uint32_t in_width; @@ -587,6 +586,12 @@ struct ipu_soc; struct ipu_soc *ipu_get_soc(int id); int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params); void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel); + +struct ipu_chan; +int32_t ipu_channel_request(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params, struct ipu_chan **p_ipu_chan); +void ipu_channel_free(struct ipu_chan **p_ipu_chan); +int32_t ipu_channel_disable(struct ipu_chan *ipu_chan, bool wait_for_stop); + void ipu_disable_hsp_clk(struct ipu_soc *ipu); static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index 48395a69a7e9..76195ccee98c 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -12,6 +12,17 @@ struct device; +#define SAMPLE_TIME(x) ((x & 0xf) << 4) +#define MOD_12B(x) ((x & 0x1) << 3) +#define REF_SEL(x) ((x & 0x1) << 1) +#define ADC_FREQ(x) (x & 0x3) +#define AVE_CTRL(x) ((x & 0x3) << 6) +#define DET_DELAY(x) ((x & 0x7) << 3) +#define SETTLING(x) (x & 0x7) +#define FRACTION_Z(x) (x & 0x7) +#define I_DRIVE(x) (x & 0x1) +#define OP_MODE(x) ((x & 0x7) << 1) + enum stmpe_block { STMPE_BLOCK_GPIO = 1 << 0, STMPE_BLOCK_KEYPAD = 1 << 1, @@ -189,6 +200,26 @@ struct stmpe_ts_platform_data { }; /** + * struct stmpe_adc_platform_data - stmpe811 adc controller platform + * data + * @sample_time: ADC converstion time in number of clock. + * (0 -> 36 clocks, 1 -> 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, + * 4 -> 80 clocks, 5 -> 96 clocks, 6 -> 144 clocks), + * recommended is 4. + * @mod_12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) + * @ref_sel: ADC reference source + * (0 -> internal reference, 1 -> external reference) + * @adc_freq: ADC Clock speed + * (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) + */ +struct stmpe_adc_platform_data { + u8 sample_time; + u8 mod_12b; + u8 ref_sel; + u8 adc_freq; +}; + +/** * struct stmpe_platform_data - STMPE platform data * @id: device id to distinguish between multiple STMPEs on the same board * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) @@ -217,6 +248,7 @@ struct stmpe_platform_data { struct stmpe_gpio_platform_data *gpio; struct stmpe_keypad_platform_data *keypad; struct stmpe_ts_platform_data *ts; + struct stmpe_adc_platform_data *adc; }; #define STMPE_NR_INTERNAL_IRQS 9 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index e326ae2882a0..bc45257f76c6 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -328,6 +328,7 @@ struct mmc_host { struct task_struct *claimer; /* task that has host claimed */ int claim_cnt; /* "claim" nesting count */ + struct workqueue_struct *workqueue; struct delayed_work detect; int detect_change; /* card detect flag */ struct mmc_slot slot; diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index 2e3a1c941eee..2e15fb18450a 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -97,6 +97,7 @@ struct sdhci_host { #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) #define SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER (1<<5) +#define SDHCI_QUIRK2_VQMMC_1_8_V (1<<6) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ diff --git a/include/linux/platform_data/mmc-esdhc-imx.h b/include/linux/platform_data/mmc-esdhc-imx.h index e1571efa3f2b..8a2707007209 100644 --- a/include/linux/platform_data/mmc-esdhc-imx.h +++ b/include/linux/platform_data/mmc-esdhc-imx.h @@ -44,6 +44,7 @@ struct esdhc_platform_data { enum cd_types cd_type; int max_bus_width; bool support_vsel; + bool vqmmc_18v; unsigned int delay_line; }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/include/linux/rfkill-gpio.h b/include/linux/rfkill-gpio.h index 4d09f6eab359..76a9674af5db 100644 --- a/include/linux/rfkill-gpio.h +++ b/include/linux/rfkill-gpio.h @@ -35,7 +35,7 @@ */ struct rfkill_gpio_platform_data { - char *name; + const char *name; int reset_gpio; int shutdown_gpio; const char *power_clk_name; diff --git a/include/linux/rfkill-regulator.h b/include/linux/rfkill-regulator.h index aca36bc83315..d489c289265a 100644 --- a/include/linux/rfkill-regulator.h +++ b/include/linux/rfkill-regulator.h @@ -41,7 +41,7 @@ #include <linux/rfkill.h> struct rfkill_regulator_platform_data { - char *name; /* the name for the rfkill switch */ + const char *name; /* the name for the rfkill switch */ enum rfkill_type type; /* the type as specified in rfkill.h */ }; diff --git a/include/linux/sync.h b/include/linux/sync.h new file mode 100644 index 000000000000..4f1993871467 --- /dev/null +++ b/include/linux/sync.h @@ -0,0 +1,390 @@ +/* + * include/linux/sync.h + * + * Copyright (C) 2012 Google, Inc. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_SYNC_H +#define _LINUX_SYNC_H + +#include <linux/types.h> +#ifdef __KERNEL__ + +#include <linux/ktime.h> +#include <linux/list.h> +#include <linux/spinlock.h> +#include <linux/wait.h> + +struct sync_timeline; +struct sync_pt; +struct sync_fence; + +/** + * struct sync_timeline_ops - sync object implementation ops + * @driver_name: name of the implentation + * @dup: duplicate a sync_pt + * @has_signaled: returns: + * 1 if pt has signaled + * 0 if pt has not signaled + * <0 on error + * @compare: returns: + * 1 if b will signal before a + * 0 if a and b will signal at the same time + * -1 if a will signabl before b + * @free_pt: called before sync_pt is freed + * @release_obj: called before sync_timeline is freed + * @print_obj: print aditional debug information about sync_timeline. + * should not print a newline + * @print_pt: print aditional debug information about sync_pt. + * should not print a newline + * @fill_driver_data: write implmentation specific driver data to data. + * should return an error if there is not enough room + * as specified by size. This information is returned + * to userspace by SYNC_IOC_FENCE_INFO. + */ +struct sync_timeline_ops { + const char *driver_name; + + /* required */ + struct sync_pt *(*dup)(struct sync_pt *pt); + + /* required */ + int (*has_signaled)(struct sync_pt *pt); + + /* required */ + int (*compare)(struct sync_pt *a, struct sync_pt *b); + + /* optional */ + void (*free_pt)(struct sync_pt *sync_pt); + + /* optional */ + void (*release_obj)(struct sync_timeline *sync_timeline); + + /* optional */ + void (*print_obj)(struct seq_file *s, + struct sync_timeline *sync_timeline); + + /* optional */ + void (*print_pt)(struct seq_file *s, struct sync_pt *sync_pt); + + /* optional */ + int (*fill_driver_data)(struct sync_pt *syncpt, void *data, int size); +}; + +/** + * struct sync_timeline - sync object + * @ops: ops that define the implementaiton of the sync_timeline + * @name: name of the sync_timeline. Useful for debugging + * @destoryed: set when sync_timeline is destroyed + * @child_list_head: list of children sync_pts for this sync_timeline + * @child_list_lock: lock protecting @child_list_head, destroyed, and + * sync_pt.status + * @active_list_head: list of active (unsignaled/errored) sync_pts + * @sync_timeline_list: membership in global sync_timeline_list + */ +struct sync_timeline { + const struct sync_timeline_ops *ops; + char name[32]; + + /* protected by child_list_lock */ + bool destroyed; + + struct list_head child_list_head; + spinlock_t child_list_lock; + + struct list_head active_list_head; + spinlock_t active_list_lock; + + struct list_head sync_timeline_list; +}; + +/** + * struct sync_pt - sync point + * @parent: sync_timeline to which this sync_pt belongs + * @child_list: membership in sync_timeline.child_list_head + * @active_list: membership in sync_timeline.active_list_head + * @fence: sync_fence to which the sync_pt belongs + * @pt_list: membership in sync_fence.pt_list_head + * @status: 1: signaled, 0:active, <0: error + * @timestamp: time which sync_pt status transitioned from active to + * singaled or error. + */ +struct sync_pt { + struct sync_timeline *parent; + struct list_head child_list; + + struct list_head active_list; + + struct sync_fence *fence; + struct list_head pt_list; + + /* protected by parent->active_list_lock */ + int status; + + ktime_t timestamp; +}; + +/** + * struct sync_fence - sync fence + * @file: file representing this fence + * @name: name of sync_fence. Useful for debugging + * @pt_list_head: list of sync_pts in ths fence. immutable once fence + * is created + * @waiter_list_head: list of asynchronous waiters on this fence + * @waiter_list_lock: lock protecting @waiter_list_head and @status + * @status: 1: signaled, 0:active, <0: error + * + * @wq: wait queue for fence signaling + * @sync_fence_list: membership in global fence list + */ +struct sync_fence { + struct file *file; + char name[32]; + + /* this list is immutable once the fence is created */ + struct list_head pt_list_head; + + struct list_head waiter_list_head; + spinlock_t waiter_list_lock; /* also protects status */ + int status; + + wait_queue_head_t wq; + + struct list_head sync_fence_list; +}; + +/** + * struct sync_fence_waiter - metadata for asynchronous waiter on a fence + * @waiter_list: membership in sync_fence.waiter_list_head + * @callback: function pointer to call when fence signals + * @callback_data: pointer to pass to @callback + */ +struct sync_fence_waiter { + struct list_head waiter_list; + + void (*callback)(struct sync_fence *fence, void *data); + void *callback_data; +}; + +/* + * API for sync_timeline implementers + */ + +/** + * sync_timeline_create() - creates a sync object + * @ops: specifies the implemention ops for the object + * @size: size to allocate for this obj + * @name: sync_timeline name + * + * Creates a new sync_timeline which will use the implemetation specified by + * @ops. @size bytes will be allocated allowing for implemntation specific + * data to be kept after the generic sync_timeline stuct. + */ +struct sync_timeline *sync_timeline_create(const struct sync_timeline_ops *ops, + int size, const char *name); + +/** + * sync_timeline_destory() - destorys a sync object + * @obj: sync_timeline to destroy + * + * A sync implemntation should call this when the @obj is going away + * (i.e. module unload.) @obj won't actually be freed until all its childern + * sync_pts are freed. + */ +void sync_timeline_destroy(struct sync_timeline *obj); + +/** + * sync_timeline_signal() - signal a status change on a sync_timeline + * @obj: sync_timeline to signal + * + * A sync implemntation should call this any time one of it's sync_pts + * has signaled or has an error condition. + */ +void sync_timeline_signal(struct sync_timeline *obj); + +/** + * sync_pt_create() - creates a sync pt + * @parent: sync_pt's parent sync_timeline + * @size: size to allocate for this pt + * + * Creates a new sync_pt as a chiled of @parent. @size bytes will be + * allocated allowing for implemntation specific data to be kept after + * the generic sync_timeline struct. + */ +struct sync_pt *sync_pt_create(struct sync_timeline *parent, int size); + +/** + * sync_pt_free() - frees a sync pt + * @pt: sync_pt to free + * + * This should only be called on sync_pts which have been created but + * not added to a fence. + */ +void sync_pt_free(struct sync_pt *pt); + +/** + * sync_fence_create() - creates a sync fence + * @name: name of fence to create + * @pt: sync_pt to add to the fence + * + * Creates a fence containg @pt. Once this is called, the fence takes + * ownership of @pt. + */ +struct sync_fence *sync_fence_create(const char *name, struct sync_pt *pt); + +/* + * API for sync_fence consumers + */ + +/** + * sync_fence_merge() - merge two fences + * @name: name of new fence + * @a: fence a + * @b: fence b + * + * Creates a new fence which contains copies of all the sync_pts in both + * @a and @b. @a and @b remain valid, independent fences. + */ +struct sync_fence *sync_fence_merge(const char *name, + struct sync_fence *a, struct sync_fence *b); + +/** + * sync_fence_fdget() - get a fence from an fd + * @fd: fd referencing a fence + * + * Ensures @fd references a valid fence, increments the refcount of the backing + * file, and returns the fence. + */ +struct sync_fence *sync_fence_fdget(int fd); + +/** + * sync_fence_put() - puts a refernnce of a sync fence + * @fence: fence to put + * + * Puts a reference on @fence. If this is the last reference, the fence and + * all it's sync_pts will be freed + */ +void sync_fence_put(struct sync_fence *fence); + +/** + * sync_fence_install() - installs a fence into a file descriptor + * @fence: fence to instal + * @fd: file descriptor in which to install the fence + * + * Installs @fence into @fd. @fd's should be acquired through get_unused_fd(). + */ +void sync_fence_install(struct sync_fence *fence, int fd); + +/** + * sync_fence_wait_async() - registers and async wait on the fence + * @fence: fence to wait on + * @callback: callback + * @callback_data data to pass to the callback + * + * Returns 1 if @fence has already signaled. + * + * Registers a callback to be called when @fence signals or has an error + */ +int sync_fence_wait_async(struct sync_fence *fence, + void (*callback)(struct sync_fence *, void *data), + void *callback_data); + +/** + * sync_fence_wait() - wait on fence + * @fence: fence to wait on + * @tiemout: timeout in ms + * + * Wait for @fence to be signaled or have an error. Waits indefintly + * if @timeout = 0 + */ +int sync_fence_wait(struct sync_fence *fence, long timeout); + +#endif /* __KERNEL__ */ + +/** + * struct sync_merge_data - data passed to merge ioctl + * @fd2: file descriptor of second fence + * @name: name of new fence + * @fence: returns the fd of the new fence to userspace + */ +struct sync_merge_data { + __s32 fd2; /* fd of second fence */ + char name[32]; /* name of new fence */ + __s32 fence; /* fd on newly created fence */ +}; + +/** + * struct sync_pt_info - detailed sync_pt information + * @len: length of sync_pt_info including any driver_data + * @obj_name: name of parent sync_timeline + * @driver_name: name of driver implmenting the parent + * @status: status of the sync_pt 0:active 1:signaled <0:error + * @timestamp_ns: timestamp of status change in nanoseconds + * @driver_data: any driver dependant data + */ +struct sync_pt_info { + __u32 len; + char obj_name[32]; + char driver_name[32]; + __s32 status; + __u64 timestamp_ns; + + __u8 driver_data[0]; +}; + +/** + * struct sync_fence_info_data - data returned from fence info ioctl + * @len: ioctl caller writes the size of the buffer its passing in. + * ioctl returns length of sync_fence_data reutnred to userspace + * including pt_info. + * @name: name of fence + * @status: status of fence. 1: signaled 0:active <0:error + * @pt_info: a sync_pt_info struct for every sync_pt in the fence + */ +struct sync_fence_info_data { + __u32 len; + char name[32]; + __s32 status; + + __u8 pt_info[0]; +}; + +#define SYNC_IOC_MAGIC '>' + +/** + * DOC: SYNC_IOC_WAIT - wait for a fence to signal + * + * pass timeout in milliseconds. + */ +#define SYNC_IOC_WAIT _IOW(SYNC_IOC_MAGIC, 0, __u32) + +/** + * DOC: SYNC_IOC_MERGE - merge two fences + * + * Takes a struct sync_merge_data. Creates a new fence containing copies of + * the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the + * new fence's fd in sync_merge_data.fence + */ +#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 1, struct sync_merge_data) + +/** + * DOC: SYNC_IOC_FENCE_INFO - get detailed information on a fence + * + * Takes a struct sync_fence_info_data with extra space allocated for pt_info. + * Caller should write the size of the buffer into len. On return, len is + * updated to reflect the total size of the sync_fence_info_data including + * pt_info. + * + * pt_info is a buffer containing sync_pt_infos for every sync_pt in the fence. + * To itterate over the sync_pt_infos, use the sync_pt_info.len field. + */ +#define SYNC_IOC_FENCE_INFO _IOWR(SYNC_IOC_MAGIC, 2,\ + struct sync_fence_info_data) + +#endif /* _LINUX_SYNC_H */ diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h index e6aa2318367b..8d18a5d55866 100644 --- a/include/media/v4l2-int-device.h +++ b/include/media/v4l2-int-device.h @@ -187,6 +187,7 @@ enum v4l2_int_ioctl_num { vidioc_int_querystd_num, vidioc_int_s_std_num, vidioc_int_s_video_routing_num, + vidioc_int_send_command_num, /* * @@ -291,6 +292,7 @@ V4L2_INT_WRAPPER_1(s_parm, struct v4l2_streamparm, *); V4L2_INT_WRAPPER_1(querystd, v4l2_std_id, *); V4L2_INT_WRAPPER_1(s_std, v4l2_std_id, *); V4L2_INT_WRAPPER_1(s_video_routing, struct v4l2_routing, *); +V4L2_INT_WRAPPER_1(send_command, struct v4l2_send_command_control, *); V4L2_INT_WRAPPER_0(dev_init); V4L2_INT_WRAPPER_0(dev_exit); diff --git a/include/uapi/linux/mxc_v4l2.h b/include/uapi/linux/mxc_v4l2.h index 49345fea15ec..248d67643042 100644 --- a/include/uapi/linux/mxc_v4l2.h +++ b/include/uapi/linux/mxc_v4l2.h @@ -48,6 +48,11 @@ #define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6 #define V4L2_MXC_ROTATE_90_LEFT 7 +#define V4L2_MXC_CAM_ROTATE_NONE 8 +#define V4L2_MXC_CAM_ROTATE_VERT_FLIP 9 +#define V4L2_MXC_CAM_ROTATE_HORIZ_FLIP 10 +#define V4L2_MXC_CAM_ROTATE_180 11 + struct v4l2_mxc_offset { uint32_t u_offset; uint32_t v_offset; diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index 69bd5bb0d5af..aabd2413d68e 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -630,6 +630,14 @@ enum v4l2_exposure_auto_type { #define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19) #define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20) + +/* Backported from Samsung Kernel */ +#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28) +#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29) +#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30) +#define V4L2_CID_SEND_COMMAND (V4L2_CID_CAMERA_CLASS_BASE+34) + + enum v4l2_auto_n_preset_white_balance { V4L2_WHITE_BALANCE_MANUAL = 0, V4L2_WHITE_BALANCE_AUTO = 1, diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index f40b41c7e108..8e590e11ee95 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1227,6 +1227,13 @@ struct v4l2_ext_controls { struct v4l2_ext_control *controls; }; +struct v4l2_send_command_control { + __u32 id; + __u32 value0; + __u32 value1; + char debug[256]; +}; + #define V4L2_CTRL_ID_MASK (0x0fffffff) #define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL) #define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000) @@ -1957,6 +1964,8 @@ struct v4l2_create_buffers { Never use these in applications! */ #define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info) +#define VIDIOC_SEND_COMMAND _IOWR('V', 103, struct v4l2_send_command_control) + /* Reminder: when adding new ioctls please add support for them to drivers/media/video/v4l2-compat-ioctl32.c as well! */ diff --git a/include/video/mxc_hdmi.h b/include/video/mxc_hdmi.h index e63fde7438f1..dbd0f94f3d2c 100644 --- a/include/video/mxc_hdmi.h +++ b/include/video/mxc_hdmi.h @@ -580,6 +580,10 @@ enum { HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2, HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1, +/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/ + HDMI_DVI_IH_STAT = 0x3D, + + /* IH_AHBDMAAUD_STAT0 field values */ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, @@ -875,6 +879,9 @@ enum { HDMI_PHY_HPD = 0x02, HDMI_PHY_TX_PHY_LOCK = 0x01, +/* HDMI STAT convenience RX_SENSE | HPD */ + HDMI_DVI_STAT = 0xF2, + /* PHY_I2CM_SLAVE_ADDR field values */ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, diff --git a/mm/mmap.c b/mm/mmap.c index 8d25fdc653be..8f87b14c7968 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -1853,7 +1853,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, struct vm_area_struct *vma; struct vm_unmapped_area_info info; - if (len > TASK_SIZE) + if (len > TASK_SIZE - mmap_min_addr) return -ENOMEM; if (flags & MAP_FIXED) @@ -1862,7 +1862,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, if (addr) { addr = PAGE_ALIGN(addr); vma = find_vma(mm, addr); - if (TASK_SIZE - len >= addr && + if (TASK_SIZE - len >= addr && addr >= mmap_min_addr && (!vma || addr + len <= vma->vm_start)) return addr; } @@ -1901,7 +1901,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, struct vm_unmapped_area_info info; /* requested length too big for entire address space */ - if (len > TASK_SIZE) + if (len > TASK_SIZE - mmap_min_addr) return -ENOMEM; if (flags & MAP_FIXED) @@ -1911,14 +1911,14 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, if (addr) { addr = PAGE_ALIGN(addr); vma = find_vma(mm, addr); - if (TASK_SIZE - len >= addr && + if (TASK_SIZE - len >= addr && addr >= mmap_min_addr && (!vma || addr + len <= vma->vm_start)) return addr; } info.flags = VM_UNMAPPED_AREA_TOPDOWN; info.length = len; - info.low_limit = PAGE_SIZE; + info.low_limit = max(PAGE_SIZE, mmap_min_addr); info.high_limit = mm->mmap_base; info.align_mask = 0; addr = vm_unmapped_area(&info); diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c index fb076cd6f808..37a6cbe2e5b8 100644 --- a/net/rfkill/rfkill-gpio.c +++ b/net/rfkill/rfkill-gpio.c @@ -20,6 +20,8 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/of_irq.h> #include <linux/rfkill.h> #include <linux/platform_device.h> #include <linux/clk.h> @@ -39,32 +41,30 @@ enum rfkill_gpio_clk_state { #define PWR_CLK_DISABLED(_RF) ((_RF)->pwr_clk_enabled != PWR_ENABLED) struct rfkill_gpio_data { - struct rfkill_gpio_platform_data *pdata; struct rfkill *rfkill_dev; char *reset_name; char *shutdown_name; enum rfkill_gpio_clk_state pwr_clk_enabled; struct clk *pwr_clk; + int gpio_cnt; + int gpiolist[5]; }; static int rfkill_gpio_set_power(void *data, bool blocked) { struct rfkill_gpio_data *rfkill = data; + int i; if (blocked) { - if (gpio_is_valid(rfkill->pdata->shutdown_gpio)) - gpio_direction_output(rfkill->pdata->shutdown_gpio, 0); - if (gpio_is_valid(rfkill->pdata->reset_gpio)) - gpio_direction_output(rfkill->pdata->reset_gpio, 0); + for (i = rfkill->gpio_cnt - 1; i >= 0; i--) + gpio_direction_output(rfkill->gpiolist[i], 0); if (rfkill->pwr_clk && PWR_CLK_ENABLED(rfkill)) clk_disable(rfkill->pwr_clk); } else { if (rfkill->pwr_clk && PWR_CLK_DISABLED(rfkill)) clk_enable(rfkill->pwr_clk); - if (gpio_is_valid(rfkill->pdata->reset_gpio)) - gpio_direction_output(rfkill->pdata->reset_gpio, 1); - if (gpio_is_valid(rfkill->pdata->shutdown_gpio)) - gpio_direction_output(rfkill->pdata->shutdown_gpio, 1); + for (i = 0; i < rfkill->gpio_cnt; i++) + gpio_direction_output(rfkill->gpiolist[i], 1); } if (rfkill->pwr_clk) @@ -77,16 +77,46 @@ static const struct rfkill_ops rfkill_gpio_ops = { .set_block = rfkill_gpio_set_power, }; +static struct rfkill_gpio_platform_data *rfkill_gpio_get_pdata_from_of(struct device *dev) +{ + struct rfkill_gpio_platform_data *pdata; + struct device_node *np = dev->of_node; + + if (!np) { + np = of_find_matching_node(NULL, dev->driver->of_match_table); + if (!np) { + dev_notice(dev, "device tree node not available\n"); + return ERR_PTR(-ENODEV); + } + } + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(dev, "can't allocate platform data\n"); + return ERR_PTR(-ENODEV); + } + pdata->reset_gpio = of_get_named_gpio(np, "gpios", 0); + pdata->shutdown_gpio = of_get_named_gpio(np, "gpios", 1); + of_property_read_u32(np, "type", &pdata->type); + of_property_read_string(np, "name", &pdata->name); + return pdata; +} + static int rfkill_gpio_probe(struct platform_device *pdev) { struct rfkill_gpio_data *rfkill; struct rfkill_gpio_platform_data *pdata = pdev->dev.platform_data; + struct rfkill_gpio_platform_data *p = NULL; int ret = 0; int len = 0; + int gpio_cnt = 0; if (!pdata) { - pr_warn("%s: No platform data specified\n", __func__); - return -EINVAL; + p = pdata = rfkill_gpio_get_pdata_from_of(&pdev->dev); + if (IS_ERR(p)) { + dev_err(&pdev->dev, "no platform data\n"); + return PTR_ERR(p); + } } /* make sure at-least one of the GPIO is defined and that @@ -109,8 +139,6 @@ static int rfkill_gpio_probe(struct platform_device *pdev) } } - rfkill->pdata = pdata; - len = strlen(pdata->name); rfkill->reset_name = kzalloc(len + 7, GFP_KERNEL); if (!rfkill->reset_name) { @@ -142,6 +170,7 @@ static int rfkill_gpio_probe(struct platform_device *pdev) pr_warn("%s: failed to get reset gpio.\n", __func__); goto fail_clock; } + rfkill->gpiolist[gpio_cnt++] = pdata->reset_gpio; } if (gpio_is_valid(pdata->shutdown_gpio)) { @@ -150,8 +179,9 @@ static int rfkill_gpio_probe(struct platform_device *pdev) pr_warn("%s: failed to get shutdown gpio.\n", __func__); goto fail_reset; } + rfkill->gpiolist[gpio_cnt++] = pdata->shutdown_gpio; } - + rfkill->gpio_cnt = gpio_cnt; rfkill->rfkill_dev = rfkill_alloc(pdata->name, &pdev->dev, pdata->type, &rfkill_gpio_ops, rfkill); if (!rfkill->rfkill_dev) { @@ -166,7 +196,7 @@ static int rfkill_gpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rfkill); dev_info(&pdev->dev, "%s device registered.\n", pdata->name); - + kfree(p); return 0; fail_rfkill: @@ -186,7 +216,7 @@ fail_reset_name: kfree(rfkill->reset_name); fail_alloc: kfree(rfkill); - + kfree(p); return ret; } @@ -194,15 +224,14 @@ static int rfkill_gpio_remove(struct platform_device *pdev) { struct rfkill_gpio_data *rfkill = platform_get_drvdata(pdev); struct rfkill_gpio_platform_data *pdata = pdev->dev.platform_data; + int i; if (pdata->gpio_runtime_close) pdata->gpio_runtime_close(pdev); rfkill_unregister(rfkill->rfkill_dev); rfkill_destroy(rfkill->rfkill_dev); - if (gpio_is_valid(rfkill->pdata->shutdown_gpio)) - gpio_free(rfkill->pdata->shutdown_gpio); - if (gpio_is_valid(rfkill->pdata->reset_gpio)) - gpio_free(rfkill->pdata->reset_gpio); + for (i = 0; i < rfkill->gpio_cnt; i++) + gpio_free(rfkill->gpiolist[i]); if (rfkill->pwr_clk && PWR_CLK_ENABLED(rfkill)) clk_disable(rfkill->pwr_clk); if (rfkill->pwr_clk) @@ -214,12 +243,19 @@ static int rfkill_gpio_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id rfkill_gpio_of_match_table[] = { + { .compatible = "net,rfkill-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, rfkill_gpio_of_match_table); + static struct platform_driver rfkill_gpio_driver = { .probe = rfkill_gpio_probe, .remove = rfkill_gpio_remove, .driver = { .name = "rfkill_gpio", .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rfkill_gpio_of_match_table), }, }; diff --git a/net/rfkill/rfkill-regulator.c b/net/rfkill/rfkill-regulator.c index d11ac79246e4..d7ea8d236a53 100644 --- a/net/rfkill/rfkill-regulator.c +++ b/net/rfkill/rfkill-regulator.c @@ -14,6 +14,7 @@ #include <linux/module.h> #include <linux/err.h> +#include <linux/of_irq.h> #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> @@ -55,22 +56,50 @@ static struct rfkill_ops rfkill_regulator_ops = { .set_block = rfkill_regulator_set_block, }; +static struct rfkill_regulator_platform_data *rfkill_regulator_get_pdata_from_of(struct device *dev) +{ + struct rfkill_regulator_platform_data *pdata; + struct device_node *np = dev->of_node; + + if (!np) { + np = of_find_matching_node(NULL, dev->driver->of_match_table); + if (!np) { + dev_notice(dev, "device tree node not available\n"); + return ERR_PTR(-ENODEV); + } + } + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + dev_err(dev, "can't allocate platform data\n"); + return ERR_PTR(-ENODEV); + } + of_property_read_u32(np, "type", &pdata->type); + of_property_read_string(np, "name", &pdata->name); + return pdata; +} + static int rfkill_regulator_probe(struct platform_device *pdev) { struct rfkill_regulator_platform_data *pdata = pdev->dev.platform_data; + struct rfkill_regulator_platform_data *p = NULL; struct rfkill_regulator_data *rfkill_data; struct regulator *vcc; struct rfkill *rf_kill; int ret = 0; if (pdata == NULL) { - dev_err(&pdev->dev, "no platform data\n"); - return -ENODEV; + p = pdata = rfkill_regulator_get_pdata_from_of(&pdev->dev); + if (IS_ERR(p)) { + dev_err(&pdev->dev, "no platform data\n"); + return PTR_ERR(p); + } } if (pdata->name == NULL || pdata->type == 0) { dev_err(&pdev->dev, "invalid name or type in platform data\n"); - return -EINVAL; + ret = -EINVAL; + goto out; } vcc = regulator_get_exclusive(&pdev->dev, "vrfkill"); @@ -109,7 +138,7 @@ static int rfkill_regulator_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rfkill_data); dev_info(&pdev->dev, "%s initialized\n", pdata->name); - + kfree(p); return 0; err_rfkill_register: @@ -119,6 +148,7 @@ err_rfkill_alloc: err_data_alloc: regulator_put(vcc); out: + kfree(p); return ret; } @@ -135,12 +165,19 @@ static int rfkill_regulator_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id rfkill_regulator_of_match_table[] = { + { .compatible = "net,rfkill-reg" }, + { } +}; +MODULE_DEVICE_TABLE(of, rfkill_regulator_of_match_table); + static struct platform_driver rfkill_regulator_driver = { .probe = rfkill_regulator_probe, .remove = rfkill_regulator_remove, .driver = { .name = "rfkill-regulator", .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rfkill_regulator_of_match_table), }, }; diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index ea479388fb5c..07cce8e17e03 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -60,6 +60,33 @@ static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = { [SGTL5000_DAP_AVC_DECAY] = 0x0050, }; +u16 init_regs[] = { + SGTL5000_CHIP_CLK_CTRL, 0x0008, + SGTL5000_CHIP_I2S_CTRL, 0x0010, + SGTL5000_CHIP_SSS_CTRL, 0x0010, + SGTL5000_CHIP_DAC_VOL, 0x3c3c, + SGTL5000_CHIP_PAD_STRENGTH, 0x015f, + SGTL5000_CHIP_ANA_HP_CTRL, 0x1818, + SGTL5000_CHIP_ANA_CTRL, 0x0111, + SGTL5000_CHIP_LINE_OUT_VOL, 0x0404, + SGTL5000_CHIP_ANA_POWER, 0x7060, + SGTL5000_CHIP_PLL_CTRL, 0x5000, + SGTL5000_DAP_BASS_ENHANCE, 0x0040, + SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f, + SGTL5000_DAP_SURROUND, 0x0040, + SGTL5000_DAP_EQ_BASS_BAND0, 0x002f, + SGTL5000_DAP_EQ_BASS_BAND1, 0x002f, + SGTL5000_DAP_EQ_BASS_BAND2, 0x002f, + SGTL5000_DAP_EQ_BASS_BAND3, 0x002f, + SGTL5000_DAP_EQ_BASS_BAND4, 0x002f, + SGTL5000_DAP_MAIN_CHAN, 0x8000, + SGTL5000_DAP_AVC_CTRL, 0x0510, + SGTL5000_DAP_AVC_THRESHOLD, 0x1473, + SGTL5000_DAP_AVC_ATTACK, 0x0028, + SGTL5000_DAP_AVC_DECAY, 0x0050, +}; + + /* regulator supplies for sgtl5000, VDDD is an optional external supply */ enum sgtl5000_regulator_supplies { VDDA, @@ -112,6 +139,8 @@ struct sgtl5000_priv { int fmt; /* i2s data format */ struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; struct ldo_regulator *ldo; + struct clk *mclk; + int revision; }; /* @@ -809,7 +838,7 @@ static int ldo_regulator_register(struct snd_soc_codec *codec, { struct ldo_regulator *ldo; struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); - struct regulator_config config = { }; + struct regulator_config config = { .ena_gpio = -ENODEV }; ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); @@ -1214,9 +1243,7 @@ static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) { - u16 reg; int ret; - int rev; int i; int external_vddd = 0; struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); @@ -1242,24 +1269,11 @@ static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) /* wait for all power rails bring up */ udelay(10); - /* read chip information */ - reg = snd_soc_read(codec, SGTL5000_CHIP_ID); - if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != - SGTL5000_PARTID_PART_ID) { - dev_err(codec->dev, - "Device with ID register %x is not a sgtl5000\n", reg); - ret = -ENODEV; - goto err_regulator_disable; - } - - rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; - dev_info(codec->dev, "sgtl5000 revision 0x%x\n", rev); - /* * workaround for revision 0x11 and later, * roll back to use internal LDO */ - if (external_vddd && rev >= 0x11) { + if (external_vddd && sgtl5000->revision >= 0x11) { /* disable all regulator first */ regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), sgtl5000->supplies); @@ -1282,9 +1296,6 @@ static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) return 0; -err_regulator_disable: - regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), - sgtl5000->supplies); err_regulator_free: regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), sgtl5000->supplies); @@ -1404,28 +1415,128 @@ static struct snd_soc_codec_driver sgtl5000_driver = { .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), }; +static s32 sgtl5000_read16(struct i2c_client *client, u16 reg, u16 *val) +{ + int retry = 0; + int ret; + u8 buf[4]; + struct i2c_msg msgs[2]; + + while (retry++ < 3) { + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = buf; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = 2; + msgs[1].buf = buf; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret == 2) { + *val = (buf[0] << 8) | buf[1]; + return 0; + } + pr_err("%s: ret=%d reg=%x addr=%x\n", __func__, ret, reg, client->addr); + } + return (ret < 0) ? ret : -EIO; +} + +static s32 sgtl5000_write16(struct i2c_client *client, u16 reg, u16 val) +{ + int retry = 0; + int ret; + u8 buf[4]; + struct i2c_msg msgs[1]; + + while (retry++ < 3) { + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + buf[2] = val >> 8; + buf[3] = val & 0xff; + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 4; + msgs[0].buf = buf; + + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret == 1) + return 0; + pr_err("%s: ret=%d reg=%x addr=%x\n", __func__, ret, reg, client->addr); + } + return (ret < 0) ? ret : -EIO; +} + static int sgtl5000_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct sgtl5000_priv *sgtl5000; - int ret; + int ret, rev, i; + u16 reg; sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), GFP_KERNEL); if (!sgtl5000) return -ENOMEM; + sgtl5000->mclk = devm_clk_get(&client->dev, NULL); + if (IS_ERR(sgtl5000->mclk)) { + ret = PTR_ERR(sgtl5000->mclk); + dev_err(&client->dev, "Failed to get mclock: %d\n", ret); + /* Defer the probe to see if the clk will be provided later */ + if (ret == -ENOENT) + return -EPROBE_DEFER; + return ret; + } + + ret = clk_prepare_enable(sgtl5000->mclk); + if (ret) + return ret; + + /* read chip information */ + ret = sgtl5000_read16(client, SGTL5000_CHIP_ID, ®); + if (ret < 0) { + ret = -ENODEV; + goto disable_clk; + } + + if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != + SGTL5000_PARTID_PART_ID) { + dev_err(&client->dev, + "Device with ID register %x is not a sgtl5000\n", reg); + ret = -ENODEV; + goto disable_clk; + } + + rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; + dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); + sgtl5000->revision = rev; + + /* Restore regs back to power up conditions */ + for (i = 0; i < ARRAY_SIZE(init_regs); i += 2) + sgtl5000_write16(client, init_regs[i], init_regs[i+1]); + i2c_set_clientdata(client, sgtl5000); ret = snd_soc_register_codec(&client->dev, &sgtl5000_driver, &sgtl5000_dai, 1); + if (ret) + goto disable_clk; + return ret; + +disable_clk: + clk_disable_unprepare(sgtl5000->mclk); return ret; } static int sgtl5000_i2c_remove(struct i2c_client *client) { - snd_soc_unregister_codec(&client->dev); + struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); + snd_soc_unregister_codec(&client->dev); + clk_disable_unprepare(sgtl5000->mclk); return 0; } diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 99480fe77f4f..e26b8fcb07e0 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -443,10 +443,10 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream, if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | - SCR_TXFIFO_FSEL_IF8; + SCR_TXFIFO_FSEL_IF8 | SCR_VAL_CLEAR; mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | - SCR_TXFIFO_FSEL_MASK; + SCR_TXFIFO_FSEL_MASK | SCR_VAL_MASK; for (i = 0; i < SPDIF_TXRATE_MAX; i++) clk_prepare_enable(spdif_priv->txclk[i]); } else { |